JP3236235B2 - Toggle flip-flop - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

[0001] 1. Field of the Invention [0002] The present invention relates to a toggle flip-flop using a CMOS technology and used in a clock frequency dividing circuit.

[0002]

2. Description of the Related Art FIG. 5 is a circuit diagram showing a configuration example of a conventional toggle flip-flop.

In this conventional example, as shown in FIG. 5, an inverter 121 for inverting a clock signal CLK input from the outside and outputting it as an A signal, and inverting a signal output from the inverter 121 and outputting it as a B signal. And an externally input reset signal Res
an inverter 156 that inverts and outputs et, a signal output from the inverter 156 and an output signal of the entire circuit are input, a NAND gate 157 that outputs a signal obtained by inverting the logical product of the two, and a B signal is “ A transfer gate 141 for passing the signal output from the NAND gate 157 when the signal is 1 ";
1 or a signal that has passed through the transfer gate 142 and a signal output from the inverter 156, and outputs a signal obtained by inverting the logical product of the two.
58, an inverter 153 for inverting and outputting the signal output from the NAND gate 158, and the A signal being "1"
, The transfer gate 142 that allows the signal output from the inverter 153 to pass, the transfer gate 143 that allows the signal output from the NAND gate 158 to pass when the A signal is “1”, and the B signal is “ A transfer gate 144 for passing the signal output from the NAND gate 157 when the signal is 1 ";
Transfer gate 143 or transfer gate 1
And an inverter 154 that inverts the signal passed through the output 44 and outputs the inverted signal as an output signal of the entire circuit.

Hereinafter, the operation of the toggle flip-flop configured as described above will be described.

First, when a reset signal Reset is input from the outside, a signal "0" is output from the inverter 156, and the signal is input to one input terminal of each of the NAND gates 158 and 157.

Here, if a signal "0" is input to one input terminal of the NAND gate 158 and the signal "0" or "1" is input to the other input terminal, the NAND gate The signal output from 158 is
It becomes “1”. Similarly, when a signal “0” is input to one input terminal of the NAND gate 157 and the signal “0” or “1” is input to the other input terminal, the output from the NAND gate 157 is output. The signal
It becomes “1”.

Accordingly, when the A signal is "1",
In any case where the B signal is “1”, the signal input to the inverter 154 through the transfer gate 143 or the transfer gate 144 is “1”.
Becomes

When signal "1" is input to inverter 154, the input signal is inverted and output as signal "0".

After the reset operation is performed as described above,
The signal “1” output from the inverter circuit 156 and the signal “0” which is the output signal of the entire circuit are input to the NAND gate 157, and the signal “1” is output from the NAND gate 157.

Thereafter, when the clock signal CLK input from the outside rises (the clock signal is "1"), the signal "0" is output from the inverter 121, the A signal becomes "0", and the signal "0". Is the inverter 123
, And the signal “1” is output from the inverter 123 as a B signal.

When the signal A becomes "0" and the signal B becomes "1", the transfer gates 141 and 143 become inactive and the transfer gates 141 and 143 become inactive.
2, 144 are active.

Since transfer gate 144 is active, signal "1" output from NAND gate 157 passes through transfer gate 144,
Input to inverter 154. Since the transfer gate 143 is in the inactive state, a signal does not pass through the transfer gate 143.
Only the signal that has passed through the transfer gate 144 is input to the inverter 154.

When signal "1" is input to inverter 154, the input signal is inverted, signal "0" is output as an output signal and input to one input terminal of NAND gate 157.

Then, in the NAND gate 157,
A signal “1” obtained by inverting a logical product of the signal “0” output from the inverter 154 and the signal “1” output from the inverter 156 is output.

The signal "1" output from the NAND gate 157 again passes through the transfer gate 144 and is input to the inverter 154. Similarly, the signal "0" is output from the inverter 154 as an output signal.

Thereafter, when the clock signal falls (clock signal is "0"), signal "1" is output from inverter 121, signal A becomes "1", and signal "1" is input to inverter 123. And inverter 1
23 outputs a signal “0” as a B signal.

When the signal A becomes "1" and the signal B becomes "0", the transfer gates 142 and 143 are activated and the transfer gates 141 and 143 are activated.
144 enters the inactive state.

Here, before the clock signal falls, the signal "1" output from the inverter 156 and the signal "1" output from the NAND gate 157 are input to the NAND gate 158. Yes,
As a result, the signal “0” is output from the NAND gate 158, and the signal “1” is output from the inverter 153.

Since the transfer gate 143 is in the active state, the signal "0" output from the NAND gate 158 passes through the transfer gate 143,
Input to inverter 154. Since the transfer gate 144 is in an inactive state, only the signal that has passed through the transfer gate 143 is input to the inverter 154.

When signal "0" is input to inverter 154, the input signal is inverted, signal "1" is output as an output signal and input to one input terminal of NAND gate 157.

Further, since the transfer gate 142 is in the active state, the signal “1” output from the inverter 153 passes through the transfer gate 142 and is input to one input terminal of the NAND gate 158.

Here, the signal "1" output from the inverter 156 is input to the other input terminal of the NAND gate 158, whereby the signal "0" is output from the NAND gate 158.

Since transfer gate 143 is in the active state, signal "0" output from NAND gate 158 similarly passes through transfer gate 143, is input to inverter 154, and signal "1" is output from inverter 154. Is output as an output signal.

Thereafter, when the clock signal rises again (the clock signal is "1"), the signal "0" is output from the inverter 121, the signal A becomes "0", and the signal "0" is input to the inverter 123. And inverter 1
23 outputs a signal “1” as a B signal.

When the signal A becomes "0" and the signal B becomes "1", the transfer gates 142 and 143 become inactive and the transfer gates 14 and 143 become inactive.
1, 144 are activated.

In the NAND gate 157,
Since the signal “1” output from the inverter 156 and the signal “1” output from the inverter 154 are input, a signal “0” is output.

Since transfer gate 144 is active, signal "0" output from NAND gate 157 passes through transfer gate 144,
Input to inverter 154. Since the transfer gate 143 is in the inactive state, a signal does not pass through the transfer gate 143.
Only the signal that has passed through the transfer gate 144 is input to the inverter 154.

When signal "0" is input to inverter 154, the input signal is inverted, signal "1" is output as an output signal, and input to one input terminal of NAND gate 157.

Then, in the NAND gate 157,
A signal “0” obtained by inverting the logical product of the signal “1” output from the inverter 154 and the signal “1” output from the inverter 156 is output.

The signal "0" output from the NAND gate 157 again passes through the transfer gate 144 and is input to the inverter 154. Similarly, the signal "1" is output from the inverter 154 as an output signal.

Thereafter, when the clock signal falls again (clock signal is "0"), signal "1" is output from inverter 121, signal A becomes "1", and signal "1" is sent to inverter 123. Input and inverter 1
23 outputs a signal “0” as a B signal.

Thereafter, when the clock signal falls again (clock signal is "0"), signal "1" is output from inverter 121, signal A becomes "1", and signal "1" is sent to inverter 123. Input and inverter 1
23 outputs a signal “0” as a B signal.

When the signal A becomes "1" and the signal B becomes "0", the transfer gates 142 and 143 are activated, and the transfer gates 141 and 143 are activated.
144 enters the inactive state.

Here, before the clock signal falls, the signal “1” output from the inverter 156 and the signal “0” output from the NAND gate 157 are input to the NAND gate 158. Yes,
As a result, the signal “1” is output from the NAND gate 158, and the signal “0” is output from the inverter 153.

Since the transfer gate 143 is in the active state, the signal "1" output from the NAND gate 158 passes through the transfer gate 143,
Input to inverter 154. Since the transfer gate 144 is in an inactive state, only the signal that has passed through the transfer gate 143 is input to the inverter 154.

When signal "1" is input to inverter 154, the input signal is inverted, signal "0" is output as an output signal and input to one input terminal of NAND gate 157.

Since the transfer gate 142 is in the active state, the signal "0" output from the inverter 153 passes through the transfer gate 142 and is input to one input terminal of the NAND gate 158.

Here, the signal "1" output from the inverter 156 is input to the other input terminal of the NAND gate 158, whereby the signal "1" is output from the NAND gate 158.

Thereafter, since transfer gate 143 is in the active state, signal "1" output from NAND gate 158 similarly passes through transfer gate 143, is input to inverter 154, and signal "0" is output from inverter 154. Is output as an output signal.

As described above, the output signal is inverted each time the clock signal CLK input from the outside falls, whereby the input signal is divided and output.

FIGS. 6A and 6B are diagrams showing an example of a frequency dividing circuit comprising the toggle flip-flop shown in FIG. 5, wherein FIG. 6A is a diagram showing the configuration, and FIG. 6B is a timing chart.

As shown in FIG. 6, when a daisy chain is formed by N-stage toggle flip-flops 160-1 to 160-N, when a signal of frequency M is input from outside, one toggle flip-flop can Since the input signal is frequency-divided by 、, a signal of frequency M / ^2N is output from the toggle flip-flop 160-n at the last stage.

In the toggle flip-flop frequency dividing circuit as shown in FIG. 6, since the circuit configuration has a daisy chain structure, the state is stabilized when the signal input to the circuit changes. It takes a considerable amount of time (until the signal is completely propagated), but on the other hand, the circuit scale is smaller and the power consumption can be reduced compared to other frequency dividers of the same function. Because of the advantage of being able to do so, they are used in digital circuits that operate at relatively slow speeds, such as watches.

Here, in the above-described frequency dividing circuit, when the frequency dividing circuit is composed of N-stage toggle flip-flops, it is necessary to output a one-clock signal from the last-stage toggle flip-flop. Therefore, it is necessary to input a signal of 2 ^N clocks to the first-stage toggle flip-flop, which requires a long time (a large number of test patterns) in performing the test.

To avoid this, the output of the final stage is forcibly set to H by using a bypass circuit or a set reset signal.
A method of setting a high level and a low level to test a circuit (a circuit at a stage after the number of operations by using a frequency-divided signal) is used.

Japanese Patent Application Laid-Open No. 2-196520 proposes that the output of the last stage is forcibly set to the high level and the low level by using the set / reset signal. In testing the peripheral circuit body, a test pattern of 2 ^N clocks is required as before.

In a technology other than CMOS, Japanese Patent Application Laid-Open No. 4-334124 proposes using a signal through switching function of a toggle flip-flop to reduce the number of chip terminals. Cannot adapt.

[0048]

SUMMARY OF THE INVENTION In a frequency divider using a conventional toggle flip-flop as described above,
Since the toggle flip-flop itself has a function of dividing the input signal and outputting the divided signal, one clock pulse is generated in the N-th toggle flip-flop of the frequency dividing circuit including the N-stage toggle flip-flop. In order to generate it, it is necessary to input 2 ^{N + 1} clock signals.

For this reason, a test is performed on a circuit using a toggle flip-flop at the N-th stage of the frequency divider circuit or a toggle flip-flop at an intermediate stage thereof.
When confirming the operation of the entire frequency divider, there is a problem that a huge number of clock signals must be input.

The present invention has been made in view of the above-mentioned problems of the prior art, and an enormous number of clock signals are input to a frequency dividing circuit including N-stage toggle flip-flops. Without using the toggle flip-flop at the N-th stage or a toggle flip-flop at an intermediate stage, a test can be performed, and the operation of the entire frequency dividing circuit can be confirmed. The purpose is to provide.

[0051]

According to the present invention, there is provided a toggle flop having a first group of gates for dividing and outputting an externally input clock signal. A first circuit that generates and outputs a first signal and a second signal based on the control signal, and outputs the clock signal as it is,
Generating a third signal and a fourth signal based on the clock signal and the first signal, and outputting the third signal and the fourth signal to the first gate group; And the clock signal output from the second circuit and the first and second signals output from the first circuit are input, and input based on the first and second signals. A second clock signal for outputting the clock signal to the first gate group.
And a gate group based on the logic level of the control signal.
Wherein the first signal to the fourth signal have respective predetermined logics.
When the level becomes the level, the first gate group outputs the clock signal output from the second gate group without frequency division.

A frequency dividing circuit having a plurality of the toggle flip-flops, wherein a common control signal is input to the plurality of toggle flip-flops.

Further, the plurality of toggle flip-flops are divided into predetermined groups, and a common control signal is input to each of the groups.

(Operation) In the present invention configured as described above, an input clock signal is divided and output based on a control signal input from the outside, or output without being divided. Or be done.

In this manner, in the frequency dividing circuit composed of N-stage toggle flip-flops, a test is performed on a circuit using the N-th toggle flip-flop or a toggle flip-flop in the middle thereof, When checking the operation of the entire peripheral circuit, if a control signal is input so that the input clock signal is output as it is,
There is no need to input a huge number of clock signals to perform a test.

[0056]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is a functional block diagram of a toggle flip-flop according to an embodiment of the present invention.

In this embodiment, as shown in FIG. 1, a first circuit 10 for generating and outputting a first signal C and a second signal D based on a control signal TEST input from the outside, A second circuit 20 that outputs the input clock signal CLK as it is and generates and outputs a third signal A and a fourth signal B based on the input clock signal CLK and signal C; A second gate group 30 that receives the clock signal CLK output from the circuit 20 and the signals C and D output from the circuit 10 and outputs the input clock signal CLK based on the signals C and D; The clock signal CLK output from the circuit 30 and the signals A and B output from the circuit 20 are input, and based on the signals A and B, the frequency of the clock signal CLK input to the circuit 20 is divided and output. First gate group or outputs the clock signal CLK outputted from the over preparative group 30 4
0.

FIG. 2 is a circuit diagram showing an embodiment of the toggle flip-flop having the function shown in FIG.

In this embodiment, as shown in FIG. 2, a first inverter 11 which inverts a control signal TEST input from the outside and outputs it as a signal C, and a signal D which is obtained by inverting a signal output from the inverter 11 a second Lee <br/> inverter 12 to output as the clock signal CL is inputted from the outside
A third inverter 21 for inverting K, and an inverter 2
1 and the signal output from the inverter 11 are input, and a signal obtained by inverting the logical product of the two is A
A NAND gate 22 that outputs a signal, a fourth inverter 23 that inverts the signal output from the NAND gate 22 and outputs the signal as a B signal, an inverter 51 that inverts and outputs an output signal of the entire circuit, and a B signal Is “1”, the first transfer gate 41 and the second transfer gate 41 that pass the signal output from the inverter 51
A transfer gate 44 and a sixth gate for passing the signal output from the inverter 21 when the D signal is "1"
Of the transfer gate 32, the transfer gate 41
Alternatively, an inverter 52 that inverts and outputs a signal that has passed through the transfer gate 42 and a signal that is output from the inverter 52 when the A signal is “1” are passed.
A fourth transfer gate 43, an inverter 54 for inverting the signal passing through the transfer gate 43 or the transfer gate 44 and outputting the inverted signal as an output signal of the entire circuit, and an output from the inverter 52 when the C signal is "1" a fifth transfer gate 31 for passing the signal, an inverter 53 for inverting a signal passing through the transfer gate 31 or transfer gate 32, inverter 5 when a signal is "1"
And a third transfer gate 42 for passing the signal output from the third transfer gate 3 .

It should be noted that the circuit 10
And the inverters 21 and 23 and the NAND
The gate 20 forms the circuit 20, the transfer gates 31 and 32 form the gate group 30, and the transfer gates 41 to 44 form the gate group 40.

The operation of the toggle flip-flop configured as described above will be described below.

First, the operation in the normal mode, that is, when the control signal TEST is not input will be described.

When the control signal TEST is not input (the control signal TEST is "0"), a signal "1" is output from the inverter 11, and the C signal becomes "1".
The signal “1” is input to the inverter 12 and the inverter 1
2 outputs a signal “0” as a D signal.

When the C signal becomes "1" and the D signal becomes "0", the transfer gate 31 becomes active and the transfer gate 32 becomes inactive.

When the clock signal CLK input from the outside rises (the clock signal is “1”), the inverter 2
1 outputs a signal “0”, the signal “0” output from the inverter 21 and the signal “1” output from the inverter 11 are input to the NAND gate 22, and the signal “1” is output from the NAND gate 22 to A. While being output as a signal, the signal “1” is input to the inverter 23, and the signal “0” is output from the inverter 23 as a B signal.

When the signal A becomes "1" and the signal B becomes "0", the transfer gates 42 and 43 become active and the transfer gates 41 and 44 become inactive.

Here, as an initial state, the inverter 52
, The signal “1” is output from the inverter 52, and the signal “1” output from the inverter 52 passes through the transfer gate 43 and is input to the inverter 54 because the transfer gate 43 is in the active state. Since the transfer gate 44 is in an inactive state, only the signal that has passed through the transfer gate 43 is input to the inverter 54.

When the signal "1" is input to the inverter 54, the input signal is inverted, and the signal "0" is output as an output signal and input to the inverter 51.

Since the transfer gate 31 is in the active state, the signal “1” output from the inverter 52 passes through the transfer gate 31 and is input to the inverter 53. The transfer gate 3
Since 2 is in the inactive state, only the signal that has passed through the transfer gate 31 is input to the inverter 53.

When signal "1" is input to inverter 53, the input signal is inverted, and signal "0" is output from inverter 53.

Thereafter, as the transfer gate 42 is in the active state, the signal “0” output from the inverter 53 passes through the transfer gate 42 and is input to the inverter 52. Since the transfer gate 41 is in the inactive state, the inverter 52
, Only the signal passing through the transfer gate 42 is input.

Then, similarly, signal "1" is output from inverter 52.

Thereafter, when the clock signal falls (when the clock signal is "0"), the signal "1" is output from the inverter 21.
Is output, and the signal “1” output from the inverter 21 is output.
And the signal “1” output from the inverter 11 is NAN
The signal is input to the D gate 22, the signal "0" is output from the NAND gate 22 as the A signal, and the signal "0" is output.
Is input to the inverter 23, and the signal "1" is output from the inverter 23 as the B signal.

When the signal A becomes "0" and the signal B becomes "1", the transfer gates 42 and 43 become inactive and the transfer gates 41 and 4 become inactive.
4 becomes active.

Further, since signal "0" output from inverter 54 is input to inverter 51, signal "1" is output.

Since the transfer gate 44 is in the active state, the signal “1” output from the inverter 51 passes through the transfer gate 44 and is input to the inverter 54. Since the transfer gate 43 is in the inactive state, only the signal that has passed through the transfer gate 44 is input to the inverter 54.

When signal "1" is input to inverter 54, the input signal is inverted, and signal "0" is output as an output signal.

The signal output from the inverter 54 is input to the inverter 51, whereby the signal “1” is output from the inverter 51.

When the transfer gate 41 is in the active state, the signal “1” output from the inverter 51 passes through the transfer gate 41 and is input to the inverter 52. Since the transfer gate 42 is in the inactive state, only the signal that has passed through the transfer gate 41 is input to the inverter 52.

When signal "1" is input to inverter 52, the input signal is inverted, and signal "0" is output from inverter 52.

Thereafter, when the clock signal rises again (the clock signal is "1"), the signal "0" is output from the inverter 21, and the signal "0" output from the inverter 21 and the signal "0" output from the inverter 11 are output. 1 is input to the NAND gate 22, the signal "1" is output from the NAND gate 22 as the A signal, the signal "1" is input to the inverter 23, and the signal "0" is output from the inverter 23 as the B signal. Is output.

When the signal A becomes "1" and the signal B becomes "0", the transfer gates 42 and 43 become active and the transfer gates 41 and 44 become inactive.

Since transfer gate 43 is active, signal “0” output from inverter 52 passes through transfer gate 43 and is input to inverter 54. The transfer gate 44
Are in an inactive state, only the signal that has passed through the transfer gate 43 is input to the inverter 54.

When signal "0" is input to inverter 54, the input signal is inverted, and signal "1" is output as an output signal and input to inverter 51.

Since the transfer gate 31 is in the active state, the signal “0” output from the inverter 52 passes through the transfer gate 31 and is input to the inverter 53. The transfer gate 3
Since 2 is in the inactive state, only the signal that has passed through the transfer gate 31 is input to the inverter 53.

When signal "0" is input to inverter 53, the input signal is inverted, and signal "1" is output from inverter 53.

After that, since the transfer gate 42 is active, the signal “1” output from the inverter 53 passes through the transfer gate 42 and is input to the inverter 52. Since the transfer gate 41 is in the inactive state, the inverter 52
, Only the signal passing through the transfer gate 42 is input.

Then, similarly, signal "0" is output from inverter 52.

Thereafter, when the clock signal falls again (the clock signal is "0"), the signal "1" is output from the inverter 21, and the signal "1" output from the inverter 21 and the signal output from the inverter 11 are output. "1" is input to the NAND gate 22, the signal "0" is output from the NAND gate 22 as the A signal, the signal "0" is input to the inverter 23, and the signal "1" is output from the inverter 23 to the B signal. Is output as

When the signal A becomes "0" and the signal B becomes "1", the transfer gates 42 and 43 become inactive and the transfer gates 41 and 4 become inactive.
4 becomes active.

Inverter 51 receives signal "1" output from inverter 54, and therefore outputs signal "0".

Since the transfer gate 44 is in the active state, the signal “0” output from the inverter 51 passes through the transfer gate 44 and is input to the inverter 54. Since the transfer gate 43 is in the inactive state, only the signal that has passed through the transfer gate 44 is input to the inverter 54.

When signal "0" is input to inverter 54, the input signal is inverted, and signal "1" is output as an output signal.

The signal output from the inverter 54 is input to the inverter 51, and similarly,
Inverter 51 outputs signal “0”.

Thus, the output signal is inverted every time the clock signal CLK input from the outside rises, whereby the input signal is divided and output.

Next, the operation in the test mode, that is, when the control signal TEST is input will be described.

When control signal TEST is input (control signal TEST is “1”), signal “0” is output from inverter 11, signal C becomes “0”, and signal “0” is output from inverter 12. Input to the inverter 12
Outputs a signal "1" as a D signal.

When the C signal becomes "0" and the D signal becomes "1", the transfer gate 31 becomes inactive and the transfer gate 32 becomes active.

Since signal "0" is outputted from inverter 11, signal "1" is always outputted from NAND gate 22, whereby signal A becomes "1" and signal B becomes 0.

When the signal A becomes "1" and the signal B becomes "0", the transfer gates 41 and 44 become inactive and the transfer gates 42 and 4 become inactive.
3 becomes active.

When the clock signal CLK input from the outside rises (clock signal is “1”), the inverter 2
1 outputs a signal "0".

Since transfer gate 32 is in the active state, signal “0” output from inverter 21 passes through transfer gate 32 and is input to inverter 53. Since the transfer gate 31 is in the inactive state, only the signal that has passed through the transfer gate 32 is input to the inverter 53.

When signal “0” is input to inverter 53, the input signal is inverted, and signal “1” is output from inverter 53.

Since the transfer gate 42 is active, the signal “1” output from the inverter 53 passes through the transfer gate 42 and is input to the inverter 52. Since the transfer gate 41 is in the inactive state, the inverter 52
, Only the signal passing through the transfer gate 42 is input.

When signal "1" is input to inverter 52, the input signal is inverted, and signal "0" is output from inverter 52.

Since the transfer gate 43 is active, the signal “0” output from the inverter 53 passes through the transfer gate 43 and is input to the inverter 54. Since the transfer gate 44 is in an inactive state, the inverter 54
, Only the signal that has passed through the transfer gate 43 is input.

When signal "0" is input to inverter 54, the input signal is inverted, and signal "1" is output as an output signal.

Thereafter, when the clock signal CLK input from the outside falls (the clock signal is "0"), the signal "1" is output from the inverter 21.

Since the transfer gate 32 is active, the signal “1” output from the inverter 21 passes through the transfer gate 32 and is input to the inverter 53. Since the transfer gate 31 is in the inactive state, only the signal that has passed through the transfer gate 32 is input to the inverter 53.

When signal "1" is input to inverter 53, the input signal is inverted, and signal "0" is output from inverter 53.

Since the transfer gate 42 is in the active state, the signal “0” output from the inverter 53 passes through the transfer gate 42 and is input to the inverter 52. Since the transfer gate 41 is in the inactive state, the inverter 52
, Only the signal passing through the transfer gate 42 is input.

When signal "0" is input to inverter 52, the input signal is inverted, and signal "1" is output from inverter 52.

Since the transfer gate 43 is active, the signal “1” output from the inverter 53 passes through the transfer gate 43 and is input to the inverter 54. Since the transfer gate 44 is in an inactive state, the inverter 54
, Only the signal that has passed through the transfer gate 43 is input.

When signal "1" is input to inverter 54, the input signal is inverted and signal "0" is output as an output signal.

As described above, in the test mode, the input clock signal is output without being divided.

FIG. 3 is a diagram showing an embodiment of a frequency dividing circuit comprising the toggle flip-flop shown in FIG.
(A) is a diagram showing a configuration, and (b) is a timing chart.

As shown in FIG. 3, in the present embodiment, an N-stage toggle flip-flop 60 constituting a frequency dividing circuit is provided.
-1 to 60-N are respectively provided with the control signal T shown in FIG.
A terminal to which EST is commonly input is provided.

In the frequency dividing circuit configured as described above, a test is performed on a circuit using a toggle flip-flop at the N-th stage of the frequency dividing circuit or a toggle flip-flop at an intermediate stage. When confirming the operation of the entire frequency dividing circuit, by inputting a high-level signal to the control signal TEST, a test can be performed based on the timing of the input clock signal. By inputting a low level signal to the control signal TEST, the input clock signal can be divided and output.

When the input clock signal is used as it is in the toggle flip-flop of the N-th stage, the input clock signal can be input by inputting a high-level signal to the control signal TEST as in the case of performing the test. The signal can be propagated to the N-th toggle flip-flop without dividing the frequency.

FIGS. 4A and 4B are diagrams showing another embodiment of the frequency dividing circuit comprising the toggle flip-flop shown in FIG. 2, wherein FIG. 4A is a diagram showing the configuration and FIG. 4B is a timing chart.

As shown in FIG. 4, three lines for applying the control signal TEST to each of the six stages of toggle flip-flops 61-1 to 61-6 forming the frequency dividing circuit are provided.
And the flip-flops 60-1 to 60-6
0-6 may be connected every other stage and divided into three types of test groups. The number of groups may always be three, regardless of the number of frequency division stages.

By sequentially inputting the high level of the control signal TEST test signal to these three wirings, it is possible to transfer data while confirming the operation of each toggle flip-flop and to confirm the operation. Is the same as the number of used toggle flip-flops.

[0124]

As described above, in the present invention,
Since the input clock signal is divided and output based on a control signal input from the outside, or is output as it is without being divided, a frequency dividing circuit including N-stage toggle flip-flops In this case, it is possible to perform a test on a circuit using a toggle flip-flop at the N-th stage or a toggle flip-flop at an intermediate stage without inputting an enormous number of clock signals. Operation can be confirmed.

[Brief description of the drawings]

FIG. 1 is a functional block diagram of a toggle flip-flop according to an embodiment of the present invention.

FIG. 2 is a circuit diagram showing one embodiment of a toggle flip-flop having the function shown in FIG.

3A and 3B are diagrams showing an embodiment of a frequency dividing circuit including the toggle flip-flop shown in FIG. 2, wherein FIG. 3A is a diagram showing a configuration and FIG. 3B is a timing chart.

4A and 4B are diagrams showing another embodiment of the frequency dividing circuit including the toggle flip-flop shown in FIG. 2, wherein FIG. 4A is a diagram showing a configuration and FIG. 4B is a timing chart.

FIG. 5 is a circuit diagram showing a configuration example of a conventional toggle flip-flop.

6A and 6B are diagrams illustrating an example of a frequency dividing circuit including the toggle flip-flop illustrated in FIG. 5, in which FIG. 6A is a diagram illustrating a configuration, and FIG. 6B is a timing chart.

[Explanation of symbols]

10, 20 circuit 11, 12, 21, 23, 51 to 54 inverter 22 NAND gate 30, 40 gate group 31, 32, 41 to 44 transfer gate 60-1 to 60-n, 61-1 to 61-6 toggle flip-flop Step CLK Clock signal TEST Control signal

Continuation of the front page (58) Field surveyed (Int. Cl. ⁷ , DB name) H03K 21/00 H03K 23/00 H03K 3/00

Claims (5)

(57) [Claims] 1. A toggle flop having a first gate group for dividing and outputting a clock signal input from the outside, wherein the first signal and the second signal are based on a control signal input from the outside. a first circuit for generating and outputting, while it outputs the clock signal to generate a third signal and a fourth signal based on said clock signal and said first signal, third A second circuit for outputting a second signal and a fourth signal to the first gate group, and a clock signal output from the second circuit and the first signal.
The first and second signals output from the circuit are input,
A second gate group that outputs an input clock signal to the first gate group based on the first and second signals, and the second gate group based on a logic level of the control signal. 1 signal
When the fourth signal reaches the predetermined logic level,
The toggle flip-flop , wherein the first group of gates outputs the clock signal output from the second group of gates without dividing the clock signal. 2. The toggle flip-flop according to claim 1, wherein the first signal is a signal obtained by inverting the control signal, and the second signal is a signal obtained by inverting the first signal. The third signal is a signal obtained by inverting the logical product of the signal obtained by inverting the clock signal and the first signal, and the fourth signal is a signal obtained by inverting the third signal. A toggle flip-flop, comprising: 3. A toggle according to claim 1 or claim 2.
In the flip-flop, the first circuit inverts the control signal and outputs the inverted signal as the first signal
A first inverter, and inverting a signal output from the first inverter to
And a second inverter that outputs the second signal.
The second circuit includes a third inverter for inverting the clock signal, a signal output from the third inverter, and the first inverter.
The signal output from the inverter is input and the logic
N which outputs a signal whose product is inverted as the third signal
An AND gate, and inverting a signal output from the NAND gate,
And a fourth inverter that outputs a fourth signal, wherein the first gate group outputs the entire circuit when the fourth signal is “1”.
And second transfer for passing a signal obtained by inverting
And the second gate when the third signal is “1”.
The third to output the inverted signal and output the inverted signal
A transfer gate, and when the third signal is "1", the first or the first signal
Passes through the third transfer gate and passes the inverted signal
With the fourth transfer gate, The signal passing through the second or fourth transfer gate
Inverter that inverts the signal to output the entire circuit And
The second group of gates, when the first signal is “1”,
Passes through the third transfer gate and passes the inverted signal
A fifth transfer gate to pass through, and the third input when the second signal is "1".
Sixth transformer for passing the signal output from the barter
And a toggle flip having a fagate.
Flop. 4. A frequency divider comprising a plurality of toggle flip-flops according to claim 1, wherein a common control signal is input to said plurality of toggle flip-flops. A frequency dividing circuit. 5. A frequency divider comprising a plurality of toggle flip-flops according to claim 1, wherein said plurality of toggle flip-flops are divided into predetermined groups. And a common control signal is input to each of the groups.