JPS6149713B2 - - Google Patents

Description

[Detailed description of the invention]

The present invention relates to a compound computer system. Large-capacity data processing, for example, processing of image data input from a camera sensor, is performed by an array processor or a tightly coupled multiprocessor (Ministry of International Trade and Industry; Proceedings of the Research and Development Results Conference). However, each system has the characteristics of a dedicated machine for performing specific calculations at high speed, and the number of processors cannot be increased or decreased in accordance with system requirements. It also has the disadvantage of increasing the overall scale.
Furthermore, in terms of speed, it is about 5 to 10 times the processing capacity of a processor (CPU) alone, and higher speeds cannot be achieved. An object of the present invention is to provide a complex computer system that has a simple equipment configuration and is highly flexible as a system. The gist of the present invention is to configure the computer in a hierarchical relationship (1:N:1) from the upper level computer to the middle level and lower level computers,
Another advantage is that the configuration includes a random access memory. Furthermore, the memory can be driven using a multi-access method. FIG. 1 is a diagram showing an embodiment of a compound computer system of the present invention. In this embodiment, one parent CPU or MPU (hereinafter referred to as P
- CPU) 1, n child MPUs (hereinafter referred to as C-MPU)) 4, 5, 6......, 7,
One grandchild CPU or MPU (hereinafter referred to as GC-MPU) 10 is used.
Note that MPU means microprocessor. P-CPU1 is data from plant 11
Import DATA. The plant 11 is a production facility, and basic data such as material flow and robot control is obtained from a television camera installed in the production facility. Imaging data from such a television camera (generally a sense camera) is the data DATA disclosed as being transferred from the plant 11 to the P-CPU 1. This data DATA
are processed for various types of control and monitoring.
This process is as follows: P-CPU1→C-MPU4~7→GC
- Executed via the CPU 10. The RAM 2 is a random access memory interposed between the P-CPU 1 and the C-MPUs 4 to 7, and is divided into a plurality of blocks A ₁ , A ₂ , A ₃ , . . . , A _o . This number of blocks is the same as the number of C-MPUs, and has a one-to-one correspondence with each other. ram8 is C-MPU4,5,...7 and GC-
It is a random access memory interposed between the CPU and multiple blocks a ₁ , a ₂ , a ₃ , ......, a
Consists of _o . Each block has a one-to-one correspondence with an individual C-MPU. n registers (R1, R2, R3,......R
_o ) 3 is each block A ₁ , A ₂ , A ₃ ,... of RAM2.
..., A _o , and each C-MPU4, 5, 6, ...
..., 7. n registers (r1, r2, r3, ......, rn) 9 are used by n C-MPUs 4, 5, 6, ......, 7 and n registers (r1, r2, r3, ......, rn) 9
They are installed corresponding to blocks a ₁ , a ₂ , a ₃ , . . . , a _o of ram8. Each register of register 3
R ₁ (where i=1, 2, . . . , n) is set to “1” when the corresponding data DATA has been stored in the corresponding block A ₁ of the RAM 2. register
When _R1 is "1", access to the corresponding block _A1 in RAM2 is performed by the i-th C-MPU, and when register _R1 is "0", RAM2 is accessed by the i-th C-MPU.
Access to the corresponding block _A1 is made by the P-CPU. That is, when R ₁ = 1, A ₁ of RAM2 is under the control of the i-th C-MPU, and R ₁ = 0.
At this time, _A1 of RAM2 comes under the control of the P-CPU. The above matters regarding register 3 are as follows: Register 9
The same holds true for . That is, r ₁ of register 9
When r 1 =1, a ₁ of ram8 is under the control of the GC-CPU 10, and when r ₁ =0, a ₁ of ram8 is under the control of the i-th C-MPU. Register 3 is set by register controller 4.
6 and the setting of register 9 is done by C-
It is done by MPU. The register controller 46 is controlled by the P-CPU1. The registers 3 and 9 are initially reset by the P-CPU 1. Printing device 40, CRT 42, external storage device 44
is placed under the control of the GC-CPU 10 and performs necessary input/output. The plant 11 receives the processing results from the GC-CPU 10 via feedback and takes necessary actions. Access to the RAM 2 by the P-CPU 1 and C-MPU is performed using the Malmö access control method. Similarly, access to RAM8 by the C-MPU and GC-CPU is performed using the multi-access control method. Explain the operation. Image data DATA from the plant 11 is taken into the P-CPU 1 which is a host computer. P-CPU1 uses this imported data
DATA is sequentially stored in corresponding blocks A ₁ to A _o of RAM2. In Figure 2, from plant 11 to P-
An example of a data transfer procedure to the CPU 1 is shown. On the plant 11 side, an input request IRQ is generated to the P-CPU 1 upon establishment of data DATA.
The figure shows a case where an IRQ occurs t ₀ hours after data establishment. When this IRQ occurs, P-CPU
If the reception OK signal RV is generated from 1, P-
CPU1 operates the receiving program and sends
Start receiving DATA. P-CPU1 is data
When DATA is received, the data DATA 18 is sequentially stored in corresponding blocks of RAM 2 determined in advance. Note that 17 is a tag signal including an address. The correspondence between the structure of the image data DATA and each block of the RAM 2 will be explained with reference to FIGS. 3 and 4. FIG. 3 shows an example of the structure of image data. It consists of 1024 bits vertically and horizontally, and each bit forms a pixel. Each pixel can take binary information of "1" or "0". This image data is scanned line by line, scanned line by line from left to right, and taken into the P-CPU 1. Once the first line has been captured, the second line is followed by the third line, and so on until the final line is captured. Here, 16 C-MPUs
This section describes the case of distributed processing. RAM
Each block of 2 consists of the same capacity, and the 1024 lines are evenly divided into 16. Therefore, each block has 64
Consists of lines. That is, pixel data from the 1st line to the 64th line is stored in block _A1 of the RAM 2, and then pixel data from the 65th line to the 128th line is stored in block _A2 . Similarly, the final block A ₁₆ includes 1024 lines from the 961st line.
Line pixel data is stored. Through the above process, all image data for one screen is stored in each block of RAM2. FIG. 4 shows how data is stored in the RAM 2 when the data is divided into 16 blocks. Register 3 displays the occupied state of data in RAM 2, and is set by register controller 46. register control 46
has the function of taking in the access address from the P-CPU 1 to the RAM 2, and sequentially setting each element _R1 of the register 3 to "1" every time this address indicates 64 lines. That is, when data writing starts from the first line and an address corresponding to the end of the 64th line is detected, the register control 46 sets element R1 to " ₁ ". element R ₁
When “1” is set to “1”, C-MPU4
block _A1 can be placed under management, and the C-MPU 4 can independently process the data in block _A1 . Next, data from line 65 to line 128 is written to block A2.
When the end of the 128th line is detected by the register controller 46, the register controller 46 sets element _R2 of register 3 to "1". Under this condition, block _A2 is placed under the control of C-MPU 5, and C-MPU 5 can perform independent processing of the data within block _A2 . Thereafter, similar processing is performed sequentially up to the 16th block _Ao , element _R0 is set to "1", and data processing in block _Ao is performed under the control of C-MPUn. The RAM 2 can be accessed from both the P-CPU 1 and the C-MPU, and an example of switching control is shown in FIG. The figure shows an example of switching access (management) to block _A1 . P-CPU1
and C-MPU 4 interface to block A ₁ via multi-access controller 100 . Multi access controller 100
is P-CPU1 while data is being stored in block _A1 .
and block _A1 . After storing the data, the C-MPU 4 and block _A1 are interfaced. In the figure, data is DATA to be processed, and control signals include an address and its tag signal. The operation goes through the steps of writing data from the P-CPU 1 to the block A ₁ and, after the writing is completed, reading and transferring the data from the block A ₁ to the C-MPU 4. The above figure 5 shows the interface for block _A1 , but other blocks _A2 , _A3 ,...
. . . etc., there is a similar relationship between the P-CPU1 and the C-MPU. Furthermore, each block a ₁ , a ₂ , a ₃ , ... of RAM8 is also connected to each C-MPU.
A similar multi-access controller intervenes between the GC and the CPU and plays the same role. The P-CPU 1 performs initial processing in response to the initial signal INITL from the line 12. FIG. 6 shows a flowchart of initial processing. By starting the initial INITL, the write address to the RAM 2 is initialized, and then the external registers 3 (R1 to Rn) and 9 (r1 to rn) are reset. Furthermore, the C-MPUs 4 to 7 are reset and enter a no-operation state (NOOP) to stand by. FIG. 7 shows a flowchart of data acquisition processing after receiving an input request IRQ in the P-CPU 1. The data is fetched in units of 1 byte, and the data is stored in the corresponding block of RAM2. Then, the address is updated, the interrupt is canceled, and the next input request IRQ interrupt is generated. Note that the flow in Figure 7 is an example in which data is transferred in 1-byte units and interrupts are canceled, but interrupts are canceled every time more than 1 byte of data is transferred, such as 1 line or the entire screen. It may be a system configuration. In addition to the above processing, the P-CPU 1 has a function of resetting the registers 3 and 9. Furthermore, G.C.
- Has a function to reset the CPU and C-MPU. The reset signals 15 and 16 correspond to this. FIG. 8 is a diagram showing the operation flow of each C-MPU. Each C-MPU is initialized by a reset command from P-CPU1. That is, the read address of RAM2 and the write address of write RAM8 are initialized. Furthermore, the external register R _n (where m=1, 2, . . . ) is reset. The above process is the initial processing, and then the processing moves to the loop logic. In the loop logic, it is checked whether "1" is set in the corresponding register _Rn , and if "1" is set,
The C-MPUm reads the contents of the m-th block A _n of the RAM 2 corresponding to the register R _n and performs predetermined data processing. After data processing, save the results to ram8
When writing to this block is completed, the mth register element r of register 9 is written.
Set _n to “1”. Next, the read RAM address is initialized, the write RAM address is initialized, and the process returns via a loop. At this time, m=m+1, and after reading and processing for the next (m+1)th block A _(n+1) , and then writing to the (m+1)th block a _n+1 of ram8. , (m+
1) The procedure up to storing the block in RAM is completed. Thereafter, the same procedure is performed until the final block is reached. At the end of this series of steps, the processed results for each block are
It is stored in all corresponding blocks of RAM 8, and "1" is set in each register element of register 9 every time each block is completed. The GC-CPU 10 reads the contents of the ram 8 and performs predetermined processing while monitoring whether the register element r of the register 9 is set to "1". FIG. 9 shows the processing flow in the GC-CPU 10. First, prior to processing, it is reset and initialized by the P-CPU 1. Next, each register element r1, r2, ......, rm of the external register 9
It is sequentially checked to see if "1" is set for each register element, and when "1" is set, the contents of the RAM block corresponding to that register element are read out and data processing is performed. Upon completion of data processing, the current register element is reset by signal 36. For example, if register r1 is set to "1", the corresponding block _a1 of ram8 is set.
The GC-CPU 10 accesses, reads the contents, performs predetermined data processing, and resets the register r1 after completing the data processing. According to the above embodiment, the GC-CPU10 has RAM8
The data stored in and the data to be stored are processed image by image. The processing results are sent to the printing device 40, CRT 42, and storage device 44 for recording. Furthermore, it is sent to the plant 11 and controlled or operated according to the processing results. From data transmission from plant 11 to GC-CPU
A time chart leading to the processing within 10 is shown in FIG. Although the movement of the entire time chart is clear from the explanation of the drawings from FIG. 1 to FIG. 9, it will be briefly explained again. First, P-CPU1 receives data DATA from plant 11, and RAM2
The blocks A ₁ , A ₂ , . . . are stored in order. Upon completion of data storage in all areas of each block, the corresponding register element R of register 3 is set to "1". The C-MPU confirms that “1” is set in register element R and takes appropriate action.
The contents of a block in RAM are read out, predetermined processing is performed, and the processing results are stored in the corresponding block in RAM8. This MPU processing is performed across all MPUs. Each time data storage is completed in a block of RAM, the corresponding register element r of register 8 is set to "1". GC-CPU10 operates on the condition that “1” is set in the register element of register 8.
Reads the contents of ram and processes the data. In the diagram,
Although the description focuses on block A ₁ , the same applies to blocks A ₂ and so on, and the overall operation is as described above. Explain processing time. FIG. 11 is a systematic diagram of processing time in this embodiment. In the figure, t _x is P−CPU
The processing time for one screen of 1, t _y is the final stage C-
The processing time of the MPU 7, _tz , is the processing time of the GC-CPU 10 driven by the C-MPU 7 at the final stage. Therefore, the total processing time T for one screen is T=t _x +t _y +t _z (1). On the other hand, when the same processing is performed by a single computer, the processing time T ₀ is T ₀ =t _x +n·t _y +n·t _z (2). However, n corresponds to the number of blocks. Comparing the two, in this embodiment, the time is shortened by the amount corresponding to the number n. In particular, (t _y + t _z )≫
At the time of t _x , T=1/nT ₀ (3), and the processing time can be reduced to 1/n. still,
The condition for (t _y +t _z )≫t _x is generally t _y ≫t _x >t _z
This is a condition that can be derived because of the relationship. Next, an example will be described in which the plant 11 is used as a production equipment plant and is applied to automatic sorting of conveyed items on a conveyor line. FIG. 12 shows conveyor lines 103 that cross each other at right angles, a conveyed object 108 is placed on the lines, and conveyor lines 103A, 1 in one of three directions are placed on the table 101 at the crossing point.
Sorting into whether to transport to 03B or 103C is automatically performed. This automatic sorting is directly performed by the conveyor branching device 104. That is, the command 51 for sorting in which direction is sent to the GC-CPU.
The conveyor branching device 104 receives the transfer from the conveyor 10 and operates the arm 104A to place the conveyed object 108 on the table 101 onto the conveyor line in the sorting command direction. This completes the sorting. The command 51 is the GC-CPU 10 in the embodiment of FIG.
given by. The data on which this command is based is the state on the table 101 captured by the camera sensor 105. Camera sensor 105
takes an image of the table 101 and sends the imaged data via the camera interface 106 to the P-
Send to CPU1. Camera interface 106
has the function of managing the transmission order of interrupt IRQ and data DATA for input requests to the P-CPU 1, and transmitting them to the P-CPU 1. P-CPU1 is data DATA
The operation after receiving is the same as in the embodiment shown in FIG. The processing in the path from the P-CPU 1 to the GC-CPU 10 in FIG. 1 is processing for pattern recognition of the conveyed object 108. FIG. 13 shows a typical example of pattern recognition. Inlet conveyor line 10
Various objects 108 are placed on top of the conveyor belt 3 . In the figure, 3
Seed conveyances 108A, 108B, and 108C are shown. These conveyed items are once placed on the table 101.
The conveyed object is placed on the table, and the camera sensor 105 photographs the conveyed object from directly above the table. On the other hand, the computer knows in advance which conveyance items are to be sorted to which output line, and the sorting destination is determined according to the pattern recognition results. In the figure, the conveyed object 108A is on the line 103A, and the conveyed object 108
B is transported to the line 103B, and the transported object 108C is transported to the line 103C. Pattern recognition of the transported object 108 will be described.
FIG. 14 shows an example of pattern recognition of the transported object 108A. The transported object 108A on the imaging screen 111 is
Patterns SX and SY are obtained by projecting in the X-axis and Y-axis directions that are perpendicular to each other. In the pattern SX, the distance from the origin to the pattern center point is X ₀ , the peak frequency Xh _nax , and the minimum frequency Xh _nio . Similarly, the pattern SY is y ₀ , Yh _nax ,
It has the value Yh _nio . If each of these three elements can be detected, the conveyed object can be determined to be 108A.
FIG. 15 is an example of the transported object 108D, and the 14th
Similar to the figure, x ₀ , y ₀ , Xh _nax , Yh _nax , Xh _nio ,
By detecting the element Yh _nio , the transported object 1
08D can be determined. Figure 16 shows the conveyed object 108D.
This is a case where
The degree of inclination and the fact that the transported object is 108D can be recognized. The above-described projection of the pattern in the X-axis direction and Y-axis direction, that is, the frequency addition process can also be accomplished by a single computer. In this embodiment, this statistical processing is achieved by the embodiment shown in FIG. The details will be explained below. (1) Regarding data processing within C-MPU. Within each C-MPU, the data within the block in the corresponding RAM 2 is read out and the following statistical processing is performed. That is, the total frequency value yh(k) of the k-th line is calculated. This becomes the following formula. becomes. However, j is the pixel number of each line, yk(j)
is the pixel information (binary information) of the j-th pixel of the k-th line. Since there are 64 lines in each block, equation (3) is calculated for the 64 blocks unique to each block. As a result, 64 total frequency values are obtained for each block, and these values are stored in the corresponding block in ram8. Furthermore, for each block, the frequency summary value of the j-th column
Find Xh ₁ (j). this is, becomes. However, xj(k) is the kth pixel information in the j column, _k1 is the start line number of the block, and _k2
is the final line number. The number of data obtained by formula (5) is 1024, and this data is also RAM8
is stored in the corresponding block within. (2) Regarding data processing within the GC-CPU. Statistical processing by data processing within the GC-CPU consists of calculating the frequencies for the entire screen for the columns determined by equations (4) and (5). The aggregated frequency values in the column direction are
If Xh(j), becomes. here,

[Formula] indicates the total value of the i-th and earlier blocks. Since the aggregation in the line direction is completed by the C-MPU, no new arithmetic processing is necessary. The GC-CPU also performs the work of extracting features from the thus obtained data in the line direction and column direction and the work of comparing them. It goes without saying that the feature extraction and comparison algorithms vary depending on the target pattern. The above example was an example of production equipment, but
General image data can be processed in the same way. Also, P-CPU and C-
The MPU and GC-CPU can generally be regarded as computers, and therefore the main memory and the like may be omitted from the drawing. In addition, when expanding the system,
This can be easily achieved by adding memory in block units, adding C-MPU, and adding software functions to P-CPU and GC-CPU. The scale of the system can also be reduced by reducing the corresponding processor and memory. Further, although the register control is provided externally in the embodiment, it can be removed by providing the function in software in the P-CPU instead. According to the present invention, data processing can be performed at a high processing speed by using a compound computer system with a 1:N:1 hierarchical structure. In particular, since microprocessors (microcomputers) are becoming smaller in size, there will be no significant increase in equipment costs. Furthermore, in the present invention, the C-MPU can be completely replaced, and the system can be expanded, reduced, and changed freely.

[Brief explanation of the drawing]

Fig. 1 is an embodiment of the present invention, Fig. 2 is a time chart, Fig. 3 is a screen diagram, Fig. 4 is a diagram showing the relationship between image data and memory, and Fig. 5 is a diagram showing multi-access. Example diagrams, Figures 6 and 7 are P-
Flowchart of CPU, Figure 8 is a flowchart of C-MPU, Figure 9 is a flowchart of GC-CPU, Figures 10 and 11 are time charts, and Figure 12 is a diagram showing an example of a production equipment plant. , 1st
3, FIG. 14, FIG. 15, and FIG. 16 are diagrams showing the relationships between different transported objects and their projected total values. 1...P-CPU, 2...RAM, 4-7...C
-MPU, 8...ram, 3, 9...register, 1
0...GC-CPU, 11...Plant.

Claims (1)

[Claims] 1. An upper processor, N intermediate processors, a lower processor, interposed between the upper processor and N intermediate processors, and divided into N blocks. a first RAM having N blocks, each block corresponding to each of the N intermediate processors;
The processor is interposed between a middle-level processor and a lower-level processor, and is divided into N blocks, with each block corresponding to each of the N middle-level processors. a second RAM with
The data is distributed sequentially to each block of the first RAM, and the N intermediate processors distribute data to each block of the first RAM.
The configuration is such that each processor processes the data in each block of RAM, stores the processing results in each corresponding block of the second RAM, and the lower processor processes the data of the second RAM for all blocks. Composite computer system. 2. A first register is provided for each block of the first RAM to indicate whether or not each of the middle N processors can be used.
A second register is provided to indicate whether or not a lower processor can be used for each block of the first and second blocks.
2. The multifunction computer system according to claim 1, wherein the processor access is executed by checking the contents of the second register.