JPS61233869A - Picture processor - Google Patents

Abstract

PURPOSE:To execute a local picture operation in high speed by revamping a DMA controller so as to be connected to a general-purpose computer bus. CONSTITUTION:The picture processing DMA controller is connected to the bus B via a bus 1. A picture processing DMA controller is of bus-slave configuration and receives a parameter relating to data transfer, kind of local operation and various information of weight factor and a command from the host computer. The parameter relating to the data transfer is written in a register group 8 and the kind of local operation and the weight factor are written to register groups 9,10 via a bus interface 1. When a transfer start instruction is received from the host compute, the picture processing DMA controller is operated, the acquisition of the right of use of the bus is confirmed and becomes a bus master. When the local operation processing is finished for execution to the given memory area, the bus slave configuration is attained.

Description

DETAILED DESCRIPTION OF THE INVENTION Technical Field The present invention relates to an image processing device that can perform local image calculations (also called neighborhood calculations or spatial filtering) at high speed.

<Prior art> In recent years, advances in LSI technology have made it possible to produce high-performance microprocessors and large-capacity memories in small sizes and at low cost, making it possible to construct high-performance computer systems at low cost. It's here. However, no matter how sophisticated a computer system is, its processing speed is a problem when it is applied to image processing. In other words, since image data is two-dimensional data, the amount of data is generally enormous (for example, if one pixel has 8-bit gradation and one screen has a configuration of 1024 x 1024 pixels, the amount will be 1 MB). Conventional sequential computer processing requires a large amount of processing time to process image data. In particular, when performing local image calculation, which is a basic image processing method, the processing time becomes extremely long because the image memory is referenced many times. Conventionally, as a countermeasure for this processing time, a high-speed bus dedicated to C1 image processing was used. In order to increase the speed of image processing, hardware dedicated to image processing was connected to this high-speed bus. In this case, compared to sequential processing by a computer, processing speeds that are usually two to four orders of magnitude faster are possible.However, dedicated image processing hardware configured in this way can only be applied to specific dedicated systems; It could not be used in general microcomputer systems.

On the other hand, conventionally, between input/output device←memory or memory→
DMA (
Direct Memory Access) controllers have been developed as peripheral LSIs for various microprocessors. These DMA controllers can be easily connected to the microprocessor's bus and can perform data transfers that are one to two orders of magnitude faster than normal program transfers.However, these DMA controllers are only intended for data transfer. Therefore, it was impossible to perform calculations on the transferred data. Also, of course,
It was completely impossible to perform local operations because it did not have line memory or a local parallel processing mechanism.

Purpose of the present invention The present invention eliminates the drawbacks of the prior art described above, improves the DMA controller so that it can be connected to a general-purpose computer bus, and can perform local image calculations that are extremely time-consuming in sequential processing by conventional computers. It is an object of the present invention to provide a novel image processing device that can perform high-speed processing.

<Embodiment> Hereinafter, one embodiment of the image processing apparatus according to the present invention will be described in detail using the drawings. FIG. 1 is a block diagram showing an embodiment of an image processing apparatus according to the present invention.

In FIG. 1, an image processing DMA, which is an image processing device,
7 controller bus interface 1 to bus B of the computer. This bus interface 1 satisfies the specifications of the computer bus B (therefore, this image processing DMA controller can be easily connected to computer systems that have the same bus specifications t), address bus buffer 12
, a data bus buffer 73, a control bus buffer 4, a control bus rosin 15, and the like. If only the bus interface 1 is replaced, the present invention can be applied to a computer system with a different bus specification. Address bus buffer 2 above. Data bus buffer 3 Oyohi control path buffer 4
Most of the devices are designed to allow bidirectional input/output and tristate output, and thus can function as both bus masks or bus slaves.

Usually, the image processing DMA controller is a bus slave, and receives various information and instructions from the host computer, such as parameters related to data transfer, types of local calculations, and load coefficients.

Note that the parameters related to the data transfer are written to the register group 8, and the type of local operation and the weighting coefficient are written to the register group 9 and the register group 10, respectively, via the bus interface 1.

The image processing DMA controller starts operating upon receiving a transfer start command from the host computer, and becomes the bus master after confirming that it has acquired the right to use the bus. When the local arithmetic processing specified in advance by the host computer has been executed on the given memory area, the image processing DMA controller issues an interrupt signal via bus interface 1 or sets an end flag. Becomes a bus slave again.

Now, in FIG. 1, a timing controller 6 provides timing for generating an address to an address generator 7, and performs timing control so as to synchronize the address generator 7 with the interface 1. Further, the address generator 7 generates 2 bits based on the contents of the register group 8.
Generate addresses for accessing memory sequentially through dimensional scanning. From the register group 8 to the address generator 7
The following parameters are given for two-dimensional scanning.

Now, as shown in Figure 2, on the screen with horizontal width
+The width in the horizontal direction is ΔX, and the width in the vertical direction is ΔY. Generally, when allocating image memory in the one-dimensional address space of a computer, the address of the pixel in the upper left corner of the entire screen is set as the minimum address, and the address is increased as the pixel moves horizontally one pixel like in rask scanning. Once one line has been scanned, addresses are assigned in the same manner starting from the leftmost pixel of the next line immediately below. Therefore,
In FIG. 2, the address of the i-th point P (i, j) in the horizontal direction and the j-th point in the vertical direction from Po is Po+j−x10i (0≦i≦ΔX.

0≦j≦ΔY).

Therefore, if the address generator 7 is equipped with a simple arithmetic function to perform the above operations, the information such as Po, An address for scanning an arbitrary rectangular area can be generated at high speed.

Next, the register group 9.10 in FIG. 1, the line memory 11,
Each component of the local parallel arithmetic unit 12 and shift register 13 will be explained. As mentioned above, register group 9
Information regarding the type of local operation (spatial product-sum operation, -order differential operation, Laplacian, etc.) is written into the register group 10, and the load coefficient for the local operation is written in advance from the host computer into the register group 10.Then, the local parallel operation unit 12 executes a predetermined local operation (spatial product-sum operation, -order differential operation, Laplacian, etc.) determined by the contents of the register group 9 on a group of data in the vicinity of the target pixel that is simultaneously output from the shift register 13. do.

FIG. 1 shows a case where the kernel size is (3×3), and the center thereof is the target pixel.

Due to the above kernel size configuration, the line memory 11 is 2
A line is required. Note that by making the length of the line memory 11 variable, local calculations can be performed in any rectangular area. In this example, Δ in FIG.
Match the line memory length to the length of X. Note that the line memory 11 can be easily realized by using a combination of a counter and a RAM, a shift register, or the like. Further, the arithmetic processing of the locally parallel arithmetic unit 12 can be realized relatively easily by performing pipeline processing.

FIG. 3 shows the configuration of the locally parallel arithmetic unit 12. In FIG. 3, a multiplier M multiplies data of each pixel outputted from the shift registers 13, . . . by a weighting coefficient corresponding to each pixel outputted from the register group 10. The multiplication result is sent to the adder ALU in a pipeline.
are added one after another, and the final result is a spatial product-sum operation with a kernel size of 3×3.

The spatial product-sum calculation result is transferred to a predetermined location in the image memory via the path interface 1.

The data transfer operations of the image processing DMA controller of this embodiment described above can be summarized as follows. That is, the image processing DMA controller uses the address generator 7 to specify an address in a raster scanning manner to a memory area for input images (rectangular area of the image memory) specified in advance by the host computer, and sequentially reads the memory contents. It is read and transferred to the line memory 11 in the DMA controller.

Then, the calculation results obtained by the local parallel calculation unit 12 in the DMA controller are sequentially written into the output image memory area designated in advance by the host computer. The operations of reading from the input image memory and writing to the output image memory are repeated alternately. For the two horizontal lines on the top and the two vertical lines on the left side, the image data of the 3x3 kernel size is not collected in the process in which the image processing DMA controller sequentially specifies addresses from Po. In this section, only reading of image data is executed.If the output data of the locally parallel arithmetic unit '12 is stored in a line memory other than that shown in FIG. It is possible to make them the same, that is, to rewrite a predetermined portion of the image memory.

Next, the processing speed of the entire system when using the above image processing DMA controller will be described.

As shown in FIG. 4, the above-mentioned image processing DMA controller
(memory) is used by connecting to the respective bus,
Data transfer is performed via this bus. Further, inside the image processing DMA controller, various calculations are performed at high speed by the dedicated hardware described above. Therefore, in FIG. 4, the data transfer and calculation speeds of the entire system when using the image processing DMA controller are mainly determined by the data transfer speed determined by the bus specifications or the access time of the memory used. . However, by providing the image processing DMA controller with a dedicated two-dimensional address generation function and arithmetic function as hardware, it becomes possible to speed up the processing by about one to two orders of magnitude compared to sequential processing by a conventional computer.

<Effects> According to the present invention described above, the conventional general computer
Transfer image data just by connecting to the path.

Image conversion, calculations between one image, etc. can be performed at very high speed.

[Brief explanation of drawings]

FIG. 1 is a block diagram of an embodiment of an image processing device according to the present invention, FIG. 2 is an explanatory diagram for explaining the address of a pixel in a rectangular area of memory, and FIG. 3 is a diagram of a locally parallel arithmetic unit. Internal circuit configuration diagram, FIG. 4 shows the overall system configuration diagram. In the figure, 1...Path interface, 2...Address bus buffer, 3...Data bus buffer, 4...
Control bus buffer 1, 5...Control bus
Hass Logic, 6...timing controller. 7... Address generator, 8... Register group, 9...
- Register group, 10... Register group, 11... Line memory. 12... Locally parallel arithmetic unit, 13... Shift register agent Patent attorney Aihiko Fukushi (and 2 others) Figure 2 Figure 4

Claims (1)

[Scope of Claims] 1. A processing device connected to a computer bus to which a central processing unit and a memory of a computer are respectively connected, an address for accessing the memory by two-dimensional scanning; address generating means for generating a signal;
bus signal generation means for generating computer bus signals necessary for data transfer; a plurality of line memories for storing image data accessed from the memory by the address generation means and the bus signal generation means; and the plurality of line memories. It is characterized by comprising a local arithmetic unit that simultaneously takes out a group of two-dimensional image data taken out by using the image data and performs local arithmetic operations thereon, and a transfer means that transfers the arithmetic results of the local arithmetic unit to an image memory. Image processing device.