JP2002278753A - Data processing system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To enhance efficiency of a data processing by enabling a data processing by a data processing system even during a data processing by a coprocessor and reducing the frequency of interruptions to a CPU in the data processing system having the CPU and the coprocessor. SOLUTION: Instructions to be processed by the coprocessor 21 are stored in an instruction register 22 capable of storing a plurality of instructions from the CPU 12, when an enable signal EN is supplied from the CPU 12 to the coprocessor 21, the instructions stored in the instruction register 22 are successively fetched, processed in the coprocessor 21 and access privileges to a RAM 14 are managed by a bus controller 21a.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an auxiliary co-processor (co-proc) which is combined with a CPU (Central Processing Unit) to reinforce its data processing and extend functions.
ESSOR).

[0002]

2. Description of the Related Art Conventionally, in order to reduce the processing load on a CPU in the compression processing of a digital audio apparatus, a specific processing mechanism, for example, a data processing with a large number of data digits, is provided with a dedicated processing mechanism. By causing the coprocessor to perform the specific processing, the load on the CPU is reduced and the processing time as a whole is reduced as compared with the case where the specific processing is performed by the CPU.

FIG. 4 shows a configuration of a conventional data processing system for performing coprocessor processing. FIG. 5 is a processing time chart of the data processing system, and FIG.
FIG. 2B shows the operation period (bus occupation period) of the CPU, and FIG. 2C shows the operation period (bus occupation period) of the coprocessor.

In FIG. 4, a CPU 42 for controlling the main control of the data processing system, a ROM 43 for storing program instructions, a RAM 44 used as a work storage area, and an input / output for exchanging data with other circuits. The circuit 45 and a coprocessor 46 having a specific processing mechanism are interconnected via a bus line 41.

[0005] The CPU 42 sequentially proceeds with necessary data processing according to the program instruction. If the program instruction is an instruction to be processed by the coprocessor 46, the CPU 42 causes the coprocessor 46 to process the instruction. To the coprocessor. In accordance with the instruction, the coprocessor 46 fetches necessary data from the RAM 44, performs a specified operation, and outputs the operation processing result to the RA.
The command is sent to M44 for storage, the processing of the command is terminated, and a termination signal is sent to the CPU 42 as an interrupt signal. In this manner, the coprocessor 46 besides the CPU 42
And by distributing the program instructions, the efficiency of the data processing system can be improved.

[0006]

SUMMARY OF THE INVENTION
The bus 41 is used for the processing of the coprocessor 46 while the processing of the instruction is being executed by the. For this reason, FIG.
As shown in the timing chart of FIG.
Cannot control the bus 41 or access the bus 41 during the period from when the instruction is transferred to the coprocessor 46 to when the interrupt (end signal) is returned. Only complete work can be performed, and substantially no other processing can be executed.

When receiving an interrupt (end signal) from the coprocessor 46, the CPU 42 uses an instruction cycle of several to several tens of clocks for interrupt processing. C
If the instruction frequency from the PU 42 to the coprocessor 46 is high and the processing execution time in the coprocessor 46 is short, the CP
The instruction cycle time used for the interrupt processing for U42 increases, and the efficiency of the data processing system decreases.

Accordingly, the present invention provides a data processing system having a CPU and a coprocessor, which enables other data processing in the data processing system even during data processing by the coprocessor, and reduces the number of interrupt processes to the CPU. It is an object of the present invention to provide a data processing system with significantly reduced data processing efficiency.

[0009]

According to a first aspect of the present invention, there is provided a data processing system, comprising: a CP for controlling a main control of the data processing system;
U1 and ROM 1 storing program instructions and the like
3 and a RAM 14 used as a work storage area, etc.
And an input / output circuit 15 for exchanging data with other circuits
And the CPU 12, the ROM 13, and the RAM 1
4. a coprocessor 21 having a bus 11 to which the input / output circuit 15 is coupled, a bus controller 21a coupled to at least a part of the RAM 14, and performing bus control including access to the coupled RAM 14; And an instruction register 22 (23) capable of storing the instruction of
Instructions to be processed by the coprocessor 21 from the CPU 12 are stored in the instruction register 22 (23), and an enable signal E from the CPU 12 is sent to the coprocessor 21.
When A is supplied, the instructions stored in the instruction register 22 (23) are sequentially fetched into the coprocessor 21 and processed, and the access right to the combined RAM is managed by the bus controller 21a. Features.

According to the data processing system of the first aspect, instructions to be processed by the coprocessor 21 are stored in the instruction register 22 (23) capable of storing a plurality of instructions from the CPU 12, and the enable signal EN is transmitted from the CPU 12 to the instruction register 22 (23). When supplied, the instructions stored in the instruction register 22 (23) are sequentially fetched and processed, so that the number of interrupt processes of the CPU 12 is significantly reduced.

In addition to the bus 11, the RAM 14 and the coprocessor 21 are directly connected by a coprocessor bus 25, and both the CPU 12 and the coprocessor 21 can be accessed by a bus controller 21a provided in the coprocessor 21. Since the access right to the RAM 14 is managed, the access to the RAM 14 is restricted only when the coprocessor 21 is accessing the RAM 14.
12 can execute necessary processing. Also, RA
M14 is divided into a plurality of areas, or a plurality of RAMs
, The restriction on access to the RAM can be reduced.

Thus, the CPU 12 and the coprocessor 2
1 improves the efficiency of data processing in the data processing system.

[0013]

DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of a data processing system according to the present invention will be described below with reference to the drawings.

FIG. 1 is a diagram showing a configuration of a data processing system according to a first embodiment of the present invention.
A CPU 12 that controls the main control of the data processing system;
A ROM 13 for storing program instructions and the like, a RAM 14 used as a work storage area and the like, and an input / output circuit 15 for exchanging data with other circuits are connected. The RAM 14 is divided into an area A and an area B. The area A is connected to the bus 11 and accessed by the CPU 12, while the area B is connected to the bus 11 and accessed by the CPU 12, and is also connected to the coprocessor bus 25 and accessed by the coprocessor 21. . Hereinafter, the areas A and B of the RAM 14 will be referred to as RA
M (A) 14a and RAM (B) 14b.

The coprocessor 21 has a dedicated processing mechanism for performing a specific processing that requires a large processing load when processed by the CPU 12, for example, processing a data having a large number of digits. The coprocessor 21 needs to obtain data from the RAM 14 or write the processing result to the RAM 14 when processing the allocated instruction.
AM14. In particular, in the present invention, the coprocessor 21 has a bus controller 21a that controls access to the RAM 14 (B) 14b.

The bus controller 21a includes a CPU
(B) that can be accessed by the CPU 12 and the coprocessor 21
14b is controlled, and normally operates based on the bus control of the CPU 12, and is configured to give priority to access to the coprocessor 21 when the coprocessor 21 is performing a processing operation. ing. This access priority processing is performed by the bus control signal BCTL supplied from the coprocessor 21 to the CPU 12.
And the coprocessor 21 stores the RAM 14 (B) 1
This occurs when accessing 4b. Further, the coprocessor 21 is configured so that its processing operation is permitted by an enable signal EN from the CPU 12.

The instruction register 22 has a plurality of n storage areas, and sequentially stores instructions to be processed by the coprocessor 21 supplied from the CPU 12 via the instruction bus 24. Each storage area of the instruction register 22 stores, for example, an instruction code register 22 indicating a type of operation.
a, a first source register 22b that represents a RAM address that is the original data of the operation, a second source register 22c that represents the RAM address that is the original data of the operation, and a write register 22 that represents the RAM address where the computed result is to be written.
d. The instructions stored in the instruction register 22 are taken out by the coprocessor 21 in the order in which they are stored. Then, when all the stored instructions have been processed, an interrupt signal indicating the end of the processing is supplied to the CPU 12.

This data processing system comprises a bus 11, C
A one-chip microcomputer 10 including a PU 12, a ROM 13, a RAM 14, and an input / output circuit 15, a coprocessor 21 having a bus controller 21a, and a new coprocessor 20 including an instruction register 22 capable of storing a plurality of instructions. , Can be configured. With such a system configuration, the data processing system of the present invention can be easily and simply configured.

Now, the control operation of the data processing apparatus according to the first embodiment of FIG. 1 will be described with reference to FIG. 2 showing a time chart thereof. 2A shows the system clock, FIG. 2B shows the operation period of the CPU 12, and FIG. 2C shows the operation period of the coprocessor 21,
FIG. 4D shows a period in which the CPU 12 can use the RAM (B).

When an instruction to be processed by the coprocessor 21 occurs while the CPU 12 is processing a series of program instructions, the instruction is supplied to the instruction register 22 in the order in which the instruction is generated, and the instruction from the address 1 of the instruction register 22 starts. The data is sequentially stored toward address n.

When an instruction is stored in the instruction register 22,
The CPU 12 supplies the enable signal EN to the coprocessor 21 (time t1 in FIG. 2). The enable signal EN is continuously supplied until the processing of the instruction by the coprocessor 21 ends. First, the coprocessor 21 fetches the instruction stored at the highest address of the instruction stored in the instruction register 22. According to the data in the source registers 22b and 22c, the original data of the operation is read from the specified address of the RAM (B) 14b. For example, assuming that reading from the RAM (B) 14b is performed during a period from time t2 to time t3, the bus controller 21a of the coprocessor 21
From the time t2 to t3
During this period, the CPU 12 is notified and the coprocessor 21 is connected to the RAM (B) 14b and acquires data at the specified address.

According to the instruction code indicating the type of operation, a predetermined operation is performed on the read source data, and the result of the operation is written to the address of the RAM (B) 14b specified by the write register 22d. . For example, the writing to the RAM (B) 14b is performed at time t4
From time t5 to the time t5, the control signal BCTL from the bus controller 21a
During the period from 4 to t5, the CPU 12 is notified, the coprocessor 21 is connected to the RAM (B) 14b, and the data of the operation result is written to the specified address.

As a result, the instruction stored at the address 1 of the instruction register 22 is processed, the processed instruction is erased, and the processing of the instruction stored at the next address 2 is similarly executed.

The processing in the coprocessor 21 is as follows.
Each instruction stored in the instruction register 22 is sequentially performed.

On the other hand, during this series of processing, the CPU 12
Are sequentially processing instructions other than the instruction instructed to the coprocessor 21 in parallel with the processing in the coprocessor 21.
In the processing of the instruction of the CPU 12, the bus 11 is not directly connected to the coprocessor 21.
3. There is no limitation on the use of the RAM (A) 14a and the input circuit 15, and they can be used freely as shown in FIG. However, only when the RAM (B) 14b is used, as shown in FIG. 2D, only the periods t2 to t3 and t4 to t5 used by the coprocessor 21 cannot be used. Since the bus control signal BCTL is supplied from the coprocessor 21 to the CPU 12, the situation can be determined by the CPU 12. Further, the CPU 12 has a RAM (B) 14b
In response, the original data of the operation used in the coprocessor 21 is written to the specified address, and the data of the operation result is read from the specified address where the result of the operation in the coprocessor 21 is written.

As described above, the processing in the coprocessor 21 is as follows.
The processing is performed in parallel with the processing in the CPU 12, and for each instruction stored in the instruction register 22, an instruction end signal is supplied to the CPU 12 as an interrupt signal at time tn when all the instructions have been executed. As a result, the enable signal EN is stopped, and a series of processing in the coprocessor 21 ends. Subsequently, when a new instruction is executed, a process using the same coprocessor 21 is performed.

In this embodiment, a plurality of instructions to be processed by the coprocessor 21 are stored in the instruction register 22 by the CPU 12.
Since the instructions stored in the instruction register 22 are sequentially fetched and processed in accordance with the enable signal EN supplied from the CPU 12, the number of interrupts to the CPU 12 is significantly reduced. Therefore, the usage efficiency as a data processing system is improved.

The RAM 14 has a plurality of areas (two in this example), a RAM (A) 14a and a RAM (B).
14b, and one RAM (A) 14a is connected to the bus 1
1 and accessed by the CPU 12. The other RAM (b) 14 b is connected to the bus 11 and to the coprocessor 21 via a coprocessor bus 25. The bus controller 21 a provided in the coprocessor 21 controls the CPU 12 and the coprocessor 21.
Manages the right of access to the RAM (B) 14b, which can be accessed by both. As a result, the coprocessor 21
Only when accessing AM (B) 14b, RAM
(B) Access to 14b is restricted, but basically the CPU 12 can execute necessary processing even while the coprocessor 21 is executing the processing. Further, instead of dividing the RAM 14 into a plurality of areas, a plurality of RAMs may be provided.

In the embodiment shown in FIG. 1, the time tn at which all the instructions stored in the instruction register 22 have been executed.
The end signal of the instruction is supplied to the CPU 12 as an interrupt signal. However, prior to the end signal of the instruction, the number of unprocessed instructions stored in the instruction register 22 decreases (for example, two). , An end notice signal is notified, and a new instruction is added to the register 22 and stored. The end notice signal and the end signal can be generated from the instruction register 22 or the coprocessor 21.

With this configuration, before all the instructions in the instruction register 22 are processed, the next instruction to be processed can be newly stored, so that the use of the coprocessor 21 occurs continuously. Coprocessor 21
Need not wait for the processing of the instruction, the use efficiency of the coprocessor 21 is further improved.

FIG. 3 is a diagram showing a configuration of a data processing system according to another embodiment of the present invention.

In FIG. 3, the instruction register 23 has a plurality of n storage areas, and sequentially stores instructions to be processed by the coprocessor 21 from the CPU 12. Each storage area of the instruction register 23 includes, for example, an instruction code register 23a indicating a type of operation, a first source register 23b indicating a RAM address serving as original data of the operation,
It comprises a second source register 23c representing a RAM address serving as original data of the computation, and a write register 23d representing a RAM address in which the computed result is written.

In the instruction register 23, unlike the instruction register 22 in FIG. 1, instructions input from the CPU 12 are sequentially accumulated from a higher address where no instruction is stored at that time, and the highest order (1 When the instruction at the address (address) is processed by the coprocessor, each instruction after the address 2 moves upward by one address.

When an instruction to be processed by the coprocessor 21 is generated, the CPU 12 sequentially stores the instruction in the instruction register 23, and supplies an enable signal EN to the coprocessor 21 while the instruction register 23 has an instruction to be processed.

The coprocessor 21 outputs an enable signal EN
While the is supplied, the processing of the instruction is executed. Instruction processing always takes out and processes the instruction stored in the address 1 of the instruction register. During that time, it is monitored whether or not the instruction is stored in the highest address of the instruction register 23 and the lowest address n. If it is detected that the instruction is not present in the first address, an empty (Empty) is detected. That is, the end signal is supplied to the CPU 12 as an interrupt signal. When it is detected that the instruction is stored at the address n, the full (Full) signal is used as an interrupt signal and the CP signal is output.
Supply to U12.

Other configurations of the CPU 12 and the coprocessor 21 are the same as those of the embodiment of FIG.
1, ROM 13, RAM 14, and input / output circuit 15
This is the same as the embodiment. The same applies to the case where the data processing system includes the one-chip microcomputer 10 and the new coprocessor 20.

Now, the control operation of the data processing apparatus according to the second embodiment of FIG. 3 will be described focusing on the instruction register 23 and its related points, which are structurally different from the first embodiment of FIG. It will be described as.

When an instruction to be processed by the coprocessor 21 occurs while the CPU 12 is processing a series of program instructions, the instruction is first stored in the address 1 of the instruction register 23, and the enable signal EN is transmitted to the coprocessor 2.
Feed to 1.

The coprocessor 21 outputs an enable signal EN
Starts when the instruction register 2 is supplied.
3, the instruction stored at the address 1 is fetched, and the instruction is processed. The processing method of this instruction is shown in FIG.
This is the same as described in the embodiment. When the one instruction is processed, the storage address of each instruction stored in the instruction register 23 at that time is advanced by one. Then, the instruction newly stored at the address 1 is read and processed by the coprocessor.

On the other hand, the CPU 12
During the processing of the instruction, the newly generated instruction is sequentially supplied to the instruction register 23 each time the instruction is generated, and the instruction is stored at the address next to the address where the instruction is already stored at that time.

Processing of the instruction in the coprocessor 21
Due to the balance with the supply of new instructions from the CPU 12, the number of instructions stored in the instruction register 23 becomes one.
It fluctuates between the address and the address n.

When the instruction is stored up to the address n of the instruction register 23, the instruction register 23 stores the instruction in its full storage capacity. The (Full) signal is supplied to the CPU 12 as an interrupt signal. CPU1
In step 2, in response to a full signal, the supply of a new instruction to the instruction register 23 is refrained, and the coprocessor 21 waits for the processing to proceed.

Conversely, if there is no instruction at address 1 of the instruction register 23, there is no instruction to be processed in the instruction register 23. This state is detected by the coprocessor 21 and an empty (Empty) signal is output. C as an interrupt signal
Supply to PU12. In the CPU 12, an empty (Empt
y) Upon receiving the signal, the enable signal EN to the coprocessor 21 is stopped, and the coprocessor 21 waits for an instruction to be processed.

As described above, in the second embodiment shown in FIG. 3, the instruction register 23 is stored in a first-in first-out type (FIFO type).
A newly generated instruction is input from the CPU 12 to the instruction register 23 even during the instruction processing by the coprocessor 21, and the instruction register 23 is used as a kind of instruction buffer. Thereby, the CP
The number of interrupts to U12 is reduced, and the waiting time for processing in the coprocessor 21 can be eliminated.

In the above-described embodiment, the data processing system of the present invention includes a one-chip microcomputer 10 including a CPU, a coprocessor 21, and an instruction register 22 (2
Although the configuration includes the new coprocessor 20 including 3), it is needless to say that the present invention is not limited to this system configuration, and any modifications are possible, and other system configurations can be adopted.

[0046]

According to the data processing system of the present invention,
A plurality of instructions to be processed by the coprocessor are stored in the instruction register from the CPU, and when an enable signal is supplied from the CPU, the instructions stored in the instruction register are sequentially fetched and processed. It can be significantly reduced.

In addition to the bus, the RAM and the coprocessor are directly connected to each other by a coprocessor bus, and the bus controller provided in the coprocessor grants an access right to the RAM that can be accessed by both the CPU and the coprocessor. Because of the management, access to the RAM is restricted only when the coprocessor is accessing the RAM. Basically, the CPU can execute necessary processing while the coprocessor is executing the processing. Further, by dividing the RAM 14 into a plurality of areas or providing a plurality of RAMs, it is possible to reduce restrictions on access to the RAMs.

Thus, the efficiency of data processing in a data processing system having a CPU and a coprocessor is improved.

[Brief description of the drawings]

FIG. 1 is a configuration diagram of a data processing system according to a first embodiment of the present invention.

FIG. 2 is a time chart of the data processing system according to the first embodiment.

FIG. 3 is a configuration diagram of a data processing system according to a second embodiment of the present invention.

FIG. 4 is a configuration diagram of a data processing system that performs a conventional coprocessor process.

FIG. 5 is a processing time chart of a conventional data processing system.

[Explanation of symbols]

 DESCRIPTION OF SYMBOLS 10 1 chip microcomputer 11 bus 12 CPU 13 ROM 14 RAM 15 input / output circuit 20 new coprocessor 21 coprocessor 21a bus controller 22 instruction register 23 instruction register 24 instruction bus 25 coprocessor bus

Claims (1)

[Claims] 1. A CP for controlling a main control of a data processing system.
U, a ROM storing program instructions and the like, a RAM used for a work storage area and the like, an input / output circuit for exchanging data with other circuits, the CPU, the ROM, the RAM, A bus to which the entry / output circuit is coupled; a coprocessor coupled to at least a part of the RAM for performing a bus control including access to the coupled RAM; and an instruction capable of storing a plurality of instructions. An instruction to be processed by the coprocessor from the CPU in the instruction register;
When an enable signal is supplied from U, the instructions stored in the instruction register are sequentially taken into the coprocessor and processed, and the bus controller manages the access right to the combined RAM. Data processing system.