GB2180118A - Image processing - Google Patents

Abstract

An image processing device for processing image data according to predetermined program comprises: an address generator (MAP) for simultaneously generating addresses corresponding to each of a central point and a plurality of individual neighbouring points of an image region; a buffer memory (CASHO-CASHn) for simultaneously receiving data on the points, and their corresponding addresses from the address generators; a central processor (CP) coupled to the address generator (MAP) and the buffer memory for comparing the neighbouring point data with the central point data; arithmetic and logic units (PU1-PUn) connected to the central processor (CP) for selectively modifying the data simultaneously for the individual points according to instructions from the central processor (CP); a data integration unit (DC) for receiving a plurality of simultaneous outputs from the arithmetic and logic units (PU1-PUn) and generating a single output based on instructions from the program; and a decision integrator (FC) for receiving a plurality of the single outputs from the data integrator and generating a coded multi-value based on instructions from the program. <IMAGE>

Description

SPECIFICATION Image processing This invention relates generally to digital image processing, and more pa rticularly to devices used for processing neighbouring parts of an imagewhich are subsequently referred to as neighbour images.

No memory IC yet has been proposed in the art which can read the neighbour images at the same time. Previouslythe method generally employed has been to store and read out data on picture elements sequentially in and from a single memory. To obtain data or neighbour images the sequential data is accumulated in a shift register, with various outputs so thatthe data from image neighbours may be obtained simultaneously.

This type of processing device using shift registers suffers from a number of difficulties. For example, the operation is fixed for one process. Therefore, it is difficu It to vary the operation for every part of an image, so that all the parts ofthe image may be processed uniformly. In addition, since the shift registers are fixed in length, it is difficult to change the configuration of the masked region. Thus, it is extremely difficu It to change the operation and the configuration of the masked region for successive picture elements based on the condition orconfiguration of a previous picture element.

Because the image data is inputted sequentially, the neighbour images to be processed cannot be shifted or accessed in random order. Also, in the case of a larger mask, it is often necessary to add hardware in orderto process the images properly.

According to the invention a neighbour image processing device comprises address generating means for simultaneously generating addresses cor- responding to each of a central point and a plurality of individual neighbour points of an image neighbourregion; buffermemorymeansforsimu- Itaneously receiving data on the points, and their corresponding addresses from said address generating means; central processor means coupled to said address generating means and said buffer memory means for comparing the neighbour point data with data on the central point of the neighbour region; arithmetic and logic means connected to said central processor means for selectively modifying the data simultaneouslyforthe individual points according to instructions from said central processor means; data integrating means for receiving a plurality of simultaneous outputs from said arithmetic and logic means and generating a single output based on instructions from the program; and decision integrating means for receiving a pluralityofthesingleout- puts from said data integration means and generating a coded multi-value based on instructions from the program.

An advantage ofthis invention is that it provides a neighbour image processing device in which the above-described difficulties accompanying a con ventional mask type processing device have been eliminated and a flexible processing operation can be carried out at high speed. It also allows random ac- cessto data on neighbour images for more efficient processing. It also increases the speed of neighbour image processing without significant added hardware.

Preferably the address generating means includes a first array of adders. It is also preferred that the data integrating means include a second array of adders.

The second array may be tree shaped.

It is preferred thatthe buffer means include a plurality of individual buffer memories, and the arithmetic and logic means include a plurality of corresponding individual arithmetic units, one arithmetic unit being connected to each of the buffer memories. Each buffer memory may comprise a high speed cache memory. In addition, each arithmetic unit may include a transistor-to-transistor logic circuit.

The central processor means may include an arithmetic and logic unit having a transistor-to-transistor circuit herein. Preferably, the device also includes memory means for storing the programs to be executed bythe processing device.

A particular example of device in accordance with this invention will now be described and contrasted with the prior art with reference to the accompanying drawings, in which: Figure 1 is a block diagram showing one example of a neighbour image processing device according to this invention; and, Figure 2 is a block diagram showing one typical example ofthe arrangement of a conventional neigh- bour image processing device.

Previously, a masktype processing device as shown in Figure 2 has been used for neighbour image processing. The conventional device has a plurality of series-connected shift registers each corresponding to one horizontal line, to which image data read out of the TV camera orthe image memory are applied.

The data is loaded in a read tap registerthrough the intermediate connected points of the shift register, and neighbour data read out in a parallel mode (Figure 2 showing the case of 3 x 3 neighbours) are applied to an arithmetic unit array orthe like. Thus, the operation is performed in the manner of a pipe line to obtain the outputs sequentially, or one by one.

The sequential outputs thus obtained are displayed astheyare, orwritten in the image memory so that they are processed later.

This invention will now be described with referpence to Figure 1.

In Figurei,anaddressarithmeticunitMAPoper- ates as follows: According to the data on the central points an image neighbour region and itsconfigur ationwhich is specified by a micro program memory MM forevery step of a program or specified by a register value stored in the address arithmetic unit MAP or a central processor CP, the address arithmetic unit MAP calculates the coordinates of a number of picture elements in the aimed region in a parallel mode, atthesametime.

In the embodiment, the address arithmetic unit MAP is an array of adders.

The buffer memories in a buffer memory section (CASHO through CASHn) are connected to the arithmetic units (CP1 through CPn) in an arithmetic unit section PU, thus forming independent buffer mem ories.

In otherwords,the buffer memories CASHO through CASHn are connected directly or closely to the center processor CP and the arithmetic units PU1 through PUn without using a bus.

These memories are high-speed cache memories, and are not memories which are coarsely connected thereto through a low-speed bus: that is, they are provided onlyforthe processor.

The addresses ofthe buffer memories CASHO through CASHn may be different from one another and are given independently and simultaneously in a parallel mode bythe address arithmetic unit MAP.

The arithmetic units PUl through PUn can read and write the image data of a number of points simultaneously in a parallel mode according to the addresses provided by the address arithmetic unit MAP.

Each ofthe arithmetic units PU1 through PUn obtains one arithmetic resultthrough arithmetic and logic operations on some ofthree inputs, and this can be accomplished by using, for instance, a TTL circuit.

The central processor CP performs a decision according to the picture element value read from the central coordinates of the neighbor region, and app lies itto the following arithmetic units PU 1 through PUn.

The central processor CP may be, for instance, an ALU (arithmetic and logic unt) utilizing TTL (transis tor4o-transistor logic) which provides one operation flag according to one input result.

It is not always necessary that the coordinates of the central point be exactly the central point in the aimed neighbor region. Since the coordinates ofthe central point are used as reference data forthe address arithmetic unit MAP to provide the addresses of the points in the aimed neighbor region, instead of the precise coordinates, the coordinates of a point inside the region or outside it may be em ployed.

Utilizing the result of decision bythe central pro cessorCP and the pictureelementvalues provided by the buffer memory section CASH, the arithmetic units PU1 through PUn carryoutthe logic and arith metic operations specified by the program simu itaneously in a parallel mode, and output the results ofthe operations at the same time.

A data integrating unit DC receives a plurality of results outputted bythe arithmetic units PU1 through PUn, and calculates a single result and out puts it. In the above-described embodiment, the data integrating unit DC may be an array of adders. Atree shaped adder, similar to the group of arithmetic units shown in Figure 2, may be used as the data integrat ing unit DC.

An integration deciding unit FC performs a logic operation by using a plurality of results outputted by the above-described data integrating unit DC, and outputs its state as a coded multi-value. The integration deciding unit FC may be made up of a pro grammabie logic array.

Aprogram sequencer PS determines the next micro-program step according to the decision code provided bythe integration deciding unit FC.

In the embodiment, a look-up table utilizing mem ories or the like is employed as the data integration deciding unit. Programs to be executed in the neighbor image processing device are stored in the program storing memory MM. The program output provided by the microprogram memory MM controls the central processor CP, the arithmetic unit section PU, the buffer memory section CASH, the data integrating circuit DC, and the data integration deciding unit FC.

One example ofthe operation ofthe neighbor image processing device thus organized will be described with reference to the removal of a small solitary point in a shaded image.

For illustration purposes, a 3 x 3 neighbor mask is considered for a point to be eliminated.

(1) If, with respect to the central point thereof, all the 8-neighbors have values higherthan a given threshold value, and the central point has a value lowerthan the threshold value, then the average of the values ofthe 8-neighbors is assignedtothecen- tral point.

(2) If all the 8-neighbors have values lowerthan the threshold value and the central point has a value higherthan the threshold value, then zero (0) is assigned to the central point.

(3) In the other cases where the values of the 8neighbors do not satisfy one of the above conditions, nothing is done. The result ofthe above-described operation is stored in the buffer memory CASHO.

The buffer memory has a source region, and a destination region.

The procedure is as described below: Step O The address arithemtic unit MAP, while producing the coordinates of all the picture elements in an aimed image region, provides, with each set of central coordinates, its neighbor coordinates.

Step 1 In response to access to one neighbor, it is determined whether or notthevalue inputted tothe central processor CP exceeesthethreshold value, and the result ofthis determination is applied to the central processor CP so as to be transmitted to the arith- metic unit section PU and the program sequencer PS. Atthe same time, the threshold value decisions are carried out in all the arithmetic units in the arithmetic unit section PU, and the results of these decisions are supplied to the deciding unit FC. According to these data, the program sequencer PS determines the next microprogram sequence Step2 According to the above-described conditions (1), (2) and (3), the average value calculated bythe data integrating unit DC through the arithmetic unitsec tion PU, the constant value "0(Zero)" provided by the data integrating unit DC, or the central point's value latched by the central processor CP is written into the corresponding destination address in the buffer memory CASHO.

Step 3 The above-described operations are carried outfor all of the picture elements, and the procedure is complete.

Now, the 3 x 3 mask process will be described.

Step O The initialization is carried out by reading thefollowing data out of the microprogram memory: (1) The weight of the mask is loaded in a register in each ofthe arithmetic units.

(2) Address generation control data are inputted to the address arithmetic unit.

(3) The deviation value from the central point's coordinate ofthe mask address produced bythe address arithmetic unit is loaded.

Step 1 All images to be processed are inputted to nine (9) buffers Othrough 8through the external input bus by by-passing the data integrating unit DC.

Step 2 The different addresses of an aimed point and its neighbors are simultaneously produced by the address arithmetic unit MAP, and the contents ofthe buffer memories are read out at the same time.

Step 3 The data thus read out are multiplied by thecorresponding mask's content, and the results are applied to the data integrating unit DC.

Step 4 The sum of these results is obtained by the data integrating unit, and written in the corresponding address in the buffer memory.

The above-described operations are repeatedly carried out for all the images.

The neighbor image processing device according to the invention is designed and operated as described above. In the conventional device described previously, different hardware is required for different processes. By contrast, in the device of the invention, high-speed processing may be performed with the same hardware. Furthermore, the device ofthe in vention has a variety of applications, and can accomplish the image processing with fewer steps than the conventional apparatus.

I. In each ofthe steps, the type of operation can be readily changed.

II. In each of the steps, the result of operation can be fed backorrecycled.

Ill. In each of the steps, the region to be processed can be changed or skipped randomly on command.

IV. In each of the steps, the outputted result of operation can be immediately accessed again.

V. Depending on the particular processing program writing method and the buffer memory method used, the processors can operate in a parallel mode, independently of one another.

In the device of the invention, the contents ofthe image data are stored in buffer memories closely coupled to the processors instead of the image memory body, and are then read out and operated at high speed by being addressed directly bythe address processor, so that the processing speed can be increased.

Claims (10)

1. A neighbor image processing device for processing image data according to a predetermined program comprising: address generating means for simultaneously generating addresses corresponding to each of a central point and a plurality of individual neighbor points of an image neighbor region; buffer memory means for simultaneously receiving data on the points, and theircorresponding addresses from said address generating means; central processor means coupled to said address generating means and said buffer memory means for comparing the neighbor point data with data on the central point ofthe neighbor region; arithmetic and logic means connected to said central processor means for selectively modifying the data simultaneouslyforthe individual points according to instructions from said central processor means;; data integration means for receiving a plurality of simultaneous outputs from said arithmetic and logic means and generating a single output based on in structionsfromthe program; and decision integrating means for receiving a plurality of the single outputs from said data integration means and generating a coded multi-value based on instructions from the program.

2. A device according to claim 1 ,wherein said address generating means includes a first array of adders.

3. A device according to claim 2, wherein said data integrating means includes a second array of adders.

4. A device according to claim 3, wherein said second array is tree shaped.

5. A device according to any of the preceding claims, wherein said buffer means includes a plurality of individual buffer memories, and said arithmetic and logic means includes a plurality of corresponding individual arithmetic units, one arithmetic unit being connected to each of said buffer memories.

6. A device according to claim 5, wherein each buffer memory comprises a high speed cache memory.

7. A device according to any of the preceding claims, wherein each arithmetic unit includes a transistor-to-transistor logic circuit.

8. A device according to any one of the preceding claims, wherein said central processor means includes an arithmetic and logic unit having a transistorto-transistor logic circuit therein.

9. A device according to any one of the preceding claims, further comprising memory means forstor- ing the program to be executed by the processing device.

10. Aneighbourimage processing devicesubstantially as described with reference to Figure 1 of the drawings.