JPS61284799A - Image data processor - Google Patents

Abstract

(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

DETAILED DESCRIPTION OF THE INVENTION [Industrial Application Field] The present invention relates to an image processing device, and particularly to a circuit that develops display data into a one-color code when writing and processing display data into a one-display memory.

[Prior Art] In recent years, image memories have tended to have larger capacities, and this has made it possible to display multiple colors. That is, a method (bitmap method) is adopted in which one display dot is associated with display data of a plurality of bits.

That is, when displaying a character on one screen, the display pattern of the character is first given as an rlJ or rOJ font pattern (that is, a binary font pattern). Then, it is necessary to develop each of the above "1" and "O" into a color code for the foreground color or a color code for the background color, and write the developed color code into the display memory.

FIG. 10 is a block diagram showing a conventional example of an image data distribution device.

The timing controller 20 controls the overall timing of the image data processing device.

The display controller 30 is the timing controller 20
Based on the timing given by.

Create a display signal to display a screen such as a CRT.

In other words, the display controller 30 transfers the display address corresponding to the display position t on the screen to the display memory address bus 51.
to access the display memory 4o. The memory timing at this time is also given from the timing controller 20.

Output data from the display memory 40 is sent to the parallel-to-serial conversion circuit 32 in the one-display controller 30 via the one-display memory data bus 53. Then, a display signal is created by predetermined processing in the 1-display controller 30.

On the other hand, the CPU 60 executes the image processing program from the 1-image processing program memory 61, prepares the address and data to be written into the display memory 40 based on the data from the input/output interface 70, and determines the timing of the 1-image memory access request. The information is transmitted to the controller 20. Here, the input/output interface 70 includes an R3232C, a modem interface, a disk interface, a mouse interface, and the like.

When the timing controller 20 receives an access request from the CPU 60, it enables the display memory address buffer 52 and the display memory data bus buffer 54 at a timing that does not conflict with the display access of the 1-display controller 30. In parallel with this,
Give execution permission to the CPU 60 by 4. In this way the CPU
60 can access the display memory 40 only at permitted timings.

The CPU 60 writes the image (display pattern) to the display memory 4o while repeating the above operations.

Here, consider a case where the pattern to be displayed once is character information.

FIG. 11 is an explanatory diagram of one-color code development, and shows an example of a character pattern to be converted into a one-color code, and an example of a color code obtained by developing a part of the character pattern.

The 0 display memory 40, in which a single character font is given as a binary value (1 or O data), corresponds to the character code.
Assume that the memory employs a bitmap method in which 4-bit information of, for example, 16 colors is held for each dot. Then, set the color code of the foreground color (displayed character color) to rloloJ
and set the color code of the background color (background color of displayed characters) to ro
Assume that "loo".

The CPU 60 checks the character font data one bit at a time, and as shown in FIG. The color codes are arranged and the arranged color codes are sent to the display memory 40 as write data.

Incidentally, unlike the bitmap method described above, most conventional character display methods use a character generator method. In the case of this character generator method, once the character code and attribute color hood are written to the display memory, the expansion from a single character code to a character font, and from that character font to a display color code, can be performed using existing hardware. Ru. Therefore, the expansion to color code in the character generator method is as follows.

Can be processed very quickly.

[Problems with the Prior Art] However, in the bitmap method, when the CPU develops color codes, there is a problem that it takes a very long time.

This means that the CPU 60 is originally a byte or 2 bytes (
While processing (words) can be executed very easily and quickly, expanding while checking each bit one by one, in other words, expanding one byte of data into a bit string according to a pattern and rearranging it. The process, although not impossible, takes a very long time.

Image display devices that can display bitmap-based graphics display text! Although it is clearly more sophisticated than Ji, it is very problematic that its display processing takes a long time.

[Object of the Invention] The present invention has been made by focusing on the above-mentioned problems of the prior art, and enables development of pattern data into a color code without bit handling by the CPU, and also enables development of the color code. It is an object of the present invention to provide an image data processing device that can shorten the time required for data processing.

[Summary of the Invention] In order to quickly develop a character font pattern into a foreground color code or a background color color code, the present invention maintains a foreground color code in a foreground color register and a background color code. The color code of the character font is held in the background color register, and the selector selectively outputs the foreground color code or the background color color code according to the pattern of the character font.

[Embodiments of the Invention] FIG. 1 is a block diagram showing an example of a circuit on which the present invention is based.

The main difference between this example and the conventional example shown in FIG. 10 is that a one-color code expansion circuit 1O is added.

In the above example, when it becomes necessary to develop a color code, the CPU 60a transmits the necessary information to the color code development circuit 1.
Set to 0. As a result, under the control of the timing controller 21, the color code expansion circuit 10 executes the color code expansion operation, and the obtained color code is stored in the display memory 4o. Therefore, as before, CP
The processing speed is faster than when U60 develops color codes.

It should be noted that the same parts as those used in the conventional example shown in FIG.

FIG. 2 is a detailed block diagram showing the color code expansion circuit used in the above example.

The foreground color register 11 is a register that holds the color code of the foreground color, and the background color register 12 is a register that holds the color code of the background color. The pattern shift register 13 is a register that holds pattern data to be developed into color codes and shifts the pattern data. The selector 14 selects and outputs the color code of the foreground color or the background color according to the contents of the upper bits of the shift register 13.

In addition, the write address counter 15 is connected to the display memory 40.
The length counter 16 is a register that holds a write address for a single color code, and the length counter 16 is a counter that holds information about the length of pattern data to be developed into one color code, and the length of one horizontal line on the screen.

Next, the operation of the above example will be explained.

First, the CPU 60a receives the color code of the foreground color and the color code of the background color to be developed.

Set the color code of the foreground color to the foreground color register 11, and steal the color code of the background color to the background color register 12.

Next, the above pattern data is transferred to the pattern shift register 1.
Set to 3. Furthermore, after calculating the address to be written into the display memory 40, the CPU 60a sets this address value in the write address counter 15. And the CPU 60a.

Obtain the pattern data for one horizontal line to be developed, and
Line length information is set in the length counter 16.

The initial values of the length counters 16 are set to all 1 (-1) by a reset signal.

While the length counter 16 is negative, no execution signal is given to the timing controller 21, so the color code expansion operation remains stopped.

Here, the case of color code development for the 8×8 dot pattern shown in the pattern of FIG. 11 will be described.

The CPU 60a selects 1 from the number of pattern data to be developed.
The value obtained by subtracting the number of dots (the value of the number of dots minus 1) is set in the length counter 16. In the case shown in FIG. 11, there are eight dots in the horizontal direction, so the length counter 16 is set to "7". after that.

An execution signal is given to the timing controller 21,
The operation begins.

After that, the timing controller 21 controls the display memory 4
An enable signal is sent at the timing when 0 can be accessed. As a result, write address counter 1
The value of 5 is output to the display memory address bus 51.

In parallel with this, the value of the foreground color register 11 or the background color register 12 is selected by the selector 14 according to the value of the upper bit of the pattern shift register 13.

That is, in the above example, if the upper bit of the shift register 13 is "1", the foreground color corresponds, and at this time, the color code rlO10J of the background color held in the foreground color register 12 is set to the selector. It is output from 14. Further, if the upper bit of the shift register 13 is "0", it is assumed that the background color corresponds, and at this time, the color code ro100 of the background color held in the background color register 13
” is output from the selector 14.

The data of each color code selected as described above is output to the display memory data bus 53. Then, the timing controller 21 supplies a timing pulse to the display memory 40, and the selected data is written into the display memory 40.

After this, the timing controller 21 outputs a count pulse, counts the write address counter 15, decrements the length counter 16, and shifts the pattern shift register 13 to the left.

The above operation is repeatedly executed for each bit of data held in the pattern shift register 13, and when the value of the length counter 16 becomes "-1", the length counter 16 is
The execution signal will no longer be output. As a result, the color code development operation described above is stopped.

The CPU 60a recognizes that the execution of the color code expansion operation has been stopped by reading the value of the length counter 16 or by noticing an interrupt signal generated by the execution signal. As a result, the pattern data to be developed next, the address to be written into the display memory 40, and the length data of a horizontal line on the screen to be converted into a color code can be determined.
Set to each counter etc. Then, data for one column is written in one display memory 40 based on the above data, and these operations are repeated for the necessary columns to complete writing for one character.

In the above description, the case where the value of the write address counter 15 and the memory address of one dot in the display memory 40 correspond one to one has been described. By the way, there are cases where information on multiple dots is held at one address in the display memory 40, and in this case as well,
The present invention can be applied. However, in this case,
It is necessary to add a predetermined function to the timing controller 21. However, since this is not directly related to the present invention, its explanation will be omitted.

FIG. 3 is a block diagram showing nm of the timing controller 21. As shown in FIG.

FIG. 4 shows the operation of the timing controller 21.
It is a timing diagram showing □.

The memory cycle of display memory 40 is divided into two time slots (display time slot and CPU time slot).

In the display time slot, a display address is always supplied from the display address circuit 31 or the parallel-serial conversion circuit 32, and display data is read out at the start of a memory cycle.

The load pulse signal is loaded into the shift register 32 in the display controller 30.

On the other hand, in the CPU time slot, the CPU 60a
When a CPU request signal and a CPU write signal are accepted, it becomes active.

Since the CPU clock and the timing controller (Q clock) usually have an independent oscillator, the CPU request signal is generated asynchronously from the perspective of the timing controller 21.

The timing controller 21 synchronizes the CPU request signal and performs a wait, and for this wait, returns a wait signal to cause the execution of the CPU 60a to wait until the CPU request is received.

When a CPU request is received, read or write is executed in the memory cycle of that CPU time slot, depending on the value of the CPU write signal. During this memory cycle.

Since the buffer enable signal is turned on, the address from the CPU is supplied.

When the CPU write signal is "0", read data from the memory is transmitted to the data bus of the CPU 60a.

On the other hand, when the CPU write signal is "1", the path direction signal becomes rlJ, so data is supplied from the data bus of the CPU 60a. Furthermore, a memory write signal is transmitted to the display memory 40, and writing is executed.

The execution signal from the color code development circuit IO is sent to the CPU 60a.
are processed by the timing controller 21 in exactly the same way as the CPU request signal and CPU write signal from. However, the 2-way signal and the buffer enable signal are prohibited because the request source is not the CPU 60a. Instead, a count pulse signal is returned to the color code expansion circuit 10 at the timing of the memory write signal, and an enable signal is returned to the color code development circuit 10 at the timing of the buffer enable signal.

The write address and color code data are output to the respective buses according to the enable signal. At the same time, writing is executed by the memory wait signal, and at the same time as the writing is completed, the contents of each register and each counter are updated by the count pulse signal.

When the length counter is set to a positive value, the execution signal is
1'', the foreground color and background color corresponding to the dot pattern are started to be written into the display memory 4o as color code data. With each write, the length counter counts down and eventually reaches rOJ.

When the length counter is rOJ, it is 1, and since the execution signal is still being output, another write is executed. As a result, the length counter becomes -1 (FF), and the execution signal becomes "0".
” and execution stops. As a result, the number of executions is one more than the value set in the length counter 16. This execution is all executed based on the timing of the timing generation circuit TG, so there is no need for waiting.
Furthermore, since all adjacent CPU time slots are effectively executed, processing is completed very quickly.

In the embodiment of the timing controller described above, the CPU request signal and the execution signal are made equal (ORI
, etc.), the display memory 40 cannot be accessed until one color code development is completed.

If a timing controller is used that controls the CPU request signal and the execution signal based on priority, it is possible to easily access the CPU 7 even during the execution of one-color code development.

t55 is a block diagram showing another example of the circuit which is the premise of the present invention, and FIG. 6 is a diagram showing details of the color code expansion circuit shown in FIG. 5.

In this example, the write address counter 15 and length counter 16 are omitted from the embodiment shown in FIG. In this case, the functions of the ii-included address counter 15 and the length counter 16 are performed by the CPU 60a.

In other words, continuous automatic execution in one-color code development is CP
The color code expansion circuit 10a, which is executed by U60a and excludes the counters 15 and 16, executes only simple color code expansion. If you do this, the CPU 60a
Although the role of
This will be an improvement over the past.

FIG. 7 is a block diagram showing another example of the present invention.

In the example shown in FIG. 7, in the color code expansion circuit 10 shown in FIG. 2, instead of the pattern shift register 13,
Pattern data register 13a and data selector 13b
It has been established that

The pattern data register 13a holds pattern data to be developed into one color code, and the data selector 13b sequentially selects pattern data from the pattern data register 13a. Furthermore, the food selector 14a is a selector that selects a foreground color code or a background color code according to the appearance of the data selector 13b.

The operation of the color code expansion circuit 10b shown in FIG.
It is basically the same as the color code expansion circuit 10 shown in the figure. The difference is that the pattern data register 13a is
The data selector 13b receives and holds pattern data from the PU 60a, outputs one bit at a time from the L bit of the pattern data, and based on this output bit,
This is the point where the foreground color or the background jλ color is selected by the code selector 14a. Note that since the data selector 13b outputs one bit from the pattern data in response to the output signal of the length counter 16, conversion to a color code can be started even from the midpoint of the pattern data register 13a.

FIG. 8 is a block diagram showing a modification of the example shown in FIG. 7.

The example shown in FIG. 8 is obtained by omitting the write address counter 15 and length counter 16 from the example shown in FIG. 7, and adding a bit position counter 17. In this case, the functions of the write address counter 15 and length counter 16 are performed by the CPU 60a.

In other words, continuous automatic execution in one-color code development is CP
The color code expansion 11111 circuit 10c executed by U60a and excluding the counters 15 and 16 executes only simple color code expansion. If you do this, CP
Although the role of U60a will increase slightly, the performance of the system as a whole will be improved compared to before.

FIG. 9 is a block diagram showing an embodiment of the present invention.

In this embodiment, a character font ROM or the like is provided in place of the pattern data register 13a of the example shown in FIG. 7, and color codes are developed for character codes.

The character font ROM 80 stores character font patterns, and the character code register 81 is a register that holds character codes to be read. Further, the Y register 82 is a register that holds the vertical position of a font pattern for one character in the character font ROM 80, and is a register for setting a reading start point in the vertical direction (Y direction).

The X counter 83 is in the horizontal direction (
It counts the position in the lateral direction (X direction).
This is a register that sets the expansion start point for the direction (direction).

The data selector 14a is a character font ROM8.
Character font patterns output from 0 are sequentially selected.

Next, the operation of the above embodiment will be explained.

The character code to be converted into a one-color code is sent from the CPU 60a to the character code register 81. Based on this code, the upper bit of the ROM address is specified, the value specifying the upper and lower positions within the character font pattern is set from the CPU 80a to the Y register 82, and the starting position in the horizontal direction (X direction) is determined by the X counter. It is set to 83. Also, bit 2 of the X counter 83
The following values are used as select signals for the data selector 13b, and the values of the Y register 82 and the values of bits 3 and above are used as the lower bits of the 7 address of the ROM 80 (character 7 on).

Every time the X counter 83 counts up (or counts down) by one, one bit from the outputs of the data selector 13b is sent to the code selector 14a as a select signal, and in response to this select signal, the code selector 14a outputs a foreground color code or a background color code.

When the development of one horizontal row of character font patterns from the character font ROM 80 is completed, the CPU 60a
adds or decrements the value in the Y register 82 by one, and
The value of the counter 83 is set again and the same operation as above is performed to perform conversion into a color code.

Also in the embodiment shown in FIG. 9, the write address counter 15 and length counter 16 may be omitted.

Note that the above cPU60a is not a general-purpose CPU.
It may be a video processing CPU dedicated to display processing, and the font size of the character font ROM 80 can be set to any vertical and horizontal sizes, and the length of the character code register 81 can also be determined arbitrarily. Therefore, the above character font is an alphabet font.

For example, in the embodiment of FIG. 9, instead of the character font ROM 80, the kanji font ROM 80 may be a kanji 7 ont or a font for a special code.
You may also use

[9. Effect of Brightness] According to the present invention, there is an effect that the development operation from a character font pattern to a color code is quickly performed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an example on which the present invention is based. FIG. 2 is a block diagram showing a color code expansion circuit used in the above example. FIG. 3 is a circuit diagram showing the timing controller in the above example. FIG. 4 is a timing diagram showing the operation of the timing cotrote shown in FIG. 3. FIG. 5 is a block diagram showing another example on which the present invention is based. FIG. 6 is a block diagram showing the color code expansion circuit in the example shown in FIG. FIG. 7 is a block diagram of a color code expansion circuit showing another example which is a premise of the present invention. FIG. 8 is a block diagram showing a modification of the example shown in FIG. 7. FIG. 9 is a block diagram showing an embodiment of the present invention. FIG. 10 is a block diagram showing a conventional example of a single image data processing device. FIG. 11 is an explanatory diagram of one-color code development. 10, lOa, 10b, 10e, 10d---color code expansion circuit. it...Foreground color register. 12...Background color register, 13b...Data selector. 14...Selector. 14a...Code selector, 15...Write address counter. 16... Length counter, 21d... Timing controller. 30...Display controller, 60&...CPU, 80...Character font ROM. 82...Y register. 83...X counter. Patent applicant: ASCII Co., Ltd., -1 Arata Yokubo -1 Self ・＼. ＼−□ Fig. 3 Mu−−+ −＋＋＋＋＋＋＋＋＋＋ ＋＋−j 4th
Figure 6

Claims (4)

[Claims] (1) A foreground color register that holds the color code of the foreground color; a background color register that holds the color code of the background color; a character code register that holds the character code; a character font ROM for storing; a Y register for holding Y-direction position data of a font pattern in the character font ROM; an X counter for counting X-direction position data of a font pattern in the character font ROM; a data selector that sequentially selects the character font patterns output from the ROM; and a code selector that selects the foreground color code or the background color code in accordance with the output of the data selector. An image data processing device characterized by: (2) A foreground color register that holds the color code of the foreground color; a background color register that holds the color code of the background color; a character code register that holds the character font pattern; a character font ROM that stores a character font; a Y register that holds position data of a font pattern in the Y direction in the character font ROM; an X counter that counts position data of a font pattern in the X direction in the character font ROM; a data selector that sequentially selects the character font patterns output from the character font ROM; a code selector that selects the foreground color code or the background color color code in accordance with the output of the data selector; An image data processing device comprising: a write address counter that holds a write address to a display memory; and a length counter that holds length information of one line of the font pattern on the screen. (3) In claim 2, the timing for generating the write timing to the display memory, the count timing of the write address counter, the select timing of the data selector, and the count timing of the length counter An image data processing device comprising a controller. (4) The image data processing device according to claim 1, wherein the character font is a Kanji font pattern.