JP2538388B2 - Pattern conversion device - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to a pattern conversion apparatus for extracting n pieces of m-bit row data from a matrix-constituting bit pattern to form n-bit column data.

[Prior Art] Devices such as computers and word processors are becoming more and more sophisticated in recent years, and accordingly, there is a demand for speeding up of these devices as a whole system including peripheral devices.

From this, the CPU that is the core of the arithmetic processing of the above equipment
It is important to build a system (hardware, software) that operates efficiently, and that is functional and capable of rapid processing.

By the way, for example, a dot pattern read from an image scanner or a dot pattern in which characters or the like are represented by matrix dots is generally stored in a memory as a bit pattern without being coded by associating dots with bits.

FIG. 6 illustrates the concept of a matrix-constituting bit pattern stored in such a memory.

In the figure, the bit pattern 10 is M bits in the row direction,
It is composed of an N-bit matrix in the column direction, and each row has m units corresponding to the memory storage unit, as will be described later.
It is divided in bit units. The bit pattern 10 shown in FIG. 6 is divided into 8-bit unit row data, and five unit row data are arranged in each row in the row direction.

To store this bit pattern 10 in memory,
Generally, the unit row data is first fetched sequentially from the top row in the row direction, all the unit row data is fetched from the top row, and then the rank unit row data is fetched in the same way from the next row. By being repeated until
All element data of bit pattern 10 is stored in memory. As a specific example, the unit row data D0 in FIG. 6 is stored at address 0 of the memory, the unit row data D1 is at address 1, and the unit row data D4 and D5 are at addresses, respectively.
Stored in 4,5.

When the bit pattern 10 stored in the memory is output to a display device such as a display, it is sent to the display device for each unit line data stored in each address in the same manner as in the above process, and from the address 0, for example. Bit patterns are sequentially taken out and displayed on the display.

However, when this bit pattern is sent to, for example, a printer that requires a plurality of bits in the column direction of the bit pattern 10 at the same time, since the data read from the memory is in the row direction, the conversion processing from the row to the column is performed. is necessary.

FIG. 7 shows the concept of conventional pattern conversion, and the conversion will be specifically described with reference to FIGS. 7 and 6 (see, for example, Japanese Patent Publication No. 61-32990).

In FIG. 7, reference numerals 12 and 14 are shift registers provided inside the CPU, the shift register 12 is for left shift, and the shift register 14 is for right shift.

A case where n-bit unit column data x indicated by hatching in FIG. 7 is taken out using these shift registers will be described.

First, the unit row data D0 is fetched from the memory and stored in the shift register 12. And the shift register 12
Shift left once, and the 1-bit data shown in Fig. 7
Xi is fetched and then the data Xi is stored in the leftmost bit position of the register 14 by one right shift of the register 14. Next, the unit line data from memory is
D5 is sent to the register 12, and the left bit of the register 12 and the right shift of the register 14 store the first bit of the unit row data D5 in the register 14. Then, such a process is sequentially repeated, and finally the unit column data D35 is stored in the register 1
2 to this register 12 left shift and register 14
By right shifting, the unit column data X of n bits is formed inside the register 14.

Therefore, when the unit column data is extracted from the n unit row data that are continuous in the column direction, the number of left shifts of the register 12 is determined according to the position where the unit column data is extracted.

As described above, in this conventional pattern conversion example, the bit pattern data is converted from the row direction to the column direction by the read operation for each unit row data, the left shift operation of the register 12, and the right shift operation of the register 14. Is being done.

[Problems to be Solved by the Invention] However, in the conventional pattern conversion described above,
Since n unit row data is written from the memory to the register inside the CPU, and more shift operations are required,
The load on the CPU is heavy, which makes it difficult to perform row-to-column conversion at high speed.

Further, such an increase in the load on the CPU lowers the processing speed of the entire system, and there is a problem that the conversion operation cannot follow when the dot pattern data is sent to the high speed printer. .

The present invention has been made in view of the above-described conventional problems, and an object thereof is to provide a pattern conversion device capable of reducing the load on the CPU and performing rapid pattern conversion.

[Means for Solving the Problems] In order to achieve the above object, a pattern conversion device according to the present invention stores a matrix configuration bit pattern for each m-bit unit row data and reads it for each unit row data. Which is one of the m-bit unit row data, and the pattern memory, a reading unit that performs n times of reading on the pattern memory, and sequentially reads n unit row data that are continuous in the column direction of the bit pattern. A bit position specifying circuit for specifying one bit position and n unit row data read from the pattern memory are sequentially input, and only bit data at the bit position specified by the bit position specifying circuit is selected. Shifter for generating a shift pulse every time data is read from the pattern memory A generator,
And a shift register that takes in bit data sequentially output from the data selector according to the shift pulse and forms n-bit unit column data.

[Operation] According to the above configuration, n unit row data are read from the memory in response to the reading by the reading unit n times.
Then, each read unit row data enters the data selector, and here, only the bit data at the bit position where the column conversion is performed is selected and reaches the shift register.

The shift pulse generator generates a shift pulse every n times of reading, and sequentially stores the bit data from the data selector in the shift register. As a result, n-bit unit column data is formed.

[Embodiment] A preferred embodiment of the present invention will be described below with reference to the drawings.

FIG. 1 shows the overall configuration of the pattern conversion device according to the present invention.

In the figure, 20 is a CPU that controls the entire apparatus, and an address bus 2 that sends out an address is sent to this CPU 20.
2, and a data bus 24 for inputting / outputting data is connected. The address bus 22 is provided with a latch circuit 26 for latching the address signal output from the CPU 20.

The CP via the address bus 22 and the data bus 24
The memory 28 connected to U20 has the bit pattern 1 described above.
It stores 0, and in the present embodiment, one that is read and written in 8-bit units is used. Of course, for example, 16
It may be read and written in bit units.

Control unit 30 that receives status signals from CPU 20
Is a memory 28 or I / O described later based on the status signal.
And the state of the address bus 22 via the latch circuit 26. Here, a memory write signal (MWR) and a memory read signal (MRD) are sent to the memory 28, and an I / O write signal (IOW) and an I / O read signal (IOR) are sent to the I / O. Has been done. Further, the ALE signal for controlling the latch operation is sent to the latch circuit 26.

The decoders 32 and 34 receive an address from the CPU 20 and send a chip select signal (CS) to the device designated by the address.

 The operation of each configuration up to this point will be outlined.

When reading the memory 28, first, the CPU 20
An address signal indicating the address to be read in is output. This address signal is latched by the latch circuit 26 and reaches the memory 28. On the other hand, the control unit 30 receiving the read command from the CPU 20 sends an MRD signal to the memory 28. With this MRD signal, the data stored in the address specified by the address signal is sent from the memory 28 to the data bus 24.

Next, the characteristic configuration of this pattern conversion device will be described below.

In the figure, a bit position specifying circuit 36 stores the bit position of the bit data extracted from the unit row data, and further supplies a bit position specifying signal indicating the bit position to a data selector circuit 38 described later. That is, when extracting the unit column data X in the hatched portion in FIG. 6 from the bit pattern 10 shown in FIG. 6, the leading bit position of the unit row data, that is, 0 is designated. The specified bit position is set to CPU2 before the unit line data is output from the memory 28.
Written by 0.

The data selector circuit 38 selects and outputs only the bit data at the bit position designated by the bit position designation circuit 36 from the unit row data.

The bit data output from the data selector circuit 38 is sequentially fetched by the bit alignment circuit 40. Then, by taking n bit data into the bit alignment circuit 40, n-bit unit column data (hatched portion X in FIG. 6) is formed.

 Each of the above circuits will be described in more detail with reference to FIG.

In the figure, the bit position specifying circuit 36 is composed of a bit position specifying register 44 and an OR gate for giving a write command to the bit position specifying register 44. here,
The bit position specification register 44 is connected to the CP via the data bus 24.
The bit position information sent from U is stored and output to the data selector circuit 38. The storage operation is controlled by the IOW signal from the control unit 30 and the CS2 signal from the decoder 34, and the storage is performed before the n-time read command output from the CPU for pattern conversion. . That is, the bit extraction position is designated for the n unit row data shown in FIG. In this embodiment, three signal lines are connected to the bit position designation register 44 from the data bus 24,
Eight bit positions can be specified.

The data selector circuit 38 is composed of a data selector 39, and is a coded signal from the bit position specification register 44.
Receiving R0 to R2, the bit of the unit row data fetched from the data bus 24 is selected. In this embodiment,
Eight signal lines from the data bus 24 to D0 to D7 are connected to the data selector circuit 38, and it is possible to receive 8-bit data. Then, the bit data selected by the data selector 38 is sent from the terminal Y to the next bit alignment circuit 40.

The bit alignment circuit 40 includes a shift register 50 that receives the bit data, a buffer 52 connected between the shift register 50 and the data bus, and an OR gate 54 that gives a read command to the buffer 52. There is. Then, the SFT pulse for performing the shift operation is supplied to the shift register 50 from the shift signal generator 42 described later.

Therefore, the bit data from the data selector circuit 38 is sequentially taken into the shift register 50 every time the SFT pulse is supplied, and 8-bit unit column data is formed in the shift register 50 by the eight SFT pulses.

Here, the OR gate 54 is supplied with the IOR signal from the control unit 30 and the CS2 signal from the decoder 34, and the CPU 20
The unit column data is sent from the shift register 50 to the data bus 24 via the buffer 52 in response to the command. The number of bits of the shift register corresponds to the number of bits of the unit column data to be extracted. For example, in the case of extracting the 8-bit unit column data, the shift register
The number of bits of 50 is changed to 8 bits, and the memory 28 to 8
It suffices to read out individual unit line data.

Next, referring to FIGS. 3 and 4, the shift register 50 will be described.
The shift pulse generator 42 that supplies the shift pulse SFT to will be described.

In FIG. 3A, the shift pulse generator 42 comprises a status judgment circuit 56, a latch circuit 58 and an OR gate 60. The status determination circuit 56 is supplied with the STATUS signal output from the CPU 20, and this signal is used for the memory 28.
To read to.

And if an example of the status judgment circuit 56 is shown,
It is possible to use the circuit shown in FIG. Here, the STATUS signal is composed of four signal lines, and the status of the memory data read can be determined based on these four signal lines. Here, when reading memory data, COD is 0, MIO is 1, S1 is 0, and S0 is 1.

The operation of the shift pulse generator 42 will be described with reference to FIG.

In the figure, CLK is the clock of the CPU 20. When the status determination circuit 56 determines that the memory data is read, the signal 100 changes from HI to LO. And the control unit 3
When the ALE signal from 0 becomes Hi, the latch circuit 58 sends a signal 100.
Are latched and output as signal 102. That is, this signal 102 indicates whether or not it is the status of the data read of the memory. In other words, this signal 102 is
When is LO, shift pulse generation is allowed. Here, the shift pulse is output in synchronization with the MRD signal by the action of the OR gate 60. And this shift pulse
The shift operation of the shift register 50 is performed at the rising edge of SFT, and the bit data output from the data selector circuit 38 is sequentially captured in the shift register 50.

Therefore, the occurrence of the shift pulse SFT is signaled on the assumption that the status of the memory data read is judged.
It is understood that the output is synchronized with MRD. Note that when reading the instruction code from the program memory, the signal 100 does not become Lo because COD becomes "1".

Next, the conversion operation of the pattern conversion device will be described with reference to FIG. 5 and with reference to FIG.

First, in step 201, the bit position designation circuit 36 is sent from the CPU 20.
A bit extraction position for pattern conversion is designated. Then, the bit position designating circuit 36 stores the designated bit position and outputs the information representing the designated bit position to the data selector circuit 38.

In step 202, interruption to the CPU 20 is prohibited, and in the following step 203, the address of the unit row data fetched from the memory 28 is calculated. For example, when the unit row data D0 shown in FIG. 6 is taken out, the address 0 is calculated first.

In step 204, a memory read command is output from the CPU 20 to the control unit 30 once. And the control unit
30 sends an MRD signal to the memory 28 based on the command, whereby the unit row data D0 is sent from the memory 28 to the data selector circuit 38 via the data bus 24. As described above, since the data selector circuit 38 selects the bit data at the bit position designated by the bit position designation circuit 36, the designated bit data reaches the shift register 50. In this case, the drive shift pulse of the shift register 50 is generated based on the read command and the MRD signal as shown in FIGS.
When the signal is generated, the shift register 50 automatically operates to take in bit data.

Then, steps 203 and 204 are repeated eight times to form 8-bit unit column data in the shift register, and the process proceeds from step 204 to step 205. Here, in step 203, the address is sequentially incremented by 5 so that the data in the same column is read.

In step 206, unit column data is read from the shift register 50 via the buffer 52. In addition, the read data can be used for other I / O via CPU20 or directly.
Sent to the device. Then, in step 207, the CPU interrupt is permitted, and in step 206, the processing from step 201 is restarted. That is, the CPU is prevented from being interrupted during the formation of one unit column data.

Therefore, as will be understood from the above, the shift register 50 automatically performs the shift operation based on the reading of the CPU 20, so that it is not necessary for the CPU to directly give the shift signal to the shift register 50. The load on the CPU 20 is significantly reduced. In addition, shift pulse generation
Since it is performed based on the data read from the memory of the CPU 20, for example, in the case of I / O read or instruction code read, the shift pulse is not generated, and the shift pulse can be generated accurately. .

[Effects of the Invention] As described above, according to the pattern conversion device of the present invention, since unit column data can be formed without requiring a complicated shift operation as in the conventional art, rapid pattern conversion can be performed. It is possible to do.

BRIEF DESCRIPTION OF THE DRAWINGS FIG. 1 is a block diagram showing an overall configuration of a pattern conversion device according to the present invention, FIG. 2 is a block diagram showing a partial configuration of FIG. 1, and FIG. 3 is a shift pulse generator. 4 is a timing chart showing the timing of each signal of the shift pulse generator, FIG. 5 is a flow chart of pattern conversion, FIG. 6 is a conceptual diagram showing a bit pattern, and FIG. 7 is a conventional pattern. It is a conceptual diagram which shows the method of conversion. 20 …… CPU 28 …… Memory 30 …… Control unit 36 …… Bit position designation circuit 38 …… Data selector circuit 40 …… Bit alignment circuit 42 …… Shift signal generator 50 …… Shift register

Claims (1)

(57) [Claims] 1. A pattern memory which stores a matrix-constituting bit pattern for each m-bit unit row data and is read out for each unit row data, and n times of reading to the pattern memory,
A reading unit that sequentially reads n unit row data that are continuous in the column direction of the bit pattern, a bit position specifying circuit that specifies any one bit position in the m-bit unit row data, and the pattern memory. A data selector that sequentially inputs the n number of unit row data to be read and selects only bit data at the bit position designated by the bit position designation circuit, and generates a shift pulse each time data is read from the pattern memory And a shift register that takes in bit data sequentially output from the data selector according to the shift pulse and forms n-bit unit column data.