JPH0236991B2 - - Google Patents

Description

[Detailed Description of the Invention] [Industrial Application Field] The present invention relates to an image data processing device, and in particular,
The present invention relates to a circuit that develops display data into color codes when writing display data to a display memory.

[Prior Art] In recent years, image memories have tended to have larger capacities, and this has made it possible to display multiple colors. That is, a method (bitmap method) is adopted in which color information display data of a plurality of bits are associated with each display dot.

That is, when displaying a character on the screen, the display pattern of the character is first given as a font pattern of "1" or "0" (that is, a binary font pattern). And "1" above,
It is necessary to develop each "0" into a foreground color code or a background color code, and write this developed color code into the display memory.

FIG. 9 is a block diagram showing a conventional example of an image data processing device.

The timing controller 20 controls the overall timing of the image data processing device.

Based on the timing given from the timing controller 20, the display controller 30
Create a display signal to display a screen such as a CRT.
That is, the display controller 30 outputs a display address corresponding to the display position on the screen to the display memory address bus 51 to access the display memory 40. The major timing at this time is also given from the timing controller 20.

Output data from the display memory 40 is sent to the parallel-to-serial conversion circuit 32 in the display controller 30 via a display memory data bus 53. Then, a display signal is created through predetermined processing in the display controller 30.

On the other hand, the CPU 60 executes the image processing program from the image processing program memory 61 and based on the data from the input/output interface 70.
An address and data to be written into the display memory 40 are prepared, and an image memory access request is transmitted to the timing controller 20. Here, the input/output interface 70 includes RS232C, modem interface, disk interface, mouse interface, etc.

Then, the timing controller 20 is
When an access request is received from the CPU 60, the display memory address buffer 52 and the display memory data bus buffer 54 are transferred at a timing that does not conflict with the display access of the display controller 30.
and enable. In parallel with this, CPU6
Grant execution permission to 0. In this way CPU6
0 can access the display memory 40 only at permitted timings.

The CPU 60 writes the image (display pattern) to the display memory 40 while repeating the above operation.

Now, consider a case where the pattern to be displayed is character information.

FIG. 10 is an explanatory diagram of color code development, showing an example of a character pattern to be converted into a color code and an example of a color code obtained by developing a part of the character pattern.

The character font is given as a binary value (data of 1 or 0) corresponding to the character code. For example, the display memory 40 stores 4 images of 16 colors for each dot.
Assume that the memory employs a bitmap method for holding bit information. Assume that the color code of the foreground color (the color of the displayed characters) is "1010" and the color code of the background color (the color of the background of the displayed characters) is "0100".

The CPU 60 converts the data of the above character font into 1
While checking the bits one by one, as shown in Figure 10, arrange the foreground color code or background color code according to whether the 1 bit is ``1'' or ``0'', and then The code is sent to the display memory 40 as write data.

Incidentally, unlike the above-mentioned bitmap method, most conventional display characters are of the character generator method. In the case of this character generator method, once the character code and attribute color code are written to the display memory, the expansion from the character code to the character font and the expansion from the character font to the display color code can be done using existing hardware. executed by the software. Therefore, the development of the color code in the character generator method is as follows.
Can be processed very quickly.

[Problems with conventional technology] However, in the bitmap method, the CPU
When the color code is developed into a color code, processing time is required, so there is a problem that the color code development takes a very long time.

This means that the CPU 60 is originally a byte or 2
Processing bytes (words) can be performed very easily and quickly, whereas expanding the data by checking it bit by bit, that is, expanding one byte of data into bit examples according to the pattern, is very easy and fast. Although it is not impossible to rearrange the data, it takes a very long time.

Although image display devices capable of bitmap graphic display are clearly more sophisticated than text display devices, the fact that their display processing takes a long time is a serious problem. In particular, there is a strong demand for shortening the development time when the same pattern data is repeatedly developed into color codes.

[Object of the Invention] The present invention has been made by paying attention to the problems of the prior art described above, and makes it possible to develop pattern data into color codes without the need for bit handling by the CPU. It is an object of the present invention to provide an image data processing device that can shorten the time required to repeatedly develop data into color codes.

[Summary of the invention] The present invention provides a method for repeating the same pattern data.
To ensure a quick expansion to the foreground color code or the background color color code, we keep the foreground color code in the foreground color register, the background color color code in the background color register, and use the rotator or The pattern data can be repeatedly used by the selector, and the foreground color register or the background color register can be selected according to the output value.

[Embodiment of the Invention] FIG. 1 is a block diagram showing a circuit showing an embodiment of the invention.

The main difference between this example and the conventional example shown in FIG. 9 is that a color code expansion circuit 10 is added.

In the above embodiment, when it becomes necessary to develop a color code, the CPU 60a sets necessary information in the color code development circuit 10. As a result, under the control of the timing controller 21, the color code expansion circuit 10 executes the color code expansion operation, and the obtained color code is stored in the display memory 4.
Written to 0. Therefore, as before
The processing speed is faster than when the CPU 60 develops color codes.

It should be noted that the same parts as those used in the conventional example shown in FIG. 9 are given the same reference numerals and the explanation thereof will be omitted.

FIG. 2 is a detailed block diagram showing the color code expansion circuit used in the above embodiment.

The foreground color register 11 is a register that holds the color code of the foreground color, and the background color register 12 is a register that holds the color code of the foreground color.
This register holds the color code of the background color.

In addition, the pattern rotator 13 holds pattern data to be developed into color codes, and
This is a register for rotating the pattern data. In the pattern rotator 13, the most significant bit and the least significant bit are connected to rotate the data. Therefore, the pattern rotator 13 is an example of pattern data repetition output means that holds pattern data to be developed into color codes and repeatedly outputs the pattern data.

The code selector 14 selectively outputs the foreground color code or the background color code according to the contents of the upper bits of the shift register 13. In addition, write address counter 15
is a register that holds the write address to the display memory 40, and the length counter 16 is the length information of the pattern data to be developed into a color code, and holds the horizontal length information of the screen. It is a counter.

Next, the operation of the above embodiment will be explained.

First, when the CPU 60a is given the color code of the foreground color and the color code of the background color to be developed,
The color code of the foreground color is set in the foreground color register 11, and the color code of the background color is set in the background color register 12.

Next, the above pattern data is set in the pattern rotator 13. Furthermore, the CPU60a is
After calculating the address to be written to the display memory 40, this address value is written to the address counter 1.
Set to 5. Then, the CPU 60a obtains horizontal pattern data to be developed, and sets this horizontal length information in the length counter 16.

The length counter 16 has its initial value set to all 1 (-1) by a reset signal.
While the length counter 16 is negative, no execution signal is given to the timing controller 21, so the color code expansion operation remains stopped.

Here, the 8× shown in the pattern of FIG.
The case of color code development for an 8-dot pattern will be explained.

The CPU 60a calculates the value obtained by subtracting 1 from the number of pattern data to be developed (the value of the number of dots - 1).
Set the length counter 16. In the case shown in FIG. 10, there are eight dots in the horizontal direction, so the length counter 16 is set to "7". Thereafter, an execution signal is given to the timing controller 21 to start the operation.

Thereafter, the timing controller 21 sends an enable signal at a timing when the display memory 40 can be accessed. As a result, the value of the write address counter 15 is output to the display memory address bus 51.

In parallel with this, the value of the foreground color register 11 or the background color register 12 is changed to the value of the code selector 1 according to the value of the upper bit of the pattern rotator 13.
4.

In other words, in the above example, if the upper bit of the rotator 13 is "1", the foreground color corresponds, and at this time, the color code "1010" of the background color held in the background color register 12 is the code It is output from the selector 14. Also, rotator 13
If the upper bit of is "0", it is assumed that the background colors correspond, and at this time, the color code "0100" of the background color held in the background color register 12 is output from the code selector 14.

The data of each color code selected as described above is output to the display memory data bus 53. Then, the timing controller 21 supplies a timing pulse to the display memory 40, and the selected data is written into the display memory 40.

After this, the timing controller 21 outputs a count pulse, counts the write address counter 15, decrements the length counter 16, and rotates the pattern rotator 13 to the left.

The above operation is repeatedly executed for each bit of data held in the pattern rotator 13, and when the value of the length counter 16 reaches "-1", an execution signal is output from the length counter 16. It disappears. As a result, the color code development operation described above is stopped.

The CPU 60a recognizes that the execution of the color code expansion operation has been stopped by reading the value of the length counter 16, by noticing an interrupt signal generated by the execution signal, or the like. As a result, the pattern data to be developed next, the address to be written into the display memory 40, and the horizontal length data on the screen to be converted into a color code are set in each counter, etc. Then, based on the above data, data for one column is written in the display memory 40, and these operations are repeated for the necessary columns.
Complete writing of one character.

In the above embodiment, the case where the color code is developed for a pattern of 8×8 dots was explained, but 32
It is also possible to develop a color code for a pattern of any size, such as ×32 dots, and the more efficient the development time is, the more the color code is developed for a pattern with a larger number of dots in the horizontal direction.

By the way, after the pattern data (for example, 16-bit data) sent from the CPU 60a is held in the pattern rotator 13, bit 15
(Most significant bit) data is code selector 14
When the data is converted into a color code, the pattern rotator 13 rotates by one. In this case, bit 15 immediately before rotating
The data moves to bit 0.

Then, when the second data in the pattern rotator 13 is converted into a color code, the pattern rotator 13 is rotated by one again, and the data of bit 15 immediately before it is transferred to bit 0.
When this operation is repeated and the 16-bit data is converted into a color code, the same data as the 16-bit data is set in the pattern rotator 13.

Here, in order to set data different from the pattern data already set in the pattern rotator 13, the pattern data may be written and held again from the CPU 60a.

If the same pattern data is to be developed into a color code again, since that pattern data is set in the pattern rotator 13, the CPU
60a eliminates the need to reset pattern data.

Therefore, if you use the same pattern data multiple times and develop it into a color code, the CPU 60a
This eliminates the need to set pattern data each time. For this purpose, when repeating the same pattern data and developing it into a color code,
The expansion operation becomes faster.

In the above description, the case where the value of the write address counter 15 and the memory address of one dot in the display memory 40 correspond one to one has been described. Incidentally, there are cases where information on a plurality of dots is held at one address in the display memory 40, and the present invention can be applied to this case as well. However, in this case, it is necessary to add a predetermined function to the timing controller 21. However, since this is not directly related to the present invention, its explanation will be omitted.

FIG. 3 is a block diagram showing details of the timing controller 21.

FIG. 4 is a timing diagram showing the operation of the timing controller 21.

The memory cycle of display memory 40 is divided into two time slots (display time slot and CPU time slot).

In the above display time slot, the display address is always supplied from the display address circuit 31 or the parallel-to-serial conversion circuit 32, and at the start of the memory cycle, the display data is read out and the shift in the display controller 30 is performed by the load pulse signal. Load it into the register 32.

On the other hand, in the CPU time slot, the CPU
When a CPU request signal and a CPU write signal are accepted from 60a, it becomes active.

The CPU clock and the timing controller clock usually have independent oscillators, so from the perspective of the timing controller 21,
CPU request signals are generated asynchronously.

The timing controller 21 synchronizes the CPU request signals and performs waiting. By returning a wait signal for this rendezvous
CPU6 until a CPU request is accepted.
Wait for execution of 0a.

When a CPU request is accepted, its
In the CPU time slot memory cycle,
Read or write is executed depending on the value of the CPU write signal. During execution of this memory cycle, the buffer enable signal is turned on, so
Address is supplied from CPU.

When the CPU write signal is "0", read data from the memory is transmitted to the data bus of the CPU 60a. On the other hand, when the CPU write signal is "1", the bus direction signal is "1", so data is supplied from the data bus of the CPU 60a. Furthermore, a memory write signal is transmitted to the display memory 40, and writing is executed.

The execution signal from the color code expansion circuit 10 is
CPU request signal from CPU60a and
It is processed by the timing controller 21 in exactly the same way as the CPU write signal. However, the wait signal and buffer enable signal are handled by the requester.
It is prohibited because it is not a CPU60a. instead of,
A count pulse signal is returned to the color code expansion circuit 10 at the timing of the memory write signal, and an enable signal is returned to the color code expansion circuit 10 at the timing of the buffer enable signal.

The write address and color code data are output to the respective buses by the enable signal. At the same time, writing is executed by the memory wait signal, and at the same time as the writing is completed, the contents of each register and each counter are updated by the count pulse signal.

When the length counter is set to a positive value, the execution signal becomes "1". Writing of the foreground and background colors corresponding to the dot pattern into the display memory 40 as color code data is started. Each time one dot is written, the length counter counts down and eventually reaches "0".

When the length counter is "0", the execution signal is still being output, so another write is executed.
As a result, the length counter becomes -1 (FF), the execution signal becomes "0", and the execution is stopped.
As a result, one more execution than the value set in the length counter 16 is performed. This execution is all executed based on the timing of the timing generation circuit TG, so there is no need for waiting. Furthermore, since all adjacent CPU time slots are effectively executed, processing is completed very quickly.

In the above embodiment of the timing controller,
Since the CPU request signal and the execution signal are made equal (simply ORed), the display memory 40 cannot be accessed until the color code development is completed.

By using a timing controller that controls the CPU request signal and execution signal based on priority, it is easy to enable CPU access even during color code expansion.

FIG. 5 is a block diagram showing another example of the circuit on which the present invention is based, and FIG. 6 is a diagram showing details of the color code expansion circuit shown in FIG. 5.

In this example, the write address counter 15 and length counter 16 are omitted from the embodiment shown in FIG. In this case, the functions of the write address counter 15 and length counter 16 are as follows.
The CPU 60a will execute it.

That is, continuous automatic execution in color code development is executed by the CPU 60a, and the counters 15 and 16
The color code expansion circuit 10a other than the color code expansion circuit 10a is configured to execute only simple color code expansion. In this case, the role of the CPU 60a increases a little, but the performance of the system as a whole is improved compared to the conventional system.

FIG. 7 is a block diagram showing another embodiment of the invention.

The embodiment shown in FIG. 7 uses a pattern data register 13a instead of the pattern rotator 13 in the color code development circuit 10 shown in FIG.
, a data selector 13b, and a counter 13c.

The pattern data register 13a holds pattern data to be developed into color codes, and the data selector 13b sequentially selects pattern data from the pattern data register 13a. The counter 13c outputs count data in ascending or descending order as a select signal for the data selector 13b.

The pattern data register 13a, data selector 13b and counter 13c hold pattern data to be developed into color codes, and
This is an example of a pattern data repetition output means for repeatedly outputting pattern data.

Further, the code selector 14 is a selector that selects a foreground color code or a background color code in accordance with the output of the data selector 13b.

The operation of the color code expansion circuit 10b shown in FIG. 7 is basically the same as that of the color code expansion circuit 10 shown in FIG.

The difference is that the pattern data register 13a is
The data selector 13b receives and holds pattern data from the CPU 60a, outputs one bit from the upper bit of the pattern data one by one, and the code selector 14 selects the foreground color or background color based on the output bits. . Further, the data selector 13b differs from the case shown in FIG. 2 in that the data selector 13b sequentially outputs one bit at a time from the pattern data register 13a in accordance with the output signal of the counter 13c. Note that the pattern position at which the color code development is desired to be started is set in the counter 13c by the CPU 60a.

Then, after outputting all the data (for example, 8-bit data) captured and held from the CPU 60a, the counter 13c repeats the output, so that the color code development can be repeated for the same pattern data.

In this case, it is only necessary to write the pattern data into the pattern data register 13a once, so the time required for the writing can be omitted.

Note that the data selector 13b is the counter 13
Since the pattern data is output one bit at a time in response to the output signal c, conversion to a color code can be started even from the midpoint of the pattern data register 13a.

FIG. 8 is a block diagram showing a modification of the example shown in FIG. 7.

In the example shown in FIG. 8, the write address counter 15 and length counter 16 are omitted from the example shown in FIG. 7, and a bit position counter 17 is added. In this case, the functions of the write address counter 15 and length counter 16 will be executed by the CPU 60a.

That is, continuous automatic execution in color code development is executed by the CPU 60a, and the counters 15 and 16
The color code expansion circuit 10c excluding the color code expansion circuit 10c executes only simple color code expansion. In this case, the role of the CPU 60a increases a little, but the performance of the system as a whole is improved compared to the conventional system.

[Effects of the Invention] According to the present invention, when writing display data to the display memory, when repeating the same pattern data and developing it into a color code, the overall size of the pattern can be freely specified, and the circuit This has the effect that overall control is simple.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing one embodiment of the present invention. FIG. 2 is a block diagram showing a color code expansion circuit used in the above embodiment. FIG. 3 is a circuit diagram showing the timing controller in the above embodiment. FIG. 4 is a timing diagram showing the operation of the timing controller shown in FIG. 3. FIG. 5 is a block diagram showing another embodiment of the present invention. FIG. 6 is a block diagram showing a color code development circuit in the embodiment shown in FIG. FIG. 7 is a block diagram of a color code expansion circuit showing another embodiment of the present invention. Figure 8 shows the 7th
FIG. 3 is a block diagram showing a modification of the embodiment shown in the figure. FIG. 9 is a block diagram showing a conventional example of an image data processing device. FIG. 10 is an explanatory diagram of color code development. 10, 10a, 10b, 10c...color code expansion circuit, 11...foreground color register, 12...background color register, 13...pattern rotator, 13a...pattern data register, 13b...data selector,
13C...Counter, 14...Code selector, 15
...Write address counter, 16...Length counter, 21d...Timing controller, 30...Display controller, 60a...CPU.

Claims (1)

[Scope of Claims] 1. In an image data processing device that writes and processes display data in a display memory, a foreground color register that holds a color code of a foreground color; a background color register that holds a color code of a background color; and a color code. a rotator that holds pattern data to be expanded into a pattern data and repeatedly outputs the pattern data by concatenating the most significant bit and the least significant bit; a code selector that selects the color code of the foreground color or the background color; a write address counter that holds a write address to the display memory; and a write address counter that holds information about the horizontal length of the pattern data on the screen. An image data processing device comprising: a length counter; 2. In Claim 1, a timing controller that generates write timing to the display memory, count timing of the write address counter, shift timing of the pattern shift register, and count timing of the length counter. An image data processing device comprising: