CA1228931A - Display control unit - Google Patents
Display control unitInfo
- Publication number
- CA1228931A CA1228931A CA000474619A CA474619A CA1228931A CA 1228931 A CA1228931 A CA 1228931A CA 000474619 A CA000474619 A CA 000474619A CA 474619 A CA474619 A CA 474619A CA 1228931 A CA1228931 A CA 1228931A
- Authority
- CA
- Canada
- Prior art keywords
- data
- display
- display control
- control unit
- register
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Expired
Links
Classifications
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/001—Arbitration of resources in a display system, e.g. control of access to frame buffer by video controller and/or main processor
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G2360/00—Aspects of the architecture of display systems
- G09G2360/12—Frame memory handling
- G09G2360/127—Updating a frame memory using a transfer of data from a source area to a destination area
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/22—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of characters or indicia using display control signals derived from coded signals representing the characters or indicia, e.g. with a character-code memory
- G09G5/24—Generation of individual character patterns
- G09G5/246—Generation of individual character patterns of ideographic or arabic-like characters
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
- G09G5/393—Arrangements for updating the contents of the bit-mapped memory
-
- G—PHYSICS
- G09—EDUCATION; CRYPTOGRAPHY; DISPLAY; ADVERTISING; SEALS
- G09G—ARRANGEMENTS OR CIRCUITS FOR CONTROL OF INDICATING DEVICES USING STATIC MEANS TO PRESENT VARIABLE INFORMATION
- G09G5/00—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators
- G09G5/36—Control arrangements or circuits for visual indicators common to cathode-ray tube indicators and other visual indicators characterised by the display of a graphic pattern, e.g. using an all-points-addressable [APA] memory
- G09G5/39—Control of the bit-mapped memory
- G09G5/395—Arrangements specially adapted for transferring the contents of the bit-mapped memory to the screen
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- Engineering & Computer Science (AREA)
- Multimedia (AREA)
- Physics & Mathematics (AREA)
- Computer Hardware Design (AREA)
- General Physics & Mathematics (AREA)
- Theoretical Computer Science (AREA)
- Controls And Circuits For Display Device (AREA)
Abstract
ABSTRACT OF THE DISCLOSURE
A display control unit is disclosed which is capable to change the processing form of a central processing unit (CPU) for increased processing speeds. In this display control unit, when the execution time of its display operation is reduced by reading out data in a source area from a memory unit and then writing the read-out data sequentially into a destination area, a predetermined period of time before the beginning of a vertical or horizontal retrace, the CPU is interrupted so that the CPU can omit its confirmation as to whether a video CPU has completed its previous processing. Also, in this display control unit, an updating processing of color specification in display data can be performed at increased speeds, only desired dots on a display screen can be logically operated, a form or an object having a solid body on a transparent background within a source area can be transferred at higher speeds, and an expansion memory can be used as a "kanji(chinese character)"
ROM (pattern memory) or the like.
A display control unit is disclosed which is capable to change the processing form of a central processing unit (CPU) for increased processing speeds. In this display control unit, when the execution time of its display operation is reduced by reading out data in a source area from a memory unit and then writing the read-out data sequentially into a destination area, a predetermined period of time before the beginning of a vertical or horizontal retrace, the CPU is interrupted so that the CPU can omit its confirmation as to whether a video CPU has completed its previous processing. Also, in this display control unit, an updating processing of color specification in display data can be performed at increased speeds, only desired dots on a display screen can be logically operated, a form or an object having a solid body on a transparent background within a source area can be transferred at higher speeds, and an expansion memory can be used as a "kanji(chinese character)"
ROM (pattern memory) or the like.
Description
3~
The present invention relates to an improved display control unit for computer systems.
The background of the invention and the invention itself will now be described in greater detail with reference to the accompanying drawings, in which:
Figure 1 is a block diagram of a typical example of prior art color display unit;
Figure 2 is a block diagram of a display control circuit employed in the prior art color display unit of Figure 1, Figure 3 is a b]ock diagram of an example of VRAM used in the color display unit of Figure l illustrating the transfer operation of a block data;
Figure 4 is block diagram o:E a display control unit according to the present invention;
Figures 5 and 6 are viewsto illustrate the contents of the respec-tive registers employed in the circuit of Figure 4;
Figure 7 is a view to illustrate the command codes used in the inventioil;
Figure 8 is a view to illustrate a logical operation used in the invention;
Figure 9 is a timing view of another embodiment of the invention;
Figure 10 is a circuit diagram of main portions of the embodiment of Figure 9;
Figure 11 is a block diagram of still another embodiment of the invention; and Figure 12 is circuit diagram of main portions of the embodiment shown in Figure 11.
8~-08 - 1 -
The present invention relates to an improved display control unit for computer systems.
The background of the invention and the invention itself will now be described in greater detail with reference to the accompanying drawings, in which:
Figure 1 is a block diagram of a typical example of prior art color display unit;
Figure 2 is a block diagram of a display control circuit employed in the prior art color display unit of Figure 1, Figure 3 is a b]ock diagram of an example of VRAM used in the color display unit of Figure l illustrating the transfer operation of a block data;
Figure 4 is block diagram o:E a display control unit according to the present invention;
Figures 5 and 6 are viewsto illustrate the contents of the respec-tive registers employed in the circuit of Figure 4;
Figure 7 is a view to illustrate the command codes used in the inventioil;
Figure 8 is a view to illustrate a logical operation used in the invention;
Figure 9 is a timing view of another embodiment of the invention;
Figure 10 is a circuit diagram of main portions of the embodiment of Figure 9;
Figure 11 is a block diagram of still another embodiment of the invention; and Figure 12 is circuit diagram of main portions of the embodiment shown in Figure 11.
8~-08 - 1 -
2;~93~
In Figure 1, there is illustrated a block diagram of a convcntional color graphics display unit.
As shown in Figure 1, there is provided a CPU microprocessor) 1 to control a whole system, and to this CPU 1 are connected a main memory 2 and a display control circuit 3. The main memory 2 is dedicated to holding programs and data, and the display control circuit 3 is used to control the color graphics display. Reference character 4 designates a VRAM (video memory) to hold data for CRT display, and character 5 represents a CRT color display unit.
Figure 2 shows a block diagram of an example of the display control circuit 3 illustrated in Figure 1.
In this example, a timing controller 11 generates a clock signal which is in turn inputted to a counter 12 having a column counter and a line counter. This counter 12 is then operated to generate a synchronous signal for CRT display via a display timing circuit 13. On the other hand, the counter 12 creates display addresses which are then outputted as VRA~I addresses via a multiplexer 15.
Read data for display access coming from VR~ 4 are inputted to a video output controller 20 via a buffer 19 to produce CRT video signals.
On the other hand, when CPU 1 tries to access VRA~I 4, the addresses of VR~I 4 are set in a VR~I address register 14. If a write strobe is input to a CPU interface controller lS, then the multiplexer 15 selects the outputs of the VRAM address register 14 given by CPU 1 as VRA~I addresses, and also the write data from CPU 1 is written into VR~I 4 via buffers 16, 17.
Figure 3 illustrates an example of the VRA~I 4 which has a series of physical addresses as a memory unit. Logically, it has a display screen as shown alld the display screen comprises 256 horizontal dots x 1024 vertical ~2~ 3~
slots.
Norlnally, a d;splay screen is physically composed of 2~ vertical jots. '['heret'orc), tho logical existence of 1()24 vertical do-ts means that the screen has unohservocl areas or that a pLurality of screerls are present.
Now let us consider an example: On the display screen shown in Fig-ure 3, coordinates ot' X, Y are used to superpose the color code block data in the source area within VIM 4 on the color code clata in the destination area (area to which cla-ta is transt'errecl).
CPU 1 calculates the physical addresses of the VRAM 4 based on the coordinates (Sx, Sy) in the source area and then sets them in the VIM address register 14 within the display control circuit 3. CPIJ 1 also produces a read colllmarl(l outllut so as to reacl the color cocle d,l-ta witllin the VRAM 4 correspond-ing to tho coorclillates (Sx, Sy).
Noxt, ('PlJ I calcul.ltos the pllysical addresses within the VRAM 4 hased on tho coor(lincltes (Dx, L)y) in lie destillation area to which the data is to bo tralls~orrecl and sets thelD in the VR~M address register 14 within theclisplay control circuit 3. I-lere aguill, CPlJ L outputs a read command to readthe color cocle data withill the VR~M 4 correspollclillg -to the Coordinates (Dx, Dy), alld thell ol)tains the l oE (i.e., ORs) the color code data within the VR~M 4 and the color cocle data frolll the al)ove-mentioned coordillates (Sx, Sy). Then, CPU 1 outputs a wr-ite comlllalld to write the ORed color code clata into the VRAM
4, in particular, a location of the VR~M 4 corresponding to the coordinates ~l)x, L)Y) accordingly, the above-mentioned Read/Read/Logical operation/Write secluellce is repeated NX times with respect to a horizontal direction and NY
times with respect to ,a vertical directioll (that is No x NY times) so as to 1~28~31 superpose the source area color code data on the destination area color code data.
In order to meet the demands for realization of cornpact computers and reduced costs, such conventional display control unit for personal com-puters is designed to reduce the amounts of its hardware, e.g. the number of gates and IC elements used, involving the internal structure of the display control unit and its associated interfaces. This, however, results in increas-ed load Oll the software accordingly.
As can be seen from the above-mentioned example, namely, the color code data transfer/superposition, in the prior art personal computer display control units, all of the processings must be performed by CPU 1 and thus it takes quite a lot of time to execute these processings.
In another aspect o:E the conventional display control unit, CPU 1 and Display Control Circult 3 are operated independently of each other, and the display timing of the display control circuit 3 has priority over the VRAM
timing of the CPU 1. As a result of this, a wait time arises in access from CPU 1 to VRAM I, which results in a greatly reduced efficiency of the data trans:Eer.
In other words, in the above-mentioned prior art, the software must share a heavy load in the display control and thus it takes a very long time to execute its operation. When a computer is upgraded with increased display specifications and with a plurality of display modes, then its address cal-culation becomes more complicated and thus it will take an extended period of time to perform its running operation.
Also, in the market there is an urgent need for not only reduction of the single block data transfer running time but also for reduction of the ~228~3~L
transfer run time for various kinds of block data. Further, there exists a need for other elements.
For example, the following are necessary: to replace the CPU
processing mode during a retrace period by that during a display period; to speed up the updating process of specifying color in the color data; to per-form a logical operation for only desired dots on the display screen; and, to transfer at higher speeds a form or an object having a solid body on a trans-parent background within a source area. Further, it is desired to be able to display "kanji" patterns fast so as to facilitate accommodation of the kanji.
The present invention aims at eliminating the drawbacks in the above-mentioned prior art display control unit as well as meeting the demands currently requested in the market.
Accordingly, it is a primary object of the invention to provide an improved display control unit which, when a run time for a display operation is reduced by reading out data within a source area and writing the read-out data sequentially into a destination area, is able to speed up a command pro-cessing during a vertical or horizontal retrace period.
It is another object oE the invention to provide a block data trans-fer device which is capable of speeding up an updating processing of specifying color in display data.
It is another object of the invention to provide a display control unit which is capable of performing a logical operation for only desired dots on a display screen.
It is still another object of the invention to provide a display control unit which is capable of transferring at high speeds a form or an object having a solid body on a transparent background within a source area.
_ ~22893~
It is yet another object of the invention to provide a memory expansion system in which an expansion memory can be em-ployed as a "kanji" ROM (pattern memory) or as a buffer area.
In accomplishing these objects, accordiny to the inven-tion, there is provided an improved display control unit in which the processing form of its CPU can be modified, that is, when the execution time of its display operation is reduced by reading out data in a source area from within a memory unit and sequentially writing the read-out data into a destination area, a predeter-mined period of time before the beginning of a vertical retracethe CPU is interrupted so that the CPU can omit its confirmation as to whether a video CPU has completed its previous processing.
According to another aspect, the invention provides a display control unit for providing screen image information and a control signal to a display unit, said display control unit comprising a destination register for reading and storing display data at a destination address to be written by a central proces-sing unit (CPU), and a write register for holding data to be written, wherein a portion of said display data is combined with a portion of said data to be written to modify said display data, and said modified display data is written into said destination address so as to be able to change a portion of a word in a dis-play memory.
The above and other related objects and features of the invention will be apparent from a reading of the following description found in the accompanying drawings and the novelty ~6--33~L
thereof pointed out in the appended claims.
In Figure 4,there is illustrated a block diagram of a display control circuit according to the invention.
In the illustrated embodiment, there are provided a clock generator 31 to generate a display timing clock and a counter 32 which comprises a column counter to generate a CRT screen dis-play timing and a VRAM address in accordance with the display timing clock, a line counter, and a row counter.
Data bus 41 from CPU l is connected via Buffer 42 to Register bus 43. The number of registers within a display control circuit 3 accessed by CPU l is held by a register pointer/counter 44 and the outputs of this register pointer/counter 44 are decoded by a register selector decoder 45, so that the registers can be specified individually. In addition to this register function, ! -6a-
In Figure 1, there is illustrated a block diagram of a convcntional color graphics display unit.
As shown in Figure 1, there is provided a CPU microprocessor) 1 to control a whole system, and to this CPU 1 are connected a main memory 2 and a display control circuit 3. The main memory 2 is dedicated to holding programs and data, and the display control circuit 3 is used to control the color graphics display. Reference character 4 designates a VRAM (video memory) to hold data for CRT display, and character 5 represents a CRT color display unit.
Figure 2 shows a block diagram of an example of the display control circuit 3 illustrated in Figure 1.
In this example, a timing controller 11 generates a clock signal which is in turn inputted to a counter 12 having a column counter and a line counter. This counter 12 is then operated to generate a synchronous signal for CRT display via a display timing circuit 13. On the other hand, the counter 12 creates display addresses which are then outputted as VRA~I addresses via a multiplexer 15.
Read data for display access coming from VR~ 4 are inputted to a video output controller 20 via a buffer 19 to produce CRT video signals.
On the other hand, when CPU 1 tries to access VRA~I 4, the addresses of VR~I 4 are set in a VR~I address register 14. If a write strobe is input to a CPU interface controller lS, then the multiplexer 15 selects the outputs of the VRAM address register 14 given by CPU 1 as VRA~I addresses, and also the write data from CPU 1 is written into VR~I 4 via buffers 16, 17.
Figure 3 illustrates an example of the VRA~I 4 which has a series of physical addresses as a memory unit. Logically, it has a display screen as shown alld the display screen comprises 256 horizontal dots x 1024 vertical ~2~ 3~
slots.
Norlnally, a d;splay screen is physically composed of 2~ vertical jots. '['heret'orc), tho logical existence of 1()24 vertical do-ts means that the screen has unohservocl areas or that a pLurality of screerls are present.
Now let us consider an example: On the display screen shown in Fig-ure 3, coordinates ot' X, Y are used to superpose the color code block data in the source area within VIM 4 on the color code clata in the destination area (area to which cla-ta is transt'errecl).
CPU 1 calculates the physical addresses of the VRAM 4 based on the coordinates (Sx, Sy) in the source area and then sets them in the VIM address register 14 within the display control circuit 3. CPIJ 1 also produces a read colllmarl(l outllut so as to reacl the color cocle d,l-ta witllin the VRAM 4 correspond-ing to tho coorclillates (Sx, Sy).
Noxt, ('PlJ I calcul.ltos the pllysical addresses within the VRAM 4 hased on tho coor(lincltes (Dx, L)y) in lie destillation area to which the data is to bo tralls~orrecl and sets thelD in the VR~M address register 14 within theclisplay control circuit 3. I-lere aguill, CPlJ L outputs a read command to readthe color cocle data withill the VR~M 4 correspollclillg -to the Coordinates (Dx, Dy), alld thell ol)tains the l oE (i.e., ORs) the color code data within the VR~M 4 and the color cocle data frolll the al)ove-mentioned coordillates (Sx, Sy). Then, CPU 1 outputs a wr-ite comlllalld to write the ORed color code clata into the VRAM
4, in particular, a location of the VR~M 4 corresponding to the coordinates ~l)x, L)Y) accordingly, the above-mentioned Read/Read/Logical operation/Write secluellce is repeated NX times with respect to a horizontal direction and NY
times with respect to ,a vertical directioll (that is No x NY times) so as to 1~28~31 superpose the source area color code data on the destination area color code data.
In order to meet the demands for realization of cornpact computers and reduced costs, such conventional display control unit for personal com-puters is designed to reduce the amounts of its hardware, e.g. the number of gates and IC elements used, involving the internal structure of the display control unit and its associated interfaces. This, however, results in increas-ed load Oll the software accordingly.
As can be seen from the above-mentioned example, namely, the color code data transfer/superposition, in the prior art personal computer display control units, all of the processings must be performed by CPU 1 and thus it takes quite a lot of time to execute these processings.
In another aspect o:E the conventional display control unit, CPU 1 and Display Control Circult 3 are operated independently of each other, and the display timing of the display control circuit 3 has priority over the VRAM
timing of the CPU 1. As a result of this, a wait time arises in access from CPU 1 to VRAM I, which results in a greatly reduced efficiency of the data trans:Eer.
In other words, in the above-mentioned prior art, the software must share a heavy load in the display control and thus it takes a very long time to execute its operation. When a computer is upgraded with increased display specifications and with a plurality of display modes, then its address cal-culation becomes more complicated and thus it will take an extended period of time to perform its running operation.
Also, in the market there is an urgent need for not only reduction of the single block data transfer running time but also for reduction of the ~228~3~L
transfer run time for various kinds of block data. Further, there exists a need for other elements.
For example, the following are necessary: to replace the CPU
processing mode during a retrace period by that during a display period; to speed up the updating process of specifying color in the color data; to per-form a logical operation for only desired dots on the display screen; and, to transfer at higher speeds a form or an object having a solid body on a trans-parent background within a source area. Further, it is desired to be able to display "kanji" patterns fast so as to facilitate accommodation of the kanji.
The present invention aims at eliminating the drawbacks in the above-mentioned prior art display control unit as well as meeting the demands currently requested in the market.
Accordingly, it is a primary object of the invention to provide an improved display control unit which, when a run time for a display operation is reduced by reading out data within a source area and writing the read-out data sequentially into a destination area, is able to speed up a command pro-cessing during a vertical or horizontal retrace period.
It is another object oE the invention to provide a block data trans-fer device which is capable of speeding up an updating processing of specifying color in display data.
It is another object of the invention to provide a display control unit which is capable of performing a logical operation for only desired dots on a display screen.
It is still another object of the invention to provide a display control unit which is capable of transferring at high speeds a form or an object having a solid body on a transparent background within a source area.
_ ~22893~
It is yet another object of the invention to provide a memory expansion system in which an expansion memory can be em-ployed as a "kanji" ROM (pattern memory) or as a buffer area.
In accomplishing these objects, accordiny to the inven-tion, there is provided an improved display control unit in which the processing form of its CPU can be modified, that is, when the execution time of its display operation is reduced by reading out data in a source area from within a memory unit and sequentially writing the read-out data into a destination area, a predeter-mined period of time before the beginning of a vertical retracethe CPU is interrupted so that the CPU can omit its confirmation as to whether a video CPU has completed its previous processing.
According to another aspect, the invention provides a display control unit for providing screen image information and a control signal to a display unit, said display control unit comprising a destination register for reading and storing display data at a destination address to be written by a central proces-sing unit (CPU), and a write register for holding data to be written, wherein a portion of said display data is combined with a portion of said data to be written to modify said display data, and said modified display data is written into said destination address so as to be able to change a portion of a word in a dis-play memory.
The above and other related objects and features of the invention will be apparent from a reading of the following description found in the accompanying drawings and the novelty ~6--33~L
thereof pointed out in the appended claims.
In Figure 4,there is illustrated a block diagram of a display control circuit according to the invention.
In the illustrated embodiment, there are provided a clock generator 31 to generate a display timing clock and a counter 32 which comprises a column counter to generate a CRT screen dis-play timing and a VRAM address in accordance with the display timing clock, a line counter, and a row counter.
Data bus 41 from CPU l is connected via Buffer 42 to Register bus 43. The number of registers within a display control circuit 3 accessed by CPU l is held by a register pointer/counter 44 and the outputs of this register pointer/counter 44 are decoded by a register selector decoder 45, so that the registers can be specified individually. In addition to this register function, ! -6a-
3~
the register pointer/counter 44 has a count-up function. That is, in setting parameters of the respective registers, after one setting has been completed, it counts up 1. Thus, the registers can be automatically specified successive-ly one by one.
Command Register 46 holds the command information -from CPU 1, and Video CPU 47 processes the display data in accordance with the cornmands from CPU 1. SR Register 48 holds the status from Video CPU 47 to CPU 1. ~Yhen CPU 1 specifies the physical address of VRAM 4 to access the VRAM 4, the VRAM
address is to be held by VRAM Address Register/Counter 37. Color Code Register 33 holds the read data from VRAM 4 as well as the write data to VRA~I 4.
The features of the invention include the below-mentioned component elements:
At first, there are included SX Register/Counter 38 to hold the values on X coordinates existing in a horizontal direction within a source area, SY Register/Counter 39 to hold the values on Y coordinates in a vertical direction and SXY Address Composing Circuit 40 to create the physical address of VRAM in accordance with the respective outputs of SX, SY Register/
Counter 38, 39.
Also, there are provided DX Register/Counter 58 to hold the values on the horizontal X coordinates of a destination area, DY Register/Counter 59 to hold the values on the vertical Y coordinates of the same and DXY
Address Composing circuit 57 to create the physical address of VRAM 4 in accordance with the respective outputs of DX, DY Register/Counters 58, 59.
The above-mentioned SX, SY, DX, DY Register/Counters 38, - ~22~3931 39, 58, 59 have not only a register function but also an up/down counter function, respectively.
Further, VRAM Address ~U9 36,which i8 contained within the display control circuit 3, ls connected through Buffer 55 to Address Line 56 of VRAM 4. VRAM Da-ta Bus 35, which is also contained in the display control circuit 3, is connected through Buffer 53 to VRAM Data Line 54.
NX Register 61 holds the transfer data number in a hori-zontal direction (that is, a direction of the X coordinates), while NY Register 63 holds the transfer data number in a vertical direction (that iSJ a direction of the Y coordinates).
There is provided a horizontal direction flag 60 which points to a positive direction (or, right direction) when it is "O"
and points to a negative direction (or, left direction) for "O". A vertical direction flag 62 indicates a positive direction (or, downward directlon) when it is "O", and a negative direction (or, upward direction) for "1". S Register 34 holds the read data from the source area, and D Register 52 holds the read data from the clestination area. ALU (ari-thmetic and logic unit) 51 performs logical operations such as IMP, AND, 0~, EOR, NOT operatlons of the outputs of S
Register 34, Color Code Register 33 and D Register 52 in accordance with the control from Video CPU 47.
~L22893~
IL Register 70 is used to previously set the number of columns, lines, or rows for IL interruptions, while Comparator 71 is dedicated to detecting the correspondence of the number of the columns, lines, or rows set by IL
Register 70.
Referring now to Fig. 10, Source Data Bit Selector 101 selects higher 4 bits or lower 4 bits from the source data and then uses the selected 4 bits to form higher 4 bits or lower 4 bits. Byte Data Selector 102 selects the data which has passed through Source Data Bit Selector 101 or the source data from S Reg:Lster 34.
Transparence Detection Circui-t 104 serves to detect a color code (that is, transparency) for a portion of the source area in which no object exists.
Parallel Bit Selector 103 causes omission of logical operations of some of the color codes within the destina-tion area which corresponds to the color code within the source area, provided that the very source area color code happens to be transparent.
Referring to Fig. 11, Expansion Memory 111 is used as "kanji" ROM(Battern Memory) or a buffer area.
Referring to Fig. 12, Slot Switch 121 is dedicated to switching a video request or a process request.
1~:28~3~
ARGR Switch 123 is used to switch a request to a video request or a process request in accordance with the respective bits of an argument register.
The foregoing elements are the characteristic ones of the present invention. Although there exlst other elements than the foregoings in the display control circuit 3, an explanation is omitted here regarding such elements as not necessary in describing the operation of the invention.
Next, we will describe the operation of the above-mentioned embodiment.
First, the operation of the display control circuit 3 is described, by way of example, in connection with the bloclc data transfer/superposition based on X, Y coordinates.
It is necessary that CPU l has previously set informa-tion necessary for the logical operation and block data transf`er in the respective registers of the display control circuit 3. When accessing the respective reglsters shown in Figs. 5 and 6, CPU l sets the register number of a register to be accessed in a register pointer/cdunter 44 and there-after performs its read/write operation.
When the source area color code data within VRAM 4 and the destination area color code area are ORed and super-posed on each other, "100100107' is to be set in Register #146 33~
(Command Register). Its higher 4 bits "1001" represents a command code shown in Figure 7 block data transfer from VRAM 4 to VR~I 4 with a logical opera-tion), while its lower 4 bits "0010" expresses an OR shown in Figure 8.
Also, when such block data as shown in Figure 3 is to be processed, it is necessary to set up the following parameters: The start coordinates (SX, SY) of the source area are set in SX Register/Counter 38 and SY Register/
Counter 39, respectively. SX Register/Counter 38 is composed of SXL (Register #132) and SXH (Register #133), while SY Register/Counter 39 is composed of SYL (Register #134) and SYH (Register #135). Therefore, CPU 1 sets a 4-byte parameter on the transfer starting point or the starting coordinates (SX, SY).
By the way, Figure 5 illustrates the contents of Registers #132-142, and Figure 6 illustrates the contents of Registers #143 - 146 as well as the contents of Registers ~t2, tt8.
Then, the destination area start coordinates (DX, DY) are set in DX Register/Counter 58 and DY Register/Counter 59. DX Register/Counter 58 is composed of DXL (Register ~tl36) and DXI-I (Register #137), while DY Register/
Counter 59 is composed of DYL, (Register #138) and DYI-I (Register #139).
Next, the number NX of data to be transferred to a horizontal direc-tion (a direction of the X coordinates) is set in NX Register 61 and the num-ber NY of data to be transferred to a vertical direction (a direction of the Y coordinates) is set in NY Register 63. NX Register 61 is composed of NXL
(Register #140) and NXH (Register #141), while NY Register 63 is composed of NYL (Register #142) and NYH (Register ~tl43).
Since the block data to be transferred to both of the X, Y direc-tions when viewed from the start coordinates (SX,SY) are in a positive direc-tion, "O" is set in both of Direction Flag 60 and Direction Flag 62. Direction ,. .~
~22~g3~_ Flag 60 corresponds to the bit 3 of Argument Register ARGR register #145~, and Direction Flag 62 to the bit 2 of Argument Register ARGR (Register #145).
When all of the foregoing settings have been effected J it is considered that the setting of parameters necessary for transfer of the block data has been completed. These parameter settings are to be performed successively from Register #132 to Register #145. First, "32" is set in Register Pointer/Counter 44. Then, it is necessary only to write the parameters successively so that the associated registers can be set up sequentially. After then, Register Pointer/Counter 44 is caused to point to Register #146 and is in a position to wait for setting o:E a command code.
Figure 7 is a table to illustrate command codes.
In this figure, "VDC" stands for the display control circuit 3.
Figure 8 is a table to illustrate logical operations. In this fig-ure, SC represents a source color code and DC stands for a destination color code.
CPU 1 creates command codes such as "10010010" in accordance with the above-mentioned command codes and logical operation codes and then sets them in Command register 46 register #146).
The higher 4 bits of the above-mentioned command code express an instruction to transfer a block data within VRA~I 4 provided that the source area and the destination area are both present within the VRAM 4. On the other hand, the lower 4 bits of the above example represent a logical operation code, that is, "0010" means tha-t the OR of the source color code data and the destination color code data before transferred is to be written into the destination.
On receiving a command code and a logical operation code from CPU 1, ~8~3~
Video CPU 47 sets the command executing (CE) of the bit 7 of SR Register 48 to initiate the execution and processing of the command.
SXY Address Composing Circuit 40 is operated to create a physical address of VRAM 4 from SX Register/Counter 38 and SY Register/Counter 39 respectively holding the source area coordinates under control of Video CPU
47. According to this physical address, a color code data is read out from VRAM 4, which read-out data is in turn set in S Register 34 through Data Line 54, Buffer 53, and VRAM Data Bus 35.
Next, DXY Address Composing Circuit 57 is operated to create a physical address of VRAM 4 from the outputs of DX Register/Counter 58 and DY
Register/Counter 59 respectively holding the destination area coordinates.
According to this physical address, a color code data is read from VRAM 4, which data is in turn set in D Register 52.
On the other hand, a color code data within S Register 34 read out from the source side and a color code data in D Register 52 read oui from the destination side are ORed by AL,U arithmetic and Logic Unit) 51 to produce a superposed color code data.
The newly operated and produced color code data is output on VRAM
Data Line 54 via VRAM Data Bus 35 and Buffer 53, and is then written into VRAM
the register pointer/counter 44 has a count-up function. That is, in setting parameters of the respective registers, after one setting has been completed, it counts up 1. Thus, the registers can be automatically specified successive-ly one by one.
Command Register 46 holds the command information -from CPU 1, and Video CPU 47 processes the display data in accordance with the cornmands from CPU 1. SR Register 48 holds the status from Video CPU 47 to CPU 1. ~Yhen CPU 1 specifies the physical address of VRAM 4 to access the VRAM 4, the VRAM
address is to be held by VRAM Address Register/Counter 37. Color Code Register 33 holds the read data from VRAM 4 as well as the write data to VRA~I 4.
The features of the invention include the below-mentioned component elements:
At first, there are included SX Register/Counter 38 to hold the values on X coordinates existing in a horizontal direction within a source area, SY Register/Counter 39 to hold the values on Y coordinates in a vertical direction and SXY Address Composing Circuit 40 to create the physical address of VRAM in accordance with the respective outputs of SX, SY Register/
Counter 38, 39.
Also, there are provided DX Register/Counter 58 to hold the values on the horizontal X coordinates of a destination area, DY Register/Counter 59 to hold the values on the vertical Y coordinates of the same and DXY
Address Composing circuit 57 to create the physical address of VRAM 4 in accordance with the respective outputs of DX, DY Register/Counters 58, 59.
The above-mentioned SX, SY, DX, DY Register/Counters 38, - ~22~3931 39, 58, 59 have not only a register function but also an up/down counter function, respectively.
Further, VRAM Address ~U9 36,which i8 contained within the display control circuit 3, ls connected through Buffer 55 to Address Line 56 of VRAM 4. VRAM Da-ta Bus 35, which is also contained in the display control circuit 3, is connected through Buffer 53 to VRAM Data Line 54.
NX Register 61 holds the transfer data number in a hori-zontal direction (that is, a direction of the X coordinates), while NY Register 63 holds the transfer data number in a vertical direction (that iSJ a direction of the Y coordinates).
There is provided a horizontal direction flag 60 which points to a positive direction (or, right direction) when it is "O"
and points to a negative direction (or, left direction) for "O". A vertical direction flag 62 indicates a positive direction (or, downward directlon) when it is "O", and a negative direction (or, upward direction) for "1". S Register 34 holds the read data from the source area, and D Register 52 holds the read data from the clestination area. ALU (ari-thmetic and logic unit) 51 performs logical operations such as IMP, AND, 0~, EOR, NOT operatlons of the outputs of S
Register 34, Color Code Register 33 and D Register 52 in accordance with the control from Video CPU 47.
~L22893~
IL Register 70 is used to previously set the number of columns, lines, or rows for IL interruptions, while Comparator 71 is dedicated to detecting the correspondence of the number of the columns, lines, or rows set by IL
Register 70.
Referring now to Fig. 10, Source Data Bit Selector 101 selects higher 4 bits or lower 4 bits from the source data and then uses the selected 4 bits to form higher 4 bits or lower 4 bits. Byte Data Selector 102 selects the data which has passed through Source Data Bit Selector 101 or the source data from S Reg:Lster 34.
Transparence Detection Circui-t 104 serves to detect a color code (that is, transparency) for a portion of the source area in which no object exists.
Parallel Bit Selector 103 causes omission of logical operations of some of the color codes within the destina-tion area which corresponds to the color code within the source area, provided that the very source area color code happens to be transparent.
Referring to Fig. 11, Expansion Memory 111 is used as "kanji" ROM(Battern Memory) or a buffer area.
Referring to Fig. 12, Slot Switch 121 is dedicated to switching a video request or a process request.
1~:28~3~
ARGR Switch 123 is used to switch a request to a video request or a process request in accordance with the respective bits of an argument register.
The foregoing elements are the characteristic ones of the present invention. Although there exlst other elements than the foregoings in the display control circuit 3, an explanation is omitted here regarding such elements as not necessary in describing the operation of the invention.
Next, we will describe the operation of the above-mentioned embodiment.
First, the operation of the display control circuit 3 is described, by way of example, in connection with the bloclc data transfer/superposition based on X, Y coordinates.
It is necessary that CPU l has previously set informa-tion necessary for the logical operation and block data transf`er in the respective registers of the display control circuit 3. When accessing the respective reglsters shown in Figs. 5 and 6, CPU l sets the register number of a register to be accessed in a register pointer/cdunter 44 and there-after performs its read/write operation.
When the source area color code data within VRAM 4 and the destination area color code area are ORed and super-posed on each other, "100100107' is to be set in Register #146 33~
(Command Register). Its higher 4 bits "1001" represents a command code shown in Figure 7 block data transfer from VRAM 4 to VR~I 4 with a logical opera-tion), while its lower 4 bits "0010" expresses an OR shown in Figure 8.
Also, when such block data as shown in Figure 3 is to be processed, it is necessary to set up the following parameters: The start coordinates (SX, SY) of the source area are set in SX Register/Counter 38 and SY Register/
Counter 39, respectively. SX Register/Counter 38 is composed of SXL (Register #132) and SXH (Register #133), while SY Register/Counter 39 is composed of SYL (Register #134) and SYH (Register #135). Therefore, CPU 1 sets a 4-byte parameter on the transfer starting point or the starting coordinates (SX, SY).
By the way, Figure 5 illustrates the contents of Registers #132-142, and Figure 6 illustrates the contents of Registers #143 - 146 as well as the contents of Registers ~t2, tt8.
Then, the destination area start coordinates (DX, DY) are set in DX Register/Counter 58 and DY Register/Counter 59. DX Register/Counter 58 is composed of DXL (Register ~tl36) and DXI-I (Register #137), while DY Register/
Counter 59 is composed of DYL, (Register #138) and DYI-I (Register #139).
Next, the number NX of data to be transferred to a horizontal direc-tion (a direction of the X coordinates) is set in NX Register 61 and the num-ber NY of data to be transferred to a vertical direction (a direction of the Y coordinates) is set in NY Register 63. NX Register 61 is composed of NXL
(Register #140) and NXH (Register #141), while NY Register 63 is composed of NYL (Register #142) and NYH (Register ~tl43).
Since the block data to be transferred to both of the X, Y direc-tions when viewed from the start coordinates (SX,SY) are in a positive direc-tion, "O" is set in both of Direction Flag 60 and Direction Flag 62. Direction ,. .~
~22~g3~_ Flag 60 corresponds to the bit 3 of Argument Register ARGR register #145~, and Direction Flag 62 to the bit 2 of Argument Register ARGR (Register #145).
When all of the foregoing settings have been effected J it is considered that the setting of parameters necessary for transfer of the block data has been completed. These parameter settings are to be performed successively from Register #132 to Register #145. First, "32" is set in Register Pointer/Counter 44. Then, it is necessary only to write the parameters successively so that the associated registers can be set up sequentially. After then, Register Pointer/Counter 44 is caused to point to Register #146 and is in a position to wait for setting o:E a command code.
Figure 7 is a table to illustrate command codes.
In this figure, "VDC" stands for the display control circuit 3.
Figure 8 is a table to illustrate logical operations. In this fig-ure, SC represents a source color code and DC stands for a destination color code.
CPU 1 creates command codes such as "10010010" in accordance with the above-mentioned command codes and logical operation codes and then sets them in Command register 46 register #146).
The higher 4 bits of the above-mentioned command code express an instruction to transfer a block data within VRA~I 4 provided that the source area and the destination area are both present within the VRAM 4. On the other hand, the lower 4 bits of the above example represent a logical operation code, that is, "0010" means tha-t the OR of the source color code data and the destination color code data before transferred is to be written into the destination.
On receiving a command code and a logical operation code from CPU 1, ~8~3~
Video CPU 47 sets the command executing (CE) of the bit 7 of SR Register 48 to initiate the execution and processing of the command.
SXY Address Composing Circuit 40 is operated to create a physical address of VRAM 4 from SX Register/Counter 38 and SY Register/Counter 39 respectively holding the source area coordinates under control of Video CPU
47. According to this physical address, a color code data is read out from VRAM 4, which read-out data is in turn set in S Register 34 through Data Line 54, Buffer 53, and VRAM Data Bus 35.
Next, DXY Address Composing Circuit 57 is operated to create a physical address of VRAM 4 from the outputs of DX Register/Counter 58 and DY
Register/Counter 59 respectively holding the destination area coordinates.
According to this physical address, a color code data is read from VRAM 4, which data is in turn set in D Register 52.
On the other hand, a color code data within S Register 34 read out from the source side and a color code data in D Register 52 read oui from the destination side are ORed by AL,U arithmetic and Logic Unit) 51 to produce a superposed color code data.
The newly operated and produced color code data is output on VRAM
Data Line 54 via VRAM Data Bus 35 and Buffer 53, and is then written into VRAM
4 in accordance with a physical address on the destination side produced by DXY Address Composing Circuit 57.
The above operations complete the logical operation and data trans-fer of a color code data of 1 dot.
In the same manner as with the block data transfer based on X, Y
coordinates, logical operations (OR) and block data transfer operations are performed on the sum (NX x NY) of X-direction NX color code data and Y-3~
direction NY color code data.
When NX Register 61 coincides with NX Counter 64 and NY Register 63 coincides with NY Counter 65, then Video CPU 47 decides that the logical opera-tion (OR)/block data transfer has been completed, clears the command executing ICE) bit within SR Register 48, and informs CPU 1 of the end of the command.
In the above discussion, the logical operation (OR)/block data transfer based on the X, Y coordinates only within VRAM 4 has been explained.
However, it is similarly possible to perform other logical operation/block data transfer processings in accordance with commands which specify other com-binations. Such cases will be discussed from now on.
l Logical operation/block data transfer from CPU 1 to VRA~I 4 (Command code CM 3~0 "1011"):
In this case, since the source is CPU 1, SX Register/Counter 38, SY Register/Counter 39 and S Register 34 are not used, but instead Color Code Register 33 is used.
Specifically, when CPU I sets a transEer data in Color Code Register 33 and Video CPU 47 writes the trans:Eer data of Color Code Register 33 into VRAM 4 according to DX Register/Counter 58 and DY Register/Counter 59, the transfer ready (TR) bit of SR Register 48 is set to inform CPU 1 that one data transfer is completed and that Color Code Register 33 is now ready to receive a next data.
Af-ter confirming that this TR bit is "1", CPU 1 sets a next trans-fer data in Color Code Register 33. This resets the TR bit and returns it to its original status. Other operations are the same as with the above-mentioned block data transfer within VRAM 4.
~2) Logical operation/block data transfer from VRAM 4 to CPU 1 command code CM 3~0 "1011"):
~228~31 In this instance, since the destination is CPU 1, a color code data from CPU 1 that is, a fixed data) is set into D Register 52 via Color Code : Register 33. The color code data, after operated, is set in Color Code Regis-ter 33 and is then read by CPU 1.
Vi.deo CPU 47 reads out a transfer data from VRAM 4 in accordance with SX Register/Counter 38 and SY Register/Counter 39 and sets the read-out transfer data in Color Code Register 33, and at the same time sets the TP~
bit of SR Register 48 for "1". CPU 1 checks this TR bit, and, if it is "1", then CPU 1 reads out the transfer data from Color Code Register 33. As a result of this, the TR bit is reset and returns to its initial status. Other operations are performed in the same way as in the above-mentioned data trans-fer within VRAM 4.
(3) Logical operation/block data transfer from a single register (Color Code Register 33) within the display control circuit 3 to VR~M 4 (Command Code CM3~0 "1010"):
[n this ca.se, the data written into Color Code Register 33 is trans-:Eerred to the destination area of VRAM 4. This is an effective way in writing the same data. The procedure of this operation is the same as in the above-mentioned block data transfer from CPU 1 to VRAM 4. However, in this instance, CPU l is required to write the data into Color Code Register 33 only once, and the data is to be transferred under control of Video CPU 47.
(4) Various logical operations including not only the OR but also the AND, XOR, complement or tlle like of the source area color code data and the destination area color code data can also be performed at high speeds by ALlJ 51 (in accordance with the instructions from Command Register 46 L 0 2~0).
~L~2~3~
The operations concerning the above-mentioned articles (2) and (3 are performed by CPU 1 in cooperation with Display Control Circuit 3, which means both of them must wait while their partners are in execution mutually.
Such mutual execution wait is controlled by setting and resetting the TR bit of SR Register 48.
Conditions of the above mentioned execution wait are different between in the display period and in the retrace period. Namely, during the return line period, since all of the memory accesses can be used for command processing, the command processing can be executed at high speeds so that the waiting of CPU 1 is eliminated. In particular, a vertical return line period is longer than a horizontal retrace period and thus it takes longer time to process commands in the vertical retrace period than in the horizontal retrace line period. Accordingly, if it is possible to employ such a command process-ing system as can avoid the waiting of CPU 1 in the vertical period, then the per:Eormance of the display control Ullit can be enhanced substantially. To this end, when the vertical retrace period comes near, an interrupt (or, IL inter-rupt) is caused to occur to inEorm CPU 1 of the effect.
Such IL interrupt is enabled by previously having set the value of Vertical Counter (Line, Row) 32 in IL Register 70 shown in Figure 4 (an inter-rupt line register, #8 Register shown in Figure 6).
The value to be set for this purpose may be the start line number of the vertical re-trace, or, in case when the overhead time for interrupt pro-cessing is long, such a value may be set as causes an interrupt to take place earlier by such long time. In either event, it is possible to improve the efficiency of the display control unit.
During the vertical retrace, SR Register 48 shown in Figure 4 (a 3~
status register, or ~2 Register shown in Figure 6) is sometimes checked for its VR bit that is, the output of the VR status signal produced by decoding the output of Counter 32 is read out) to decide whether a processing in the very vertical retrace is to be continued or not.
The above-mentioned VR bit is produced by decoding the output of Counter 32 such that it becomes "O" a predetermined time before the termina-tion of the vertical retrace line period. It is necessary to set up the pre-determined time duration even when a processing happens to be longest during the vertical retrace so as to prevent such longest processing from being carried over into the display period.
Similarly as with the above-mentioned IL interrupt occurred when the vertical retrace approaches, the status of the horizontal retrace can also be shifted forwardly in time to increase its processing efficiency.
When CPU 1 perEorms a processing aiming at the horizontal retrace, it is necessary during such processing to check SR Register ~8 for its }IR bit.
In this case, a timing to generate the SIR bit can also be staggered in the following mantler to enhance the processing efficiency. That is, in the repetitive processings during the horizontal retrace, the leading edge of the timing may be shifted beEore a minimum time duration required to issue a VR~M
access after detection of the IIR bit, and the trailing edge thereof may be staggered before more than -the maximum time duration.
figure 9 illustrates the timing mentioned above.
The predetermined time duration from the beginning of the vertical or horizontal retrace necessary to cause an in-terrupt to CPU 1 may be changed depending upon the time periods from the generation of an interrupt signal 3~
to CPU 1 to the initiation of the interrupt processing. Also, this predetermined time duration must be changed in accordance with the length of the execution time of programs.
Also, during the vertical and horizontal retrace, the process-ing mode of CPU 1 is changed by causing CPU 1 to omit the confirmation as to whether Video CPU 47 has completed its previous processing, and at the same time a status signal to indicate the then processing is present with-in the retrace period is monitored so as to continue to change the process-ing mode of CPU l. The status signal has been previously extinguished within a predetermined time after the termination of the retrace. Then, the processing mode of CPU 1 is returned to its original way, in which CPU 1 confirms whether Video CPU 47 has completed its previous processing.
Figure 10 illustrates a block diagram of another embodiment oE the invention, showing an example in which an updating processing of color specification in the display data can be performed at increased speeds.
The foregoing cliscussion is concerned with the memory contents of one memory address and is limited to the 1 dot display system. However, in general, a memory interface consists of a byte (8 bits) or a word (16 32 bits) and thus contains information on display of a plurality of dots.
In this case, when the dots are to be processed one by one, the remaining bits must be masked.
~228~3~
Next, we will describe the operation to be performed when a byte interface has 4-bit color information (2 dots/byte).
As it contains the information about 2 dots/byte, the source data and destination data are respectively selected for each bit.
Source Data Selector 101 selects higher 4 bits when 0 bit of SXY is "0", and lower 4 bits when this 0 bit is "1".
The data is then transferred via Byte Data Selector 102 to FLU 51. In ALU 51, a logical operation of the data and the value of D Register 52 is executed for each bit. After then, Parallel Bit Selector 103 outputs as VRAM data either 4 bits (that is, the upper 4 bits for "0", the lower 4 bits for "1") to be specified in accordance wi-th the value of the bit 0 of DXY.
If the value of the source data bus is "0" and L 0 3 = 1, Transparency Detection Circuit 104 decides the source data as transparent and thus Parallel Bit Selector 103 allows the value of D Register 52 as it is to pass through.
In this manner, the bit select/mask function and trans-parency processing can be realized.
In other words, the color code data within the source area and the color code data within the destination area are logically operated, while a portion belonging to the source ~L2~:~3931 area and having no object existing therein, more particularly the color code (transparent color) of such portion is detected by Transparency Detection Circuit 104 and the logical opera-tion of the transparent portion is omitted, so that only the form stored in the source area and having a solid body can be transferred at high speeds.
The above-mentioned operations can be realized similarly even if the number of the color information bits or the number of bits / word may be varied.
The above discussion rela-tes to a bit-by-bit processing.
According to cases, however, it may be necessary to process data in bytes for purposes of higher speeds. In this instance, the command code "llll 1100" is used. Source Data Bit Selector lOl is not used for this purpose, but the value of S Register 3~ is directly gulded to ALU 51 by Byte Data Selector 102 (CM2 = 1), and then the output of ALU 51 is forcibly guided to VRAM Data Bus 35, so that a higher speed processing can be executed.
In other words, a part of the display data read out to the destination register is modified and the modified display data is written into VRAM 4, so that it i5 possible to speed up the updating processing of the color specification in the display data.
~L228931 Source data specified by a source address is divided into a plurality of portions and one of the data portions is then selected, while destination data specified by a destination address is also divided into a plurality of data portions and one of the data portions is selected. After logical operations are performed on the thus selected data portions, the logical operakion result or the destination data is selected for each of the portions of the respective data. us a result of this, it is possible to perform logical operations only on a desired dot on the display screen.
Fig. 11 is a block diagram of another embodiment of the invention, illustrating an example using an expansion memory as a "kanJi"(chinese-character) accomodation or as a buffer area.
In Fig. 11, Expansion Memory 111 is extended in parallel with VRAM 4. For example, when this expansion memory 111 is extended in parallel with VRAM 4 as a chinese-character pattern ROM, chinese characters ("kanji") can be accommodated.
This is because a high-speed display can be realized by trans-ferring a chinese-character pattern to VRAM 4 by means of area movement. Also, it is convenient since there is no need to load any external pattern data for this purpose. Further, since the read speed of the chlnese-character pattern ROM, or ~2~893~
the cycle time of the area movement in this case may be slower than the display memory access, low-speed and large-capacity memory elements can be used. To achieve this, an address register may be located wlthin the expansion memory and, at the time when the previous access has been completed, an address may be updated to initiate the next reading.
Also, when an RAM is extended as an expansion memory, this can be used as a work memory of VRAM 4 to expand the address space up to the same capacity as that of VRAM 4.
Specifically, bits MXC, MXD and MXS of ARGR are defined.
MXC, which serves to switch and control the VRAM access from CPU 1, makes it possible to directly read and write an expan-sion memory from CPU 1. MXD specifies the destination area to the expansion memory and makes it possible for the expan-sion memory to be read and wrltten as the data memory. MXS
specifies the source area to the expansion memory and permits reading of a fixed pattern or reading from a buffer memory.
Fig. 12 is a circuit diagram of the main portions of the embodiment shown in Fig. 11.
Next, the operation of the embodiment in Fig. 11 will be-described with reference to Fig. 12.
Access requests for a memory are normally classified into two main categories; namely, video requests (VRQ) and ~2893~
process requests (PRQ). The video requests VRQ are requests for reading of data for CRT display and are issued based on the counts of Counter 32. The process requests PRQ are VRAM
accesses that are issued by Video CPU. This issue results from the controls of CPU such as setting of parameters from CPU 1, starting of commands, VRAM access and the like.
The video requests VRQ and process requests PRQ are con-trolled by timing control signals, and are respectively permitted by the allocated time slots. These operations are processed by Slot Switch 121 shown in Fig. 12. That is, at a timing when the video request VRQ is issued,Slot Switch 121 is always connected to the video request VRQ side, and in other cases it is connected to the process request PRQ side.
Thus, PRQ is permitted only when Slot Switch 121 is connected to the PRQ side.
Next, we will describe the operation and function of the bits MXC, MXD, MXS of ARGR.
The contents of the process request PRQ are classified into CRQ to be issued when CPU 1 accesses VRAM 4 directly, DRQ issued when the destination data is accessed while Video CPU 122 is executing a command, and SRQ issued when the source data is accessed. These requests are normally connected to the process request PRQ side by ARGR Switch 123.
~2~3931 This ARGR Switch 123 is adapted to connect the requests, CRQ, DRQ and SRQ to an XRQ side in accordance with each of the bits MXC, MXD and MXS. This XRQ is a memory request (MX
request) to the expansion memory, and when the XRQ appears the expansion memory is to be accessed instead of VRAM 4.
Thus, by distributing each of the process request or PRQ
requests independently to the VRAM 4 expansion memory in this way, the expansion memory can be used as a buffer memory or a pattern memory. When the expansion memory is specified by MXD and VRAM 4 by MXS to specify the area movement, then it is possible to save the da-ta in an area where VRA~ 4 is con-tained. On the other hand, when VRAM 4 and the expansion memory are specified by MXD and MXS respectively, then it is possible to return the saved data to its original state, or to move a fixed pattern (or, a chinese-character pattern) to VRAM 4 for display.
The foregoing description has been made on condition that a color code or color data is to be handled, but this can also apply to a monochrome system. In that case, the color data may be replaced by the byte da-ta.
The present invention is useful in performing display control of not only the color CRT but also othe. display units such as a monochrome CRT, LCD, plasma, and EL.
;
- 2~ -~L2~:8931 As can be clearly understood from the foregoing des-cription, the present invention provides several effects:
namely, when reducing the execution time for display ope-ration by reading out the source area data from a memory unit and then writing the read-out source area data sequen-tially into the destination area, the command processing speed can be increased during a vertical or horizontal retrace line period; it is possible to increase the speed of an update processing on color specification in display data, and at the same time only a desired dot on the display screen can be logically operated;.and, it is possible to transfer a form or an object existing within the source area and having a solid body at high speeds, and an expansion memory can be used as a "Icanji" (chinese-character) ROM (or, : a pattern memory) or a buffer area.
The above operations complete the logical operation and data trans-fer of a color code data of 1 dot.
In the same manner as with the block data transfer based on X, Y
coordinates, logical operations (OR) and block data transfer operations are performed on the sum (NX x NY) of X-direction NX color code data and Y-3~
direction NY color code data.
When NX Register 61 coincides with NX Counter 64 and NY Register 63 coincides with NY Counter 65, then Video CPU 47 decides that the logical opera-tion (OR)/block data transfer has been completed, clears the command executing ICE) bit within SR Register 48, and informs CPU 1 of the end of the command.
In the above discussion, the logical operation (OR)/block data transfer based on the X, Y coordinates only within VRAM 4 has been explained.
However, it is similarly possible to perform other logical operation/block data transfer processings in accordance with commands which specify other com-binations. Such cases will be discussed from now on.
l Logical operation/block data transfer from CPU 1 to VRA~I 4 (Command code CM 3~0 "1011"):
In this case, since the source is CPU 1, SX Register/Counter 38, SY Register/Counter 39 and S Register 34 are not used, but instead Color Code Register 33 is used.
Specifically, when CPU I sets a transEer data in Color Code Register 33 and Video CPU 47 writes the trans:Eer data of Color Code Register 33 into VRAM 4 according to DX Register/Counter 58 and DY Register/Counter 59, the transfer ready (TR) bit of SR Register 48 is set to inform CPU 1 that one data transfer is completed and that Color Code Register 33 is now ready to receive a next data.
Af-ter confirming that this TR bit is "1", CPU 1 sets a next trans-fer data in Color Code Register 33. This resets the TR bit and returns it to its original status. Other operations are the same as with the above-mentioned block data transfer within VRAM 4.
~2) Logical operation/block data transfer from VRAM 4 to CPU 1 command code CM 3~0 "1011"):
~228~31 In this instance, since the destination is CPU 1, a color code data from CPU 1 that is, a fixed data) is set into D Register 52 via Color Code : Register 33. The color code data, after operated, is set in Color Code Regis-ter 33 and is then read by CPU 1.
Vi.deo CPU 47 reads out a transfer data from VRAM 4 in accordance with SX Register/Counter 38 and SY Register/Counter 39 and sets the read-out transfer data in Color Code Register 33, and at the same time sets the TP~
bit of SR Register 48 for "1". CPU 1 checks this TR bit, and, if it is "1", then CPU 1 reads out the transfer data from Color Code Register 33. As a result of this, the TR bit is reset and returns to its initial status. Other operations are performed in the same way as in the above-mentioned data trans-fer within VRAM 4.
(3) Logical operation/block data transfer from a single register (Color Code Register 33) within the display control circuit 3 to VR~M 4 (Command Code CM3~0 "1010"):
[n this ca.se, the data written into Color Code Register 33 is trans-:Eerred to the destination area of VRAM 4. This is an effective way in writing the same data. The procedure of this operation is the same as in the above-mentioned block data transfer from CPU 1 to VRAM 4. However, in this instance, CPU l is required to write the data into Color Code Register 33 only once, and the data is to be transferred under control of Video CPU 47.
(4) Various logical operations including not only the OR but also the AND, XOR, complement or tlle like of the source area color code data and the destination area color code data can also be performed at high speeds by ALlJ 51 (in accordance with the instructions from Command Register 46 L 0 2~0).
~L~2~3~
The operations concerning the above-mentioned articles (2) and (3 are performed by CPU 1 in cooperation with Display Control Circuit 3, which means both of them must wait while their partners are in execution mutually.
Such mutual execution wait is controlled by setting and resetting the TR bit of SR Register 48.
Conditions of the above mentioned execution wait are different between in the display period and in the retrace period. Namely, during the return line period, since all of the memory accesses can be used for command processing, the command processing can be executed at high speeds so that the waiting of CPU 1 is eliminated. In particular, a vertical return line period is longer than a horizontal retrace period and thus it takes longer time to process commands in the vertical retrace period than in the horizontal retrace line period. Accordingly, if it is possible to employ such a command process-ing system as can avoid the waiting of CPU 1 in the vertical period, then the per:Eormance of the display control Ullit can be enhanced substantially. To this end, when the vertical retrace period comes near, an interrupt (or, IL inter-rupt) is caused to occur to inEorm CPU 1 of the effect.
Such IL interrupt is enabled by previously having set the value of Vertical Counter (Line, Row) 32 in IL Register 70 shown in Figure 4 (an inter-rupt line register, #8 Register shown in Figure 6).
The value to be set for this purpose may be the start line number of the vertical re-trace, or, in case when the overhead time for interrupt pro-cessing is long, such a value may be set as causes an interrupt to take place earlier by such long time. In either event, it is possible to improve the efficiency of the display control unit.
During the vertical retrace, SR Register 48 shown in Figure 4 (a 3~
status register, or ~2 Register shown in Figure 6) is sometimes checked for its VR bit that is, the output of the VR status signal produced by decoding the output of Counter 32 is read out) to decide whether a processing in the very vertical retrace is to be continued or not.
The above-mentioned VR bit is produced by decoding the output of Counter 32 such that it becomes "O" a predetermined time before the termina-tion of the vertical retrace line period. It is necessary to set up the pre-determined time duration even when a processing happens to be longest during the vertical retrace so as to prevent such longest processing from being carried over into the display period.
Similarly as with the above-mentioned IL interrupt occurred when the vertical retrace approaches, the status of the horizontal retrace can also be shifted forwardly in time to increase its processing efficiency.
When CPU 1 perEorms a processing aiming at the horizontal retrace, it is necessary during such processing to check SR Register ~8 for its }IR bit.
In this case, a timing to generate the SIR bit can also be staggered in the following mantler to enhance the processing efficiency. That is, in the repetitive processings during the horizontal retrace, the leading edge of the timing may be shifted beEore a minimum time duration required to issue a VR~M
access after detection of the IIR bit, and the trailing edge thereof may be staggered before more than -the maximum time duration.
figure 9 illustrates the timing mentioned above.
The predetermined time duration from the beginning of the vertical or horizontal retrace necessary to cause an in-terrupt to CPU 1 may be changed depending upon the time periods from the generation of an interrupt signal 3~
to CPU 1 to the initiation of the interrupt processing. Also, this predetermined time duration must be changed in accordance with the length of the execution time of programs.
Also, during the vertical and horizontal retrace, the process-ing mode of CPU 1 is changed by causing CPU 1 to omit the confirmation as to whether Video CPU 47 has completed its previous processing, and at the same time a status signal to indicate the then processing is present with-in the retrace period is monitored so as to continue to change the process-ing mode of CPU l. The status signal has been previously extinguished within a predetermined time after the termination of the retrace. Then, the processing mode of CPU 1 is returned to its original way, in which CPU 1 confirms whether Video CPU 47 has completed its previous processing.
Figure 10 illustrates a block diagram of another embodiment oE the invention, showing an example in which an updating processing of color specification in the display data can be performed at increased speeds.
The foregoing cliscussion is concerned with the memory contents of one memory address and is limited to the 1 dot display system. However, in general, a memory interface consists of a byte (8 bits) or a word (16 32 bits) and thus contains information on display of a plurality of dots.
In this case, when the dots are to be processed one by one, the remaining bits must be masked.
~228~3~
Next, we will describe the operation to be performed when a byte interface has 4-bit color information (2 dots/byte).
As it contains the information about 2 dots/byte, the source data and destination data are respectively selected for each bit.
Source Data Selector 101 selects higher 4 bits when 0 bit of SXY is "0", and lower 4 bits when this 0 bit is "1".
The data is then transferred via Byte Data Selector 102 to FLU 51. In ALU 51, a logical operation of the data and the value of D Register 52 is executed for each bit. After then, Parallel Bit Selector 103 outputs as VRAM data either 4 bits (that is, the upper 4 bits for "0", the lower 4 bits for "1") to be specified in accordance wi-th the value of the bit 0 of DXY.
If the value of the source data bus is "0" and L 0 3 = 1, Transparency Detection Circuit 104 decides the source data as transparent and thus Parallel Bit Selector 103 allows the value of D Register 52 as it is to pass through.
In this manner, the bit select/mask function and trans-parency processing can be realized.
In other words, the color code data within the source area and the color code data within the destination area are logically operated, while a portion belonging to the source ~L2~:~3931 area and having no object existing therein, more particularly the color code (transparent color) of such portion is detected by Transparency Detection Circuit 104 and the logical opera-tion of the transparent portion is omitted, so that only the form stored in the source area and having a solid body can be transferred at high speeds.
The above-mentioned operations can be realized similarly even if the number of the color information bits or the number of bits / word may be varied.
The above discussion rela-tes to a bit-by-bit processing.
According to cases, however, it may be necessary to process data in bytes for purposes of higher speeds. In this instance, the command code "llll 1100" is used. Source Data Bit Selector lOl is not used for this purpose, but the value of S Register 3~ is directly gulded to ALU 51 by Byte Data Selector 102 (CM2 = 1), and then the output of ALU 51 is forcibly guided to VRAM Data Bus 35, so that a higher speed processing can be executed.
In other words, a part of the display data read out to the destination register is modified and the modified display data is written into VRAM 4, so that it i5 possible to speed up the updating processing of the color specification in the display data.
~L228931 Source data specified by a source address is divided into a plurality of portions and one of the data portions is then selected, while destination data specified by a destination address is also divided into a plurality of data portions and one of the data portions is selected. After logical operations are performed on the thus selected data portions, the logical operakion result or the destination data is selected for each of the portions of the respective data. us a result of this, it is possible to perform logical operations only on a desired dot on the display screen.
Fig. 11 is a block diagram of another embodiment of the invention, illustrating an example using an expansion memory as a "kanJi"(chinese-character) accomodation or as a buffer area.
In Fig. 11, Expansion Memory 111 is extended in parallel with VRAM 4. For example, when this expansion memory 111 is extended in parallel with VRAM 4 as a chinese-character pattern ROM, chinese characters ("kanji") can be accommodated.
This is because a high-speed display can be realized by trans-ferring a chinese-character pattern to VRAM 4 by means of area movement. Also, it is convenient since there is no need to load any external pattern data for this purpose. Further, since the read speed of the chlnese-character pattern ROM, or ~2~893~
the cycle time of the area movement in this case may be slower than the display memory access, low-speed and large-capacity memory elements can be used. To achieve this, an address register may be located wlthin the expansion memory and, at the time when the previous access has been completed, an address may be updated to initiate the next reading.
Also, when an RAM is extended as an expansion memory, this can be used as a work memory of VRAM 4 to expand the address space up to the same capacity as that of VRAM 4.
Specifically, bits MXC, MXD and MXS of ARGR are defined.
MXC, which serves to switch and control the VRAM access from CPU 1, makes it possible to directly read and write an expan-sion memory from CPU 1. MXD specifies the destination area to the expansion memory and makes it possible for the expan-sion memory to be read and wrltten as the data memory. MXS
specifies the source area to the expansion memory and permits reading of a fixed pattern or reading from a buffer memory.
Fig. 12 is a circuit diagram of the main portions of the embodiment shown in Fig. 11.
Next, the operation of the embodiment in Fig. 11 will be-described with reference to Fig. 12.
Access requests for a memory are normally classified into two main categories; namely, video requests (VRQ) and ~2893~
process requests (PRQ). The video requests VRQ are requests for reading of data for CRT display and are issued based on the counts of Counter 32. The process requests PRQ are VRAM
accesses that are issued by Video CPU. This issue results from the controls of CPU such as setting of parameters from CPU 1, starting of commands, VRAM access and the like.
The video requests VRQ and process requests PRQ are con-trolled by timing control signals, and are respectively permitted by the allocated time slots. These operations are processed by Slot Switch 121 shown in Fig. 12. That is, at a timing when the video request VRQ is issued,Slot Switch 121 is always connected to the video request VRQ side, and in other cases it is connected to the process request PRQ side.
Thus, PRQ is permitted only when Slot Switch 121 is connected to the PRQ side.
Next, we will describe the operation and function of the bits MXC, MXD, MXS of ARGR.
The contents of the process request PRQ are classified into CRQ to be issued when CPU 1 accesses VRAM 4 directly, DRQ issued when the destination data is accessed while Video CPU 122 is executing a command, and SRQ issued when the source data is accessed. These requests are normally connected to the process request PRQ side by ARGR Switch 123.
~2~3931 This ARGR Switch 123 is adapted to connect the requests, CRQ, DRQ and SRQ to an XRQ side in accordance with each of the bits MXC, MXD and MXS. This XRQ is a memory request (MX
request) to the expansion memory, and when the XRQ appears the expansion memory is to be accessed instead of VRAM 4.
Thus, by distributing each of the process request or PRQ
requests independently to the VRAM 4 expansion memory in this way, the expansion memory can be used as a buffer memory or a pattern memory. When the expansion memory is specified by MXD and VRAM 4 by MXS to specify the area movement, then it is possible to save the da-ta in an area where VRA~ 4 is con-tained. On the other hand, when VRAM 4 and the expansion memory are specified by MXD and MXS respectively, then it is possible to return the saved data to its original state, or to move a fixed pattern (or, a chinese-character pattern) to VRAM 4 for display.
The foregoing description has been made on condition that a color code or color data is to be handled, but this can also apply to a monochrome system. In that case, the color data may be replaced by the byte da-ta.
The present invention is useful in performing display control of not only the color CRT but also othe. display units such as a monochrome CRT, LCD, plasma, and EL.
;
- 2~ -~L2~:8931 As can be clearly understood from the foregoing des-cription, the present invention provides several effects:
namely, when reducing the execution time for display ope-ration by reading out the source area data from a memory unit and then writing the read-out source area data sequen-tially into the destination area, the command processing speed can be increased during a vertical or horizontal retrace line period; it is possible to increase the speed of an update processing on color specification in display data, and at the same time only a desired dot on the display screen can be logically operated;.and, it is possible to transfer a form or an object existing within the source area and having a solid body at high speeds, and an expansion memory can be used as a "Icanji" (chinese-character) ROM (or, : a pattern memory) or a buffer area.
Claims (8)
PROPERTY OR PRIVILEGE IS CLAIMED ARE DEFINED AS FOLLOWS:
1. A display control unit for providing screen image information and a control signal to a display unit, said display control unit comprising a destination register for reading and storing display data at a destination address to be written by a central processing unit (CPU), and a write register for holding data to be written, wherein a portion of said display data is combined with a portion of said data to be written to modify said display data, and said modified display data is written into said destination address so as to be able to change a portion of a word in a display memory.
2. The display control unit as claimed in claim 1, char-acterized in that said modify function is composed of data for each 1-dot information when a command is executed.
3. The display control unit as claimed in claim 1, char-acterized in that said modify function is composed of a parallel bit selector.
4. A display control unit for providing screen image information and a control signal to a display unit, said display control unit comprising: means for specifying a transfer start point of a source area; means for specifying a transfer start point of a destination area; means for holding the amount of trans-fer data in a horizontal direction; means for holding the amount of transfer data in a vertical direction; means for holding the mov-ing directions of respective horizontal and vertical transfer points; first select means for dividing source data specified by a source address into a plurality of data sections and selecting one of said data sections; second select means for dividing des-tination data specified by a destination address into a plurality of data sections and selecting one of said data sections; means for performing logical operations on said data sections selected by said first and second select means; and third select means for selecting said logical operation result or destination data for each of said sections of said data, wherein data in said source area specified by said means is read out from a memory unit and said read-out data is sequentially written into said destination area, thereby performing data transfer between said source and destination areas, and wherein said logical operations are per-formed only on a desired dot on a display screen.
5. A display control unit for providing screen image information and a control signal to a display unit, said display control unit comprising: means for specifying a transfer start point of a source area; means for specifying a transfer start point of a destination area; means for holding the amount of transfer data in a horizontal direction; means for holding the amount of transfer data in a vertical direction; means for hold-ing the moving directions of the respective horizontal and vertical transfer points; transparency detection means for detecting a transparent color that is a color code for a portion of said source area with no object existing therein; and, logical opera-tion means for performing logical operations on color code data within said source area as well as on color code data within said destination area and also omitting logical operations on said transparent color portion, wherein data in said source area spe-cified by said means is read out from a memory unit and said read-out data is sequentially written into said destination area, thereby performing data transfer between said source and destina-tion areas, and wherein a form having a solid body within said source area is transferred at high speeds.
6. A display control system for a CRT display comprising the display control unit of claim 1 in combination with a CPU eon-nected to the display control unit, a main memory for holding programs and data and connected to the CPU, a VRAM for holding display data and connected to the display control unit, and an expansion memory connected to the display control unit parallel with the VRAM wherein the display control unit includes specifi-cation means for specifying either said VRAM or said expansion mem-ory for the command processing memory access of the CPU or the dis-play control unit, whereby said expansion memory is used as a data area of the VRAM to be able to expand the address space of the VRAM equivalently.
7. The display control system of claim 6 wherein the expansion memory is used as a buffer area.
8. The display control system of claim 6 wherein the expansion memory is used as a pattern memory.
Applications Claiming Priority (2)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP28,784/1984 | 1984-02-20 | ||
| JP59028784A JPS60173580A (en) | 1984-02-20 | 1984-02-20 | Display controller |
Publications (1)
| Publication Number | Publication Date |
|---|---|
| CA1228931A true CA1228931A (en) | 1987-11-03 |
Family
ID=12258041
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| CA000474619A Expired CA1228931A (en) | 1984-02-20 | 1985-02-19 | Display control unit |
Country Status (4)
| Country | Link |
|---|---|
| EP (1) | EP0155499B1 (en) |
| JP (1) | JPS60173580A (en) |
| CA (1) | CA1228931A (en) |
| DE (1) | DE3586954T2 (en) |
Families Citing this family (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| GB2246935B (en) * | 1987-09-19 | 1992-05-20 | Hudson Soft Co Ltd | An apparatus for the control of an access to a video memory |
| GB2210239B (en) * | 1987-09-19 | 1992-06-17 | Hudson Soft Co Ltd | An apparatus for controlling the access of a video memory |
| US7827424B2 (en) * | 2004-07-29 | 2010-11-02 | Ati Technologies Ulc | Dynamic clock control circuit and method |
| US7800621B2 (en) | 2005-05-16 | 2010-09-21 | Ati Technologies Inc. | Apparatus and methods for control of a memory controller |
| US8799685B2 (en) | 2010-08-25 | 2014-08-05 | Advanced Micro Devices, Inc. | Circuits and methods for providing adjustable power consumption |
Family Cites Families (9)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| US4197590A (en) * | 1976-01-19 | 1980-04-08 | Nugraphics, Inc. | Method for dynamically viewing image elements stored in a random access memory array |
| JPS5326539A (en) * | 1976-08-25 | 1978-03-11 | Hitachi Ltd | Data exchenge system |
| GB2016757A (en) * | 1978-02-21 | 1979-09-26 | Data General Corp | Display Terminal |
| JPS54139431A (en) * | 1978-04-21 | 1979-10-29 | Hitachi Ltd | Crt display unit |
| JPS54139433A (en) * | 1978-04-21 | 1979-10-29 | Hitachi Ltd | Decision system for end of writing |
| US4240140A (en) * | 1978-12-26 | 1980-12-16 | Honeywell Information Systems Inc. | CRT display terminal priority interrupt apparatus for generating vectored addresses |
| JPS5674738A (en) * | 1979-11-21 | 1981-06-20 | Toshiba Corp | Transfer system of display data |
| US4394645A (en) * | 1981-09-10 | 1983-07-19 | Sensormatic Electronics Corporation | Electrical surveillance apparatus with moveable antenna elements |
| JPS5960480A (en) * | 1982-09-29 | 1984-04-06 | フアナツク株式会社 | Display unit |
-
1984
- 1984-02-20 JP JP59028784A patent/JPS60173580A/en active Pending
-
1985
- 1985-02-13 EP EP85101561A patent/EP0155499B1/en not_active Expired - Lifetime
- 1985-02-13 DE DE19853586954 patent/DE3586954T2/en not_active Expired - Fee Related
- 1985-02-19 CA CA000474619A patent/CA1228931A/en not_active Expired
Also Published As
| Publication number | Publication date |
|---|---|
| DE3586954D1 (en) | 1993-02-18 |
| EP0155499A2 (en) | 1985-09-25 |
| EP0155499B1 (en) | 1993-01-07 |
| DE3586954T2 (en) | 1993-06-03 |
| JPS60173580A (en) | 1985-09-06 |
| EP0155499A3 (en) | 1990-09-12 |
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