JPS60204058A - Small-sized electronic apparatus with data storage function - Google Patents

Abstract

PURPOSE:To edit data quickly and surely by performing the data editing work after all data are inputted. CONSTITUTION:The output of an oscillator 7 is divided by a frequency dividing circuit 8 and is given to a timing signal generating circuit 9, and various fundamental timing signals are given to a ROM10, a RAM11, an instruction decoder 12, and an address control part 13. A microprogram which controls all operations of an apparatus is stored in the ROM10, and an operating part 14 executes operations on a basis of this program, and resultant data are stored in the RAM11, and data from the RAM11 is supplied to a display part 2 through a decoder 15. The data editing work is performed in the operating part 14 after all data are inputted from an input part.

Description

Detailed Description of the Invention (Technical Field of Ja Ming) This invention relates to a small electronic device with a data storage function that presets data such as a telephone number, and reads and displays the data as needed. Regarding equipment.

[Prior art]

2. Description of the Related Art Conventionally, various small electronic devices with a data storage function have been developed that store a plurality of data in a memory and read and display the data arbitrarily as needed.

In this type of device, each time one piece of data is input, editing work is performed such as rearranging the data into, for example, Alphabella) l1l(f) and writing it into memory.

[Problems with conventional technology]

As mentioned above, if you edit each data entry, even if you accidentally press the page update key or make a data entry error, the editing process will be executed immediately.
Therefore, it takes a great deal of effort to restore the original normal editing state.

[Purpose of the invention]

An object of the present invention is to provide a small electronic device with a data storage function that allows data editing work to be easily performed.

[Key points of the invention]

Editing work is not done while data is being input, but is done after all data has been input.

〔Example〕

An embodiment in which the present invention is applied to an electronic wristwatch will be described below with reference to the drawings. FIG. 1 shows the external appearance of an electronic wristwatch. A display section 2 is provided at the center of the top surface of the case 1, and at the bottom are pushbutton switches SA (+ direction search) and 5B (one direction search) for searching data such as phone numbers preset in the memory. is provided.

In addition, on the right side of case 1, there is a switch for setting data such as telephone numbers, etc. It instructs to display the usage rate of the data storage section of the SL1 memory (as described later, one line corresponds to one page) and the maximum number of pages. A switch S□ is provided on the left side, and a switch S7 for specifying a data read mode and a data write mode, and a switch Sa for specifying a clock mode and a memory mode are provided on the left side. Inside the case 1, LSI parts, batteries, etc. are arranged.

FIG. 2 shows the configuration of the display section 2. As shown in FIG. This display unit 2 consists of a liquid crystal display device, and 3 in the figure is 6 digits, each digit is 5X
There is a character display section consisting of a five-dot display, a number display section 4 consisting of mouth-shaped segments, a colon display section 5, and a PM display section 6. The numeric display section 4 displays the time, date, telephone number, etc., and the colon display section 4 blinks at a one-second cycle in clock mode, and also indicates PM.
The display section 6 is turned on during the afternoon time period in the clock mode.

FIG. 3 shows the entire circuit. The reference frequency signal outputted from the oscillator 7 is frequency-divided by a frequency divider circuit 8 and provided to a timing signal generation circuit 9 . The various basic timing signals created there are stored in ROM (read only memory).
10, a RAM (random access memory) 11, an instruction decoder 12, and an address control unit 13, and drive each of them.

The ROM10 stores microprograms that control all operations of this electronic wristwatch, and each microprogram is read out from the area addressed by the address input terminal N13 and executed. The operation code of the microprogram to be read out is input from the terminal 0P to the instruction decoder 12, and the data is input from the terminal DO to the data bus and sent to the RA.
The address input terminal A d (L r ) of the MII is input to the input terminal DI2 of the address control unit 13 and the calculation unit 14, respectively, and the next address data is input to the address control unit 13.

The instruction decoder 12 decodes the operation code and provides a read/write control signal to the RAM II, and also provides a calculation command to the calculation section 14.

Further, the data read from the terminal DO of the RAM 11 is input to the terminals DI8, DI of the arithmetic unit 14, and the arithmetic operation is executed according to the arithmetic instruction at that time.

The calculation result data is then sent to the terminal DI of RAMII and written therein. Further, the calculation unit 14 outputs a signal 32nz every 1/32 seconds and provides it to the address control unit 13. At this time, the time clock from the frequency divider circuit 8 is also input to the address control section 13, and the address control section 13 accordingly writes a program for the time measurement process flow to be executed once every 1/32 second. In response to this, the calculation unit 14 executes calculations to obtain new timing data, and the resulting data is stored in the RAMI.
Store in I.

The data read from RAMII is also input to the decoder 15, converted to display data, and displayed on the display section 2. In addition, the input section 16 is connected to the switch SL% 8Az 8B.
%8t, St, and Ss, and the input data from these switches is sent to the data bus and written to RAM II.

FIG. 4 is a configuration diagram of RAMII. As shown,
It has at least each register of TSDN Ms L% n5NN PSS% FSE and a data storage register for 50 pages numbered 1 to 50. The T and D registers respectively store time data or date data in the clock mode. M register is 1” in clock mode,
This is a flag register that is set to 60" in memory mode. The L register is a flag register that is set to 0" in read mode and '1' in write mode. N register is a register where the maximum page number is set, P register is a register where the number of display pages is set, S register is a register where the top page of the set pages is set. , FSK register is an editing flag register. Data such as a telephone number is set in each of the data storage registers 1 to 50, and each constitutes one page. In this case, each Up to 6 digits of the alphabet (letters) and 12 digits of numbers can be set on the page.

Next, the operation of the above embodiment will be explained with reference to FIGS. 5 to 9. First, the overall operation will be explained with reference to the general flow shown in FIG. 5 and the state transition diagram shown in FIG. 8. When the arithmetic unit 14 gives a signal of 32 Hz to the output seat address control unit 13, the address control unit 13 reads the timekeeping processing program from the ROM10 and causes the arithmetic unit 14 to execute the timekeeping operation (step Gs). TSD
Read the previous time data and date data from each register, add a predetermined value to it, and read the new data again.
Set in each register of D.

When the time counting process is completed, it is determined whether the switch S3 for changing the clock mode or memory mode has been operated or not (step G,); if not, step G6
, and determines whether the data in the N register is 0" or not. If it is 0, the clock mode is being set, so execute the display process in step G and proceed to step 8.
As shown by A in the figure, the data of the T1D register is sent to the display section 2 to display the time and date. Next, it is determined whether or not there is a predetermined interrupt process (step G8), and if there is, it is executed; if not, it waits until the next execution of this general flow.

On the other hand, when it is determined in step G2 that the switch S has been operated, the process advances to step G, and it is determined whether the data in the N register is 1''.

If it is "l", the current mode is memory mode, so proceed to step G4, and set the 7 lag "'0" in the N register to set the clock mode.On the other hand, if it is not 1, the current mode is clock mode, so step G4 .

Then, proceed to step G6 to set the memory mode by setting 1'' in the N register.As shown in FIG. For example, when the switch S3 is operated, the mode is reversed and B's memory mode is displayed, and the telephone number is displayed.Furthermore, if B's telephone number has been displayed until then, A's clock is changed by operating the switch S3. The display switches to the mode display.

If the data in the N register is not 0" in step Go, that is, if the memory mode has been set, the process advances to step G9, where the write mode or read mode is switched. It is determined whether the switch S? has been operated. Then, if it is not operated, jump to step G, 4, it is determined whether the L register is '0'', and '
If it is 0'', the read mode is being set, and step G!
Proceed to s and edit flag register Fs],! It is determined whether or not the force is 0'', and if it is 0, the read process (step G16) is executed, and then the process proceeds to step G. On the other hand, '0''
If not, the process proceeds to step G after executing the write process (step G8.).

On the other hand, if the data in the L register is not 0'' in step GI4, the write mode is being set, and the process immediately proceeds to step G17 to execute it.

Next, the operation of the write process in step G17 will be explained with reference to FIGS. 6 and 9. When writing data, first operate switch sA or switch sB to write data into RAM.
The data storage registers 1 to 5o of II are searched in the plus or minus direction to find an area where no data is written.

At this time, first, in step W1, data "5" of the N register storing the maximum number of pages "50" is stored in the S register.
The data "51" obtained by adding 1 to "0" is set.

Next, RAM II is addressed by the data in the P register in which the current number of displayed pages is set (step W2). Then, it is determined whether or not the key is manually operated (step Ws), and if the switch S or SB is operated, step W is executed.

It is determined whether it is switch S1 or not, and now "
Since the answer is "NO", the process advances to step Wxt, where it is determined whether the switch is the switch SA or not. If switch SA is now being operated, the process advances to step W0 and the P register is incremented by 1.
The register is advanced one page. And step W0
The data “50” in the N register and the data in the P register are compared, and if N≧P, the process returns to step W.
On the other hand, if N(P), the current displayed page has exceeded the 50th page, so the process advances to step W8, the P register is set to "1", the displayed page is returned to the first page, and then step W2 Return to le.

On the other hand, when switch SB is operated, step W1. The process advances to step W0, where the operation of the switch SB is determined, and then, in step Wta, the P register is set to -.
1 and move back one page.

Then, it is determined whether the data in the P register has become "0", that is, whether the 0th page has been reached (step W
1? ), and if it is not the θth page, the process returns to step W. On the other hand, if it is the θth page, the data "50" of the N register is set in the P register, and the 50th page is set. Then, return to step W.

Then, by operating switch SA or SB as described above, +
The data written in the page corresponding to the data in the P register which is set to 1 or -1 is read out from the register and displayed on the display unit 2. When the display section 2 shows that no data (telephone number) is written in the current page of the P register as shown in FIG. 9A by repeatedly operating the switch SA or SB, the switch Stop SA or SB operation. As a result, B in Figure 9
As shown in FIG. 3, first, a cursor is displayed at the first digit of the character display section 3. Therefore, when the switch S1 is operated once, the alphabet rAJ is automatically displayed in the first digit. In this case, steps W, ,W, ,W□,
The operation of switch S□ is determined by each process in Wo, and then step W2. As a result of the process, the letter "A" is displayed, and the process returns to step W.

To input a telephone number using a hand drum, set the last name and abbreviation within six characters in the character display section 3, and set the actual telephone number in the number display section 4. But now, my last name is l'-8UZUK.
Assuming IJ, telephone number is set to [0123-45-7890J, operate eight switches in succession until the first letter rSJ is displayed according to the alphabet. Then, as shown in FIG. 9C, when the letter "S" is displayed, the switch SL is operated to input that letter.

At this time, the operation of the switch SL is determined in step W4, and then in step W1, the data in the S register and the P register are compared. When S>P, the data of the current display page of the P register is set to the S register (step W6), and the data r8J is transferred to the register of the current page (step W,).
, and as shown in FIG. 9D, the display cursor is moved to the next second digit (step W,) and the data "
S'' is stored in the register of the current page (step W9). Then, the process returns to step W3.

The other characters rUZUKIJ are input in exactly the same way, and are performed by operating the switch 81%SL. Then, as shown at I in FIG. 9, the last character rIJ appears and the switch SL
If you memorize it by , as shown in F in Figure 9,
The cursor moves to the first digit on the upper side of the number display section 4, and then the number changes from 0.1 to 0.1 each time switch S is operated.
. . , 9, and when a desired number is displayed, operate switch SL to store it in the register of the current page. G, H, and I in FIG. 9 show this process. When data entry for one page is completed, specify the next page using switch SA or SB.
The next data is stored in the same manner by using the switch 81%SL.

As described above, when the required number of data has been input into the data storage registers 1 to 50 of RAMII, there is no longer any key operation required, so proceed to step W.

From step W,. Proceed to edit flag F, 11. It is determined whether or not is 1". Since the write process is currently being executed, it has been set to 1" first, and the process proceeds to step W1, where the data in the S register and the data in the N register are 50''. In this case, if a data input operation has been performed, the relationship S≦N is established and the editing work begins in step W1m, but if no data input operation has been performed, S>N is established from the processing in step W1. , and this writing process ends.

Step WI! In the editing work, the work of arranging the 6 character data in the data in each of the data storage registers 1 to 50 is performed. When that work is completed, step W8. Edit flag FSE! is set to 10", and then by repeating steps W14 to W, o, the actual number of data in RAM II, that is, the number of used registers n from 1 to 50.
is calculated.

That is, first, in steps W1 to W□, data "0" is set in the n register and data rlJ is set in the P register. Then, the P-th page, ie, the first page, of the AM II is specified (step W16), and it is determined whether there is data there (step W1y). Then, if there is data, the n register is incremented by 1, and if not, it is not incremented by 1 and step W.

Proceed to. Then, it is determined whether the data in the P register is equal to the data "50" in the N register, that is, whether the search for the presence or absence of data has been performed up to the 50th page. Proceed to step W1o and P
The register is incremented by 1 and the next page is designated. In this way, step W1. The process ww and o are repeated 50 times to find the number of registers used, n, and when N=P, the process ends.

Next, referring to FIGS. 7 and 10, step 0.
The read processing of step 6 will be explained. In this case, if the data in the registers 1 to 50 are to be sequentially read and displayed, the switch SA or SB is operated, and if the number of registers in use is to be displayed, the switch S is kept pressed.

For example, if you operate switch SA now, step 1i
The operation is determined by step R1, and n
It is determined whether the register data (the number of registers in which data is written) is not "0", and if n=
If =l'-QJ, then no data is stored in any of the data storage registers 1 to 50, so step R is executed.
The process advances to step 1, and data display processing for the current page is performed.

In this case, since no data has been written to this page, delimited data indicating no data is displayed as shown in D in FIG. 10.

On the other hand, if n40, the process advances to step R8 and the P register and n register are compared. If it is Pkn, go to step 几 and advance the currently displayed page to the next page.
The data of that page is displayed (step R1). If p = n, proceed to step R4 and check whether the data in the N register is equal to the data "50" in the N register, that is, whether data has been written to all registers from 1° to 50. If there is an empty page (rNOJ), the process advances to step R6, returns the current display to the first page, and displays the data (step R
,). Also, if data has been written to all pages (rYE8), proceed to step R5, specify the next page, and display the data (step R?) O and P)
When n, proceed to step R1 and return to the first page,
Display the data (step R?).

In this way, each time the switch SA is operated, the necessary steps from step ■ to R2 are executed based on the relationship between the currently displayed page and the number of n registers used, and the next page is sequentially specified. The data will then be displayed. A-+B-)(!-+D- in Figure 10)
+A→... indicates this situation, for example 1 to 50
If data has been written to registers 1 to 20 among the registers in , and if the P register is on page 3 when this read process is started, first the data on the third page will be displayed. and then switch sA
Each time you operate , 4.5, dl..., 19.20
Each page of data is displayed, and when the 21st page with no data written is reached, a delimited data display with no data as shown in D in FIG. 3.4, . . . , 20 pages of data are displayed, and then the display of delimited data with no data on the 21st page and returning to the 1st page are repeated.

Since the switch SB is a switch that addresses l'LAM11 in the negative direction, contrary to the switch SA, step R6-几1. Since each process is self-evident, the explanation will be omitted.

Next, when you want to know the number of registers in use, press the switch S1, and for the duration of the press, for example, 27150 is displayed as shown in E in FIG. In this case, "27" indicates the number of registers used, and "50" indicates the maximum number of pages.

Immediately, when switch S1 is pressed, step R'fLs
The process advances to step R111 via step R111, and the pressing operation is determined. Then, the number display process as shown in the sword in Figure 10 (
Step R86) is performed.

Although the number of used pages is displayed in the above embodiment, the number of remaining pages may be displayed.

Furthermore, when data is read out sequentially each time a switch is operated, in the above embodiment, when the last data of the data written in alphabetical order in the data storage registers 1 to 50 is read out and displayed, the next register is read out. The delimited data is displayed to show that no data has been written, but in addition to this, for example, data is currently stored in registers 1 to 10, and when switching to memory mode, the data in register 5 is displayed first. Assuming that, every time the switch is operated, 5→
The delimited data may be displayed as follows: 6 → 7 → 8 → 9 → 10 → 1 → 2 → 3 → 4 → delimited data → 5 → 6 → . Furthermore, it goes without saying that the arrangement order performed when editing data is not limited to alphabetical order.

Further, the present invention is not limited to the electronic wristwatch h1. The present invention is applicable to any small electronic device having a memory.

〔Effect of the invention〕

As explained above, in this invention, data editing work is performed after all data has been input, so even if a key operation error occurs during data entry, there is no problem with the editing work, and the editing work can be done quickly and reliably. It has the advantage of being able to be edited.

[Brief explanation of drawings]

Fig. 1 is an external view of an electronic wristwatch according to an embodiment of the present invention, Fig. 2 is a block diagram of the display unit 2, Fig. 3 is a circuit block diagram, Fig. 4 is a block diagram of the AMII, and Fig. 5 is a block diagram of the electronic wristwatch. Figure 6 shows the general flow, Figure 6 shows the write process flow, Figure 7 shows the read process flow, Figure 8 shows the transition between clock mode and memory mode, and Figure 9 shows the write mode. FIG. 10 is a diagram showing state transition in read mode. 2...Display section, 3...Character display section, 4
...Numeric display section, 7. River... Oscillator, 8...
...Frequency divider circuit, 9...Timing signal generation circuit, 10...ROM, 11...RAM
, 12... Instruction decoder, 13... Address control unit, 14... Arithmetic unit, 15...
...Decoder, 16...Input section, S□-, S
2, S II, S A N5B1SL...
switch. Patent applicant Casio Computer Co., Ltd. Figure 1 Figure 2 Figure 4 Figure 51 Figure 8 Figure 9 Figure 10 Procedural amendment (voluntary) September 20, 1981 Manabu Shiga, Commissioner of the Patent Office 1, of the case Indication Patent Application No. 58340 of 1983 2, Name of the invention, Small electronic device with data storage function 3, Relationship to the case of the person making the amendment Patent applicant address: 2-6-1 Nishi-Shinjuku, Shinjuku-ku, Tokyo Name: (
144) Casio Computer Co., Ltd. Representative: Toshio Kashio 4, Agent address: 6-7-16-5, Ginza, Chuo-ku, Tokyo Subject of amendment (1) "Detailed description of the invention" column of the specification. 6. Contents of amendment (1) In the first line of page 5 of the specification attached to the application, “...
...Correct the phrase ``also data'' to ``also numerical data and address data.'' (2) Similarly, on page 5, lines 14 to 17 of the specification, there is a statement that says, ``...Also, the calculation unit 14 is 1/32...
・Additionally, the “0'' signal and carry signal generated by the calculation of the calculation unit 14 are given to the address control unit 13, and the RO is input according to the calculation result of the calculation unit 14.
The address of Ml0 can be changed. Furthermore, the 32 Hz clock clock output from the frequency dividing circuit 8 is also input to the address control section 13, and so on.'' (3) Similarly, it is blank from page 17, line 20 to page 18, line 4 of the specification. (1'-YESJ)
, step RsJ [and when data has been written to all pages ("y:g8J"), step R
Proceed to step 6 to return the current display to the first page and display the data (step R?). Also, if there is an empty page, correct it as (rNOJ 1. Step RsJ). (4) Correct the drawings in Figures 3 and 7 as shown in the attached sheet.

Claims (1)

[Claims] a storage means having a plurality of data storage sections capable of storing data consisting of a plurality of characters; a data writing means for sequentially specifying the plurality of data storage sections of the storage means and writing data into the plurality of data storage sections; After the data writing means finishes writing data to multiple data storage units,
A small electronic device with a data storage function, comprising: editing means for rearranging data in a plurality of data storage sections of the storage means in a predetermined order.