JPS6310553Y2 - - Google Patents

Description

[Detailed Description of the Invention] The present invention relates to a key input control circuit for a small electronic device such as a small electronic calculator.

In recent years, small electronic calculators have been made smaller and thinner, and have also become functionally capable of displaying clocks, calendars, etc. There are also wristwatches that have calculation functions so that they can be used as calculators if necessary. In such calculators, the number of key switches is limited, so various designs have been developed in which one key can perform multiple functions.For example, by sequentially operating one key, mode selection and setting can be performed. Compact electronic computers that perform this have also been put into practical use.

However, in a wristwatch-like calculator such as the one described above, the number of keys that can be provided is extremely limited, so it is not desirable in terms of space to provide a separate mode switch for mode selection and setting.

The present invention has been made in view of the above points, and it is an object of the present invention to provide a key input control circuit that can reduce the total number of keys by allowing the mode key to also serve as an all clear key and a clear entry key.

An embodiment of the present invention will be described below with reference to the drawings. In FIG. 1, reference numeral 1 denotes a key input section, which is provided with a numeric keypad 2, a function key 3, and an M/C key 4 that serves both a clear function and a mode selection function. This M/C key 4 can be used to select various modes such as clock display mode, calculation mode, stopwatch mode, and separate clock mode.In calculation mode, clear entry (CE) and all clear (AC) can be selected. It has a function. The key operation output from the key input section 1 is input to the control section 6 in the control unit 5. Also, 7 is a pulse oscillator (PG) that generates a reference pulse signal.
The output of the pulse oscillator 7 is divided into a 1/100 second signal and a 1 second signal by a frequency divider 8 and sent to the control section 6. Further, the frequency divider 8 outputs clock pulses φ ₁ and φ ₂ having the same period and a phase difference of 180°, and is sent to the timing signal generating circuit 9. The timing signal generation circuit 9 generates various timing signals based on the input clock pulses φ ₁ and φ ₂ and supplies them to the control section 6 and other circuits. The control unit 6 is equipped with output lines a, b, and c that output signals according to the operation of the M/C key 4, and the output lines a and b output signals as "0" or "1" depending on the conditions at that time. " signal is output, and a "1" signal is output from the output line c each time the M/C key 4 is operated. That is, when the M/C key is operated, the output lines a and b of the control unit 6 output "0, 0" after inputting a number in calculation mode, and "1" after calculation or clear entry. , 0", "0, 1" after all clear or mode change
signal is output. Therefore, the signals output from the output lines a and b are output from the flip-flop
Input to F ₁ and F ₂ respectively. The outputs of the flip-flops F ₁ and F ₂ are the AND circuits 11 and 11, respectively.
12 and also to an AND circuit 15 via inverters 13 and 14. Further, the signal output from the output line of the control section 6 is passed through the transfer gate 16 to the AND circuits 11, 12,
15. The output of the AND circuit 15 is used as a clear entry signal, and the output of the AND circuit 11 is used as an all clear signal for the control unit 6.
is input to. Further, the signal outputted from the output line c of the control section 6 is transferred to the transfer gate 1.
7, and is sent to the quaternary mode counter 1 through the OR circuit 18 together with the output of the AND circuit 12.
9 as a count-up signal. This mode counter 19 is connected to the upper bit output line 19.
a and lower bit output line 19b, 0 to
``00'', ``01'', ``10'', depending on the count in step 3.
Outputs a binary code signal of "11". Then, the output of the mode counter 19 is directly and inverter 2
It is sent to the decoder 21 via 0a and 20b.
This decoder 21 selectively outputs a "1" signal to output lines 21a to 21d according to the contents of the mode counter 19. This mode counter 19
The signals output from the output lines 21a to 21d are respectively input to the mode designation terminals of the control unit 6, that is, the terminals that designate the clock display mode WAT, the calculation mode CAL, the stopwatch mode ST, and the separate clock mode DUAL. Ru. In addition, the decoder 21
The signal outputted from the output line 21b of
is sent as a gate signal via However,
The control unit 6 outputs control signals according to key input data from the key input unit 1, clock data from the frequency divider 8, etc. It is sent to the control section 25. The RAM 23 is made up of various registers such as a display register 23a, a clock register 23b, and a separate clock register 23c, and writes data from and to the arithmetic circuit 24 in accordance with control instructions from the control unit 6. Data reading is performed. The data output from the arithmetic circuit 24 is then sent to the display control section 25 and displayed on the display section 26.

Next, the operation of this embodiment configured as described above will be explained. The control unit 6 accesses the RAM 23 every time the 1-second signal is input from the frequency divider 8, gives a control command to the arithmetic circuit 24, and adds 1 second to the clock register 23b and separate clock register 23c of the RAM 23. That is, the clock register 23b is caused to perform a time measurement process with respect to the current time, and the separate clock register 23c is caused to perform a time measurement process based on an arbitrarily set time in advance. By setting the time of any designated country in the world in this separate clock register 23c, the current time of that country can be known. In addition, when the stopwatch mode is specified, the control unit 6 also controls the frequency divider 8.
Timing processing is performed using the 1/100 second signal inputted from the controller, and the clock data is stored in the RAM 23 and displayed on the display section 26.

Thus, the mode of the control unit 6 is designated by the contents of the mode counter 19 associated with the operation of the M/C key 4, and the mode counter 19 is shown in FIG.
The relationship between the contents and the specified mode is shown. That is,
If the content of the mode counter 19 is ``0'', the clock display mode is specified, if it is ``1'', the calculation mode is specified, if it is ``2'', the stopwatch mode is specified, and if it is ``3'', the separate clock mode is specified. . In addition, when the content of the mode counter 19 is "1" and the calculation mode is specified, operating the M/C key 4 after setting the number will perform a correction entry operation (clear entry), and the calculation or correction entry operation will be performed. When the M/C key 4 is operated later, a bankrupt operation (all clear) is performed.

Next, referring to Figures 3 and 4, press the M/C key 4.
The details of the mode specifying operation and clearing operation by the operation will be explained. As shown in FIG. 3a, when the contents of the upper and lower bits of the mode counter 19 are "00", the output line 2
A "1" signal is output from 1a to designate the clock display mode, and this mode designation causes the current time held in the clock register 23b to be displayed, for example, "A.M.
"10:00:30" is read out to the display control section 25 via the arithmetic circuit 24 and displayed on the display section 26. In this state, when the M/C key 4 is operated, a "1" signal is output from the output line c of the control section 6, and the transfer gate 17 and OR circuit 1 are output.
8 to the mode counter 19. As a result, as shown in FIG. 3b, the mode counter 19
The content of is incremented by +1 and becomes “01”, and the decoder 21
A "1" signal is output from the output line 21b to designate the calculation mode. At the same time, flip-flop _F1 is set to “0”, flip-flop F2 is set to “ _0”
“1” is written to. When this calculation mode is designated, the transfer gate 16 is brought into an open state by the "1" signal output from the output line 21b of the decoder 21. In this case, the transfer gate 17 is closed by the "0" signal input via the inverter 22.
In this state (see Figure 3b), immediately M/
When the C key 4 is operated, the output line c of the control section 6
As a result, the AND circuit 12 outputs a “1” signal, and the OR circuit 18 outputs a “1” signal.
It is sent to the mode counter 19 via. Therefore, the content of the mode counter 19 is incremented by 1 and becomes "10", and a "1" signal is output from the output line 21c of the decoder 21 to designate the stop watch mode, and as shown in FIG. ” is displayed. In this stopwatch mode, by operating the start/stop key (not shown) in the key input unit 1, time is measured in units of 1/100 seconds as described above. When the M/C key 4 is operated in this state, the "1" signal output from the output line c of the control section 6 is sent to the mode counter 19 via the transfer gate 17 and the OR circuit 18, and its contents are incremented by +1. Ru.
Therefore, as shown in FIG. 3d, the mode counter 19
The content becomes "11", a "1" signal is output from the output line 21d of the decoder 21, the separate clock mode is designated, and the mode is displayed as "DUAL".
In this case, a different clock time of ``3:01:6'' is displayed. If the M/C key 4 is further operated in this state, the contents of the counter 19 will be increased by +1 as shown in Fig. 3e.
and returns to the state of "00", and the clock display mode is designated again.

When the M/C key 4 is operated in the clock display mode shown in FIG. 4a, the calculation mode is designated as shown in FIG. 4b. In this calculation mode, for example, as shown in Figure 4c, □2□3□×
If the key operation is performed, "23." is displayed on the display section 26. Next, if the user presses the key □4 as shown in FIG. 4d, the display section 26 will display "4.". Now, if this key operation of □4 is an error and the error is noticed immediately after the key input, the M/C key 4 is operated as shown in FIG. 4e. In this calculation mode, as described above, a "1" signal is output from the output line 21b of the decoder 21, and the transfer gate 1
6 is open. Further, when the numeric keypad 2 is operated, the contents of the flip-flops F ₁ and F ₂ are cleared, and the outputs of the inverters 13 and 14 become "1" and are input to the AND circuit 15. Therefore,
As described above, when the M/C key 4 is operated after setting the number, the "1" signal output from the output line c of the control section 6 is input to the AND circuit 15 via the transfer gate 16, and the "1" signal is input from the AND circuit 15 to the AND circuit 15. 1” signal is output and clear entry processing is executed. Further, when the M/C key 4 is operated, a "1" signal is also output from the output line a of the control section 6, and this "1" signal is transmitted to the AND circuit 1.
5 is sent to the control section 6 and then read into the flip-flop _F1 . Thereafter, when the correct numerical value "5" is input as shown in FIG.
Furthermore, by operating the numerical keys in □5 above, "0" is written into each of the flip-flops F ₁ and F ₂ .
Then, when the □= key is operated as shown in FIG. It is displayed in section 26. Further, when the □= key is operated, a "1" signal is output from the output line a of the control section 6 and written to the flip-flop _F1 . Therefore, in this state, when the M/C key 4 is operated as shown in FIG. 4g, a "1" signal is output from the AND circuit 11, and all clear processing is performed. Also, by operating the M/C key 4 above, the flip-flop
" ₀ " is written to F1, and "1" is written to flip-flop _F2 . After the above-mentioned all clear processing, when the M/C key 4 is operated as shown in FIG. Ru. As a result, a "1" signal is output from the output line 21c of the decoder 21, and the stopwatch mode is designated. In this manner, the operation mode is designated and the clear process is performed by operating the M/C key 4.

As described above, according to the present invention, the mode key has the function of switching various modes, the function of the all clear key, and the function of the clear entry key, and each function is selected according to the processing state of the control means in the calculation mode. By selecting one of them, the total number of keys can be reduced, and the practical effect of realizing miniaturization of small-sized electronic devices such as small-sized electronic calculators can be achieved.

[Brief explanation of the drawing]

The drawings show one embodiment of the present invention; Fig. 1 is a circuit configuration diagram, Fig. 2 is a diagram showing various mode designations and clear designation states by operating the M/C key, and Fig. 3 a - 4e is a diagram showing details of designating various modes by operating the M/C key, and FIGS. 4a to 4i are diagrams showing details of clearing operation by operating the M/C key when calculation mode is designated. 1...Key input section, 4...M/C key, 6...
Control unit, 19...mode counter, 21...decoder, 23...RAM (random access memory), _F1 , _F2 ...flip-flop.

Claims (1)

[Claims for Utility Model Registration] A control means 6 which has a plurality of modes including at least a calculation mode and outputs various commands for executing processing according to each mode, and a calculation is executed by the commands from the control means. A small electronic device having a calculation means 24 for controlling the control means, a key input means 1 having a mode key 4 for sequentially specifying switching among the above-mentioned modes, and a mode storage means 19 for storing mode data indicating the mode of the control means. and, in the calculation mode, according to the processing state of the control means, a first processing state indicating after numeric entry, a second processing state indicating after calculation or clear entry processing, and after all clear processing or mode change. state storage means for storing a third processing state indicating the next processing state;
F ₁ , F ₂ , and allow input of the mode key when the stored content of the mode storage means is not the calculation mode;
first logical control means 17, 22 for outputting a mode update signal for updating the mode data to the mode storage means; the mode storage means stores the calculation mode, and the state storage means stores the calculation mode; second logic control means 13, 14, which allows the input of the mode key when the processing state of the above is stored and outputs a clear entry signal for clear entry processing;
15, when the mode storage means stores the calculation mode and the state storage means stores the second processing state, input of the mode key is allowed, and all clear for all clear processing; a third logic control means 11 for outputting a signal; and allowing input of the mode key when the mode storage means stores the calculation mode and the state storage means stores the third processing state. and fourth logic control means 12 for outputting the mode update signal to the mode storage means.