JPS60105043A - Information processing system - Google Patents

Abstract

PURPOSE:To attain addition of a new instruction without narrowing an operand designating range by providing protecting mechanisms to both hardware and software areas, and inhibiting the access of both areas. CONSTITUTION:A program of a software area SA is read out of a memory control unit and sent to a preceding control unit via a line 115. The instruction held at an instruction register 31 is decoded and sent to an access control circuit 36. An access signal for hardware area HA is sent to the memory control unit via a line 203. It is decided whether an address exception exists or not with use of an operand address. Then an address exception signal is sent to an arithmetic unit. While the instruction held at the register 31 is also set to an instruction queue 32 and then sent to the arithmetic unit from a line 300 at a fixed time point. The arithmetic unit reads out the contents of a general-purpose register 34 and performs an operation with the operand sent from the memory control unit. The result of this operation is written to the register 34 via a line 310.

Description

[Detailed Description of the Invention] [Field of Application of the Invention] The present invention relates to an information processing system, and in particular, a main memory is divided into a hardware area and a software area, and the hardware area includes an instruction execution procedure for processing a specific complex instruction. The present invention relates to an information processing method that improves protection for the hardware and software areas and enables an increase in the number of microprograms in a device storing the information.

[Background of the invention]

In conventional microprogram-controlled information processing devices, instructions are processed by microprograms stored in fixed logic circuits or control storage devices. There are some instructions that are used very infrequently, and instructions that are executed by a wide variety of very complex processes, but if you try to execute these instructions with a conventional microprogram-controlled information processing device, fixed logic circuits have become very complex, or microprograms have increased).

Furthermore, in the above information processing apparatus, it is extremely difficult to add new instructions.

Therefore, in order to improve the above-mentioned drawbacks, a column of multiple types of instruction executors + An information processing device was proposed that executes a sequence of instruction execution procedures when a temporary event occurs (Japanese Patent Laid-Open No. 56-21
No. 237 and Japanese Unexamined Patent Publication No. 56-124952).

The sequence of instruction execution procedures described above is stored in the hardware area of the main memory, and the program that can be viewed by the operating system is stored in an area called a software area.

By the way, when the instruction execution procedure in the hardware area accesses the main memory, the software area,
Must be able to do both in the hardware area. Moreover, when accessing the software area, it is necessary to perform main memory access according to the mode of the program state word immediately before control is passed to the above instruction execution sequence, and when accessing the hardware area, It is necessary to use real addresses and prohibit memory protection. Furthermore, when accessing the software area, it is necessary to make an exception when the hardware area is accessed by mistake; The protection mechanism can be improved.

However, in the conventional information processing device described above, two types of access modes are provided for accessing the main memory, and in the first access mode, the main memory is accessed using the execution address and memory protection is prohibited. Second access
mode, according to the mode of the program state word immediately before the interrupt that transfers control to the sequence of instruction execution steps described above occurs.
Accessing main memory. The problem with the above-mentioned conventional information processing devices is that in the first access mode, the purpose is to access the hardware, or it is also possible to access the software area. . Further, in the second access mode, the purpose is to access the software area, but it is also possible to access the hardware area, and the protection mechanism is insufficient.

In such a case, it is necessary to specify whether the access is to a software area or a hardware area. Therefore, in conventional devices including the above-mentioned information processing device, a part of the operand address specification is used to specify this in the instruction execution procedure.

For example, in the case of the above-mentioned information processing apparatus, a Bass Regino Focus O was used. However, this specification method has the disadvantage that the operand address specification range becomes narrow because one pit of the operand address information is used for specification other than addresses.

Furthermore, the above-mentioned publication does not disclose anything about a method of specifying an operand address specified by an instruction execution procedure in a hardware area.

[Purpose of the invention]

An object of the present invention is to eliminate such conventional drawbacks, and to store an instruction execution procedure for processing a specific compound instruction in the hardware area of the main memory, and to store a program in the software area. In an information processing device, there is protection for hardware areas and software tracking areas, and when specifying which area to access, there is no need to narrow the specified range of operand addresses, and fixed logic It is an object of the present invention to provide an information processing device that does not require complication of the iL6 or increase in microprograms, and can easily add new instructions.

[Summary of the invention]

In order to achieve the above object, the information processing device according to the first aspect of the present invention includes:
The software area of the main memory stores the program r11, and the hardware area stores a sequence of instruction execution procedures to be executed when processing a specific compound instruction or when a specific event occurs. In the device, when executing the above sequence of instruction execution steps, the main memory is accessed in the first or second access mode selected according to the base field, but in the first access mode, the main memory is accessed using the real address. At the same time, memory protection is prohibited and access to the software area is prohibited. It is characterized in that it accesses according to the mode of the status word and also accesses the hardware area.

[Embodiments of the invention]

Embodiments of the present invention will be described below with reference to the drawings.

FIG. 1 is an explanatory diagram of divided areas of a main storage device applied to the present invention.

As shown in Figure 1, the main memory is a hardware area (
) J, A) and a software area (SA). The hardware area (HA) includes a fixed area (H
PXA) is established, and a software security area (S
A) is also provided with a fixed area (SFXA), and both of these areas are prefix areas. The hardware area contains a sequence of instruction execution procedures for processing specific compound instructions stored in the software area, a sequence of instruction execution procedures for processing that should be performed when a specific event occurs, etc. Stored. The fixed area (HPXA) and fixed area (SPXA) each have a new PSW (prog
ram 3tatus Word) and the old psw are stored. The boundary address (BADR) is an address that separates the hardware area (HA) and the software area (SA).

FIG. 2 is a diagram showing the command formats of newly established commands used in the present invention and commands to which the present invention is applied.

These instruction formats are the instruction formats used in IBM's System/370 data processing system, so
For details, see IBM Manual GA-7000 [IBM S
system/ 370 principles ofQ
See perat ion J.

(a) is called the S format, and includes a 16-bit operation code, a B2 field (also called the base field) that specifies one general-purpose register (called the base register) that stores the base address, and a B2 field (also called the base field) that stores the base address. It consists of a displacement field D2 containing 12-bit displacement values to be added. The operands used (residing in main memory) are specified indirectly by the B2 field and the contents of the B2 field.

(c) This is called the HaRX format, and includes an 8-bit operation code, an R1 field that specifies a general-purpose register that stores one operand, an X2 field that specifies one general-purpose register that stores an index address, and a base. It consists of a B2 field that specifies one general-purpose register that stores an address, and a displacement field D2 that contains a 12-bit displacement value that is added to this index address and the base address. The other operand used (residing in main memory) is specified indirectly by the contents of the X2 field, the B2 field, and the B2 field.

(d) is called the R8 format, which stores an 8-bit operation code, one operand, and specifies a general-purpose register. It consists of an R3 field, a B2 field specifying one general-purpose register storing a base address, and a displacement field D2 containing a 12-bit displacement value to be added to this base address. The other operand used (residing in main memory) is specified indirectly by the B2 field and the contents of the B2 field.

(e) is called the ST format, and includes an 8-bit operation code and one 8-bit operand itself.
field, a B1 field that specifies one general-purpose register storing a base address, and a displacement field D1 that contains a 12-bit displacement value to be added to this base address. The other operand to be incremented (residing in main memory) is specified indirectly by the B1 field and the contents of the B1 field.

(f) is called the SS format, and includes an 8-bit operation code, an L field that specifies the operand length, a B1 field that specifies a general-purpose register that stores one base address, and 12 bits that are added to this base address. A y-position field D1 containing a bit displacement value, a B2 field specifying the general-purpose register storing the other base address, and a displacement field D2 containing a 12-bit displacement value to be added to this base address.
It consists of One operand used (residing in main memory) is specified indirectly by the contents of the B1 and DI fields, and the other operand (residing in main memory)
(existing in main memory) is indirectly designated by B2 field 2 and the contents of B2 field.

(b) shows the instruction format of the "Ir installation instruction" used in the present invention.

Newly installed instructions are executed only in the instruction execution procedure of the hardware area, and are used in the end macro mode (E
MD) is a command.

It should be noted that when main memory access is performed in FIGS. 2(a) and 2(c) to 2(f), the base field (B1 field or B2 field) is always specified.

The EMD instruction in Figure 2(b) stores 8 bytes starting from address 28 of the fixed area (HPXA) into PSW, and stores 4 bytes starting from address θ of the fixed area (HPXA) into general-purpose register 12 (not shown). Store. It also has a function to reset macro mode. Reading of instructions from the new PSW is performed after the macro mode is reset. If specified in a mode other than macro mode, an instruction exception will occur.

FIG. 3 is an explanatory diagram of the operation when a specific compound instruction is detected, FIG. 4 is an overall block diagram of an information processing apparatus showing an embodiment of the present invention, and FIG. 5 is a predecessor of FIG. 4. FIG. 6 is a detailed block diagram of the IflJ control unit, and FIG. 7 is a detailed block diagram of the address generation means of FIG. 5.

FIG. 8 is a detailed diagram of the memory access control circuit of the memory access control means of FIG. 5 and the storage control unit of FIG. 4, respectively.

In FIG. 3, the main memory, the PSW register, and the general-purpose register 12 are shown.As is clear from FIG. 1, the main memory has a software area (SA) above the boundary address (BADR), The hardware area (H
A).

Complex instructions are stored in a part of the software area (SA), and a fixed area (HPXA) of the software area (HA) under the bar is stored.
) has an old PSW save area and a new PSW storage area, and other areas store instruction depth procedures.

In the example shown in FIG. 4, the information processing device is the arithmetic unit 7.
, a preceding control unit 4, a storage control unit 5, and an input/output device 6. The storage control unit 5 includes a main storage device, and the input/output device 6 includes an input/output controller.

As shown in FIG. 5, the advance control unit 4 in FIG.
Instruction buffer 30, instruction register 31, instruction queue 32
, a decoder 33, a general-purpose register 34, an address generation means 35, a memory access control means 36, and a boundary address register 37.

The program of the software area (SA) is read out from the storage control unit 5 of FIG. 4 and sent to the advance control unit 4 via line 115.

In the advance control unit 4, as shown in FIG.
The program sent via 5 is set in the instruction buffer 30, and the instructions are extracted one by one and held in the instruction register 31. OP of the instruction held in the instruction register 31
The code field is decoded by the decoder 33, and the index field of the instruction is ll5301.
F'i)1. The search result is sent to the address generating means 35 via line 121 and the index register.

Further, the base field of the instruction is stored in the general-purpose register 34 by multiplying the line 302 by μ, and the read result is shown on the line 120.
and the address generation means 3 via the base register.
5 and the taste placement field of the instruction is sent via line 303 directly to the address generating means 35.

In the address generating means 35, the address sent via the line 120 is input to the AND gate A as shown in FIG.
1 is sent to the input terminal of the three-way adder 1 via the base register 2. On the other hand, the address sent via line 121 is passed through index register 3 to the other input terminal of three-way adder 1, and the address sent via line 303 is It is sent to the remaining input terminals of the three-way adder 1. and,
Perform address calculation with three-man power adder 1 and add operand.
It generates an address and sends the result to the storage control unit 5 via line 110. In the storage control unit 5,
The address on line 110 is used to read the sioberand from the main memory and sent to the arithmetic unit 7 via line 205.

The instruction held in the instruction register 31 is decoded by the decoder 33, and the decoded result is sent to the memory access control means 36 via line 2 (Jl). The I-I A access signal is sent to the memory access control means 36. The memory access control means 36 sends the I-I A access signal to the storage control unit 5 via the line 203. 110 is used to determine whether or not there is an address exception, and the address exception signal is sent to line 2.
04 is sent to the arithmetic unit 7 through four channels.

The instructions held in the instruction register 31 are stored in the instruction queue 32.
and is sent to the arithmetic unit 7 via line 300 at a predetermined time. In the arithmetic unit 7, the contents of the general-purpose registers in the arithmetic unit 7 are read using the instructions of the gland 300. The operands sent from the storage control unit 5 and the contents of the above-mentioned general-purpose registers are multiplied by the arithmetic unit 7, and the result is sent to the advance control unit 4 via the line 310, and is stored in the general-purpose register 34 as 1. Get into it. The result is also written into the general-purpose register of the arithmetic unit 7.

The features of the present invention reside in the address generation means 35, the memory access control means 36, and each memory access control circuit within the storage control unit 5.

7 shows a memory access control circuit in the memory access control means 36, and FIG. 8 shows a memory access control circuit in the storage control unit 5.

Next, the operation of these memory access control circuits will be explained.

When a program in the software area (SA) is being executed, if a specific compound instruction exists, that compound instruction is similarly read out and held in the instruction register 31 via line 120. The compound instruction is then set in an instruction queue 300 and then sent to the arithmetic unit 7 via line 300. The arithmetic unit 7 sends an interrupt signal and a macro mode set signal 1" to lines 101 and 200, respectively, as a computation of a compound instruction. The memory access control means 3 of the advance control unit 4
6, as shown in FIG. 7, the cymacromode clip 70 tube 10 is set by the signal sent through the line 200, and the macromode signal line 100 is set to 61''.

Next, in the address generating means 35 of FIG.
'' is input to the index register 3. Also, since the macro mode signal line 100 becomes 1'' and the interrupt signal line 101 becomes ``1'', the contents of the boundary atres are set to the base register 2 via the line 122. . A value is set in the boundary address register 37 in FIG. 5 by an initial state setting operation of the system, for example, by scan-in. The contents of the base register 2 and index register 3 are the contents of the three-manual adder 1 in FIG.
and the addition result is sent to the storage control unit (S unit) 5. The addition result output from the 3-way adder 1 indicates the address of the old PSW for the program interrupt in the fixed area (HPXA), and the current PSW is set to the old PSW by the control 1 of the storage control unit 5. (See ■ in Figure 3). Next, when the constant "68" is input to the index register 3, the contents of the base register 2 and the contents of the index register 3 are added by the three-way adder 1 in the same way. The result shows the address of -#psw in the fixed area (HPXA), and the new PSW is thereby set to the current PSW (see ◯ in FIG. 3).

The current PSW before replacement and the current PSW after replacement have different instruction addresses, but other parts such as the memory protection key and mode pit are almost the same.

Next, the constant "00" is input to the index register 3, and the contents of the base register 2 and the contents of the index register 3 are added by the three-output adder 1 in the same manner. The result of this addition indicates the save area of the fixed area (HPXA), and the general-purpose register 12 is thereby saved to the save area (see ■ in FIG. 3).

Next, the boundary address is read and stored in the general-purpose register 12 (see ■ in FIG. 3).

Thereafter, the corresponding sequence of instruction execution procedures is read from the hardware area (HA) and executed. In the instruction execution procedure, general purpose register 12 can be used as a base register.

When the execution of the corresponding instruction execution procedure sequence is completed and one interrupt processing is completed, the old PsW in the fixed area (HPXA) is set to the current SW (1) by the EMD instruction shown in FIG. 2(d). (See ■ in Figure 3).

When the EMD instruction is held in the instruction register 31, it is recognized by the decoder 33 and a return signal of 1'' is output on the line 210. As a result, the flip-flop 10 of the memory access control means 36 of FIG. 7 is reset. As a result, the macro mode signal line 100 becomes "0".In this way, a sequence of instruction execution procedures in the hardware area (HA) corresponding to a specific compound instruction in the software area (SA) is executed. .

The above explanation was an example in which when a specific compound instruction is detected, the corresponding sequence of instruction execution procedures in the hardware area (HA) is executed by an interrupt. However, if a specific event is detected, Also, a sequence of corresponding instruction execution procedures in the hardware area (HA) is executed.

During the execution of the command execution procedure sequence in the hardware area (HA), the macro mode signal line 100 is ``1'', but the line 101 is 0'' except for the EMD instruction, so the base register The contents of are entered into base register 2.

In this way, when executing the sequence of instruction execution procedures in the hardware area (1-(A)), the macro mode signal m1
00 is 1'.

The most significant bit of the base field is sent via line 202 to memory access control means 36.

The base field is composed of 4 bits as shown in FIG. When the line 202 is "1", that is, the value of the base field is 8 to 15, the circuit of FIG.
The A access signal line 203 is "1".

becomes.

When the HA access signal line 203 is 1'', the address information is real address information and memory preservation is prohibited.

In the memory access control circuit shown in FIG. occurs and the operating system is notified.

This means that when an instruction specifying 8 to 15 in the base field is executed as a sequence of instruction execution procedures in the hardware area (LA), accessing the software area (SA) is prohibited, and the hardware Area (HA
).

The line 202 is "0", that is, the base field value is 0 to 7.
In the case of HA access signal gland 203 by the circuit shown in FIG.
is "0'°. If the HA access signal line 203 is 0", whether the address information is real address '1♂j information, a logical address, or a logical address depends on the current PSW. It means.

In the memory access control circuit shown in FIG. 8, when the HA access control line 203 is 0'', the address register 2
When the content of 0 exceeds the content of the boundary address 21, the output of the compensator 22 is [address>boundary register], and the operating system is notified of the occurrence of the address exception. This means that the base field is 0~
7 and the command is executed as a sequence of instruction execution steps in the hardware area (HA), the software
Direct installation (SA) can be accessed, and hardware area (H
This indicates that access to A) is prohibited.

When an instruction in the software area (SA) is being executed, the macro mode signal line 100 is 0'' as described above, so in the circuit shown in FIG. 7, the HA access signal line 203 is set to II OII. The operation when the HA access number line 203 is 0'° is as described above.

Even when the HA access signal line 203 is "0" or 11', if the access address exceeds the maximum capacity t of the main memory, the operating system is notified of the occurrence of the address exception condition. Ru.

As described above, main memory access in the instruction execution procedure of the hardware area (HA) is controlled f9 by the HA access signal 1203, and when the HA access signal is 60'', main memory access is performed according to the current PSW. access to the software area (SA) is permitted, but access to the hardware area (HA) is prohibited.On the other hand, when the HA access signal is 1'', the main address is used as the real address. Storage access is performed, and access to the hardware area (HA) is allowed, but access to the software area (SA) is prohibited. Further, whether the HA access signal is 0'' or 1'' is defined according to the base field, and therefore does not narrow the range in which the operand address can be specified. By changing the i-direction of the base field even in the same instruction, the software area (
SA) Both the upper and lower hardware areas (1iA) are accessed.

A sequence of instruction execution procedures in the hardware area (HAI) corresponds to one specific compound 66 instruction in the software area.
In order to treat the instruction in the same way as the 1+i-1 compound instruction, execution A of this series of instruction execution procedures prohibits interrupts other than hard machine checks and program interrupts.

A sequence of instruction execution steps that correspond to specific events? Even when the program is running, interrupts other than hard machine checks and program interrupts are similarly prohibited.

〔Effect of the invention〕

As explained above, according to the present invention, when accessing the hardware area, access to the software area is prohibited, and when accessing the software area, access to the hardware area is prohibited. Therefore, it is possible to provide a protection mechanism that is improved compared to the conventional one. Furthermore, since it is possible to specify by the base field whether to access the hardware area or the software area, the specified range of operand addresses is not narrowed. Furthermore, the hardware area (H
A) The above operand address can be easily specified, and no special hardware is required in this case. New instructions can be easily added, and instructions that are executed by a wide variety of complex processes or instructions that are used infrequently can be executed without complicating fixed logic circuits or increasing the size of microprograms. be able to.

[Brief explanation of the drawing]

Fig. 1 is an explanatory diagram of the divided areas of the main storage device applied to the present invention, Fig. 2 is a diagram showing the Ura-rei format of the new building order used in the present invention, and Fig. 3 is a diagram showing the specific compound order 6. Explanation of the operation when the alertness is detected - Figure 4 shows the solo mountain climbing II of the present invention? FIG. 5 is a detailed block diagram of the antecedent unit shown in FIG. 4, FIG. 6 is a detailed block diagram of the address generation means shown in FIG. 5, and FIG. Each memory access system (memory access within one means)
Detailed diagram of the 1tilJ control circuit, Figure 8 shows the 1tilJ control circuit.
FIG. 2 is a detailed block diagram of one unit of memory access control circuit. 1...3 additional labor profit, 2...base register, 3
. . . index register, 4 . . . preceding control unit, 5 . . . 1. tX system wholesale unit, 6... Input/output device, 7... Performance x 1 Figure 2 Figure 3 Figure 4-B Figure 5 Figure 5 Second port 7 Figure 2''2 1v stop

Claims (1)

[Claims] 1. Programs are stored in the software area of the main memory.
In addition, in the information processing device, the hardware area stores a sequence of instruction execution procedures to be executed when processing a specific compound instruction or when a specific event occurs. When executing a column, the main storage is accessed in the first or second access mode selected according to the base field;
In the above access mode, access is made using the real address, and at the same time, memory protection is prohibited, and access to the software area is also prohibited, and in the above second access mode, the interrupt that passes control to the above instruction execution sequence is An information processing method characterized by accessing according to the mode of the immediately preceding program state word and prohibiting access to a hardware area.