JPH02138623A - Microprocessor for microprogram system with pointer register - Google Patents

Abstract

PURPOSE:To realize the common use of a microprogram that is designated by each general-purpose register and to shorten the access time to a microprogram store means by designating each general-purpose register with the bit information stored in a pointer register means. CONSTITUTION:The bit information is calculated from the address of a control space address map designated by the address of a machine word instruction via an ALU 7. Then the bit information is set at a pointer register 10 so that a specific register can be designated out of a general-purpose register group 8. In other words, an access is possible to a specific general-purpose register just by designating in common only the group 8 in a selecting X2 field without designating individually each general-purpose register in a designating X3 field for microinstruction in a microinstruction register 4. As a result, a microprogram for designation of general-pourpose registers is reduced and the access time is shortened to a microprogram store part.

Description

[Detailed Description of the Invention] [Objective of the Invention] (Industrial Application Field) The present invention relates to a microprocessor based on a microprogram control system, and particularly to a microprocessor in which a desired register among a group of general-purpose registers is directly designated by a microinstruction. The invention relates to a microprocessor with at least an accessible pointer register.

(Prior Art) Generally, in a microprocessor, a control space is constructed by allocating predetermined addresses to various control registers, general-purpose registers, etc., and associating these addresses with each register. It is used to store and read information.

Recently, a computer operating system called "TRON" has been proposed, and various microprocessors have been developed in connection with it.

Regarding these TRON systems and microprocessors, see, for example, "Tron Project 1987" by K. Sakamuko, Open Architecture Computer Systems, SprLnglr-Verlag To
kyo 1987 (page 291)
-308).

FIG. 4 shows the internal configuration of a conventional microprocessor. FIG. 5A is an overall address map showing typical addresses and register groups constituting the control space employed in the TRON system.

FIG. 5B is an address map expressed in hexadecimal notation assigned to each register of the general purpose register group. 5th A
As is clear from the figure and FIG. 5B, it can be seen that an extremely large number of addresses in the control space are used.

In the conventional microprocessor shown in FIG. 4, when data is stored in or read from the general-purpose register 8 in the control space specified by a machine language instruction, 15 addresses in general-purpose registers in control space For example, H' 01
84. H' 018C is sequentially compared, and when a match occurs, the program branches to a program that accesses a designated register, such as RO or R1.

In FIG. 4, 5 and 6 are operand registers for temporarily holding operands, 7 is an arithmetic unit, and 9 is a gate.

Desired registers RO to R14 of the general-purpose register group 8 constituting the control space in the conventional microprocessor described above
The access operation will be described in detail with reference to the flowchart in FIG.

For example, when reading the contents of a specific register in the general-purpose register group 8, the results of decoding a machine language instruction by the instruction decoder 1 are stored in the microinstruction storage section 2, and then read and stored in the microinstruction register 4. put in. Then, specify the general-purpose register group 8 in the selection field X2 of the microinstruction, specify a specific register of the register group 8, for example, R4 in FIG. action,
That is, in this case, register R in general-purpose register group 8
4 and transfers it to an external memory (not shown) via the data bus L-BUS.

That is, in the flowchart of FIG.
At T-1, the address src of the source operand of the STC microinstruction is compared with the address "H0184" expressed in hexadecimal notation of the first register RO of the general-purpose register group 8 shown in FIG. 5B. In this comparison, if it matches H'0184 (ST-2), the contents of the second register R1 are read out and transferred to an external memory (not shown) via the L-BUS (ST-3). If no in step 5T-2, step 5T-4
Then, srC is similarly compared with the address "H'018C" of the second register R1. If this src matches this address "H'018C" (S
T-5), in step 5T-6, the contents of the second register R1 are read out and transferred to the external memory via the L-BUS.

If the result in step 5T-5 is NO, the address "H'0194" of the next register R2 is further compared with src. Such comparison operations are performed sequentially to search for matching addresses.

(Problem to be Solved by the Invention) Therefore, as is clear from the series of address accessing operations described above, if the specific register is the 15th register R14, the above address operation is performed 15 times. There is a problem in that the number of steps in the search program increases because it is necessary to perform the search operation repeatedly.

Furthermore, there is a problem in that a large number of microprograms are required to retrieve the contents of registers at matching addresses, and processing work is required.

The present invention was made to solve the above problems,
The purpose of this is to provide a pointer register that can specify each register in a group of general-purpose registers, and instead of specifying each general-purpose register using a microprogram, the control space address map address specified by the address of a machine language instruction can be used to It is an object of the present invention to provide a microprocessor that can calculate bit information that can specify a register and set it in the pointer register.

[Structure of the invention]

(Means for Solving the Problems) In order to solve the above problems, the present invention specifies a control space address that specifies a microinstruction and a plurality of registers in a general-purpose register group in a microprocessor using a microprogram control method. decoding means for decoding an instruction to obtain address data; address register means for temporarily storing the address data from the decoding means; and address register means for temporarily storing the decoded instruction from the decoding means. means for decoding the general-purpose register group; arithmetic means for calculating address data stored in the address register means to obtain bit information of address data for specifying a specific register in the general-purpose register group; and pointer register means for temporarily storing bit information in order to access the specific register in response to the bit information from the arithmetic means while being specified in response to the specified instruction. shall be.

(Operation) Therefore, in the present invention, each general-purpose register is specified by the bit information in the pointer register means, so the microinstruction only needs to specify the entire general-purpose register group, and the microprogram for specifying each general-purpose register is This can be shared, and the time required to access the microprogram storage means can also be shortened.

(Embodiment) FIG. 1 shows the configuration of a microprocessor 100 equipped with a pointer register embodying the present invention.

In the microprocessor 100 shown in FIG. 1, 1 is an instruction decoder that decodes machine language instructions, 2 is a microinstruction storage section, 3 is an address register, 4 is a microinstruction register, and 5 and 6 are operands that temporarily store operands. Registers, 7 is the arithmetic unit, 8 is a group of general-purpose registers,
Reference numeral 9 indicates a first gate, and reference numeral 10 indicates a pointer register that temporarily stores bit information calculated from the address of a machine language instruction.

12 indicates a second gate. This second gate 12 controls the control field XI of the microinstruction register 4 to control whether or not to output the contents of a specific register of the general-purpose register group 8 accessed by the pointer register 10 to the data bus. Run under control.

A feature of the present invention is that a so-called "pointer register 0" is newly adopted.Here, the function of this new pointer register will be defined.

By setting the bit information calculated by the ALU 7 from the address of the control space address map specified by the address of the machine language instruction in the pointer register 10, a specific register in the general-purpose register group 8 can be specified. ing.

In other words, instead of specifying each general-purpose register individually in the microinstruction specification X3 field in the microinstruction register 4, you can specify a specific general-purpose register by commonly specifying only the general-purpose register group 8 in the selection X2 field. This function allows access to registers.

Next, the operation of the microprocessor 100 shown in FIG. 1 will be explained while also referring to the flowchart shown in FIG.

The machine language instruction decoded by the instruction decoder 1 shown in FIG. 1 is stored in the microinstruction storage section 2, while its address is temporarily stored in the address register 3.

The microinstruction read from the microinstruction storage section 2 is stored in the microinstruction register 4, which includes a control field XI that specifies the operation to be processed, a selection field X2 that collectively specifies the general-purpose register group 8, and a microinstruction field X2 in the microprocessor 100. Each control is performed by the X3 field which specifies each of the other registers.

The contents of the address register 3 (address data) that specifies the address of the control space address map are set by the microprogram to the ALU by predetermined bits, in this example, 3 bits.
7, the bit-shifted address data is transferred to the pointer register 10 via the data bus L-BUS.
The specific general-purpose register for the operation designated by the next microinstruction is accessed via gate 9 (step 5-1). Address of the source operand of this STC microinstruction s
The operation of shifting rc to the right by 3 bits in ALU 7 will be described in detail.

FIG. 3 shows binary code addresses for two of the hexadecimal addresses H'0184 to H'01F4 of the general registers RO to R14 described above. These binary code addresses are
Supplied from U7 head address register 3, shifted to the right by 3 bits, and then transferred to pointer register 10.
and stored at - time (step 5-2). Shifting the binary code address to the right by 3 bits counting from the LSB means truncating 3 bits of address bit information. That is, the bit information is unnecessary for accessing a desired register. Of the binary code address information shifted by 3 bits in this way, the bit information of 4 bits starting from the new LSB is the bit information necessary to access the desired register. According to the present invention, a desired register can be directly accessed by the pointer register 10 by using this 4-bit information.

The contents obtained by accessing the desired register in this way are read out to the L-BUS by opening the second gate 12 and transferred to an external memory (not shown) in accordance with a command from the control register X1 (step 5-3). ).

〔Effect of the invention〕

As detailed above, the microprocessor 1 of this embodiment
According to 00, a desired register can be accessed with extremely fewer access steps than the conventional method of accessing a desired register in a group of general-purpose registers (see the flowchart in FIG. 6).

Therefore, according to the present invention, even if a specific register in the general-purpose register group 8 is not specified by a microinstruction, it can be specified by the pointer register 10, so that a predetermined general-purpose address can be accessed without searching for an address in the control space. There are advantages.

Further, according to the present invention, since each general-purpose register is specified by bit information in the pointer register, the microinstruction only needs to specify the entire general-purpose register group.
This has the advantage that the microprogram for specifying each general-purpose register can be shortened and the time required to access the microprogram storage section can also be shortened.

Therefore, the number of program steps can be significantly reduced and the processing speed can be increased.

Furthermore, being able to reduce the number of program steps means that the macro instruction storage section can be used more effectively.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of a first embodiment of a microprocessor according to the present invention, FIG. 2 is a flowchart showing a register addressing method of the microprocessor shown in FIG. 1, and FIG. Figure 4 is a block diagram of a conventional microprocessor; Figures 5A and 5B are address maps of the control space in the microprocessor shown in Figure 4. FIG. 6 shows a flowchart showing a register addressing method in the microprocessor shown in FIG. 1... Instruction decoder 2... Micro instruction storage unit 3... Address register 4... Micro instruction register 5.6... Operand register 7... Arithmetic unit 9... First gate 10. ...Pointer register 12...Second gate

Claims (1)

[Claims] In a microprocessor using a microprogram control system, decoding means decodes an instruction to obtain a microinstruction and address data specifying a control space address specifying a plurality of registers in a general-purpose register group;
address register means for temporarily storing address data from said decoding means; means for temporarily storing decoded instructions from said decoding means; and designating a particular register in a general purpose register group. arithmetic means for calculating address data stored in said address register means in order to obtain bit information of address data for said address register means; 1. A microprogram control microprocessor equipped with a pointer register, comprising pointer register means for temporarily storing bit information in order to access the specific register in response to bit information from the register.