JPS6218937B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a microprogram control system having a plurality of processing levels, and particularly to a microprogram control system that enables high-speed interrupt processing. Conventionally, a circuit for controlling a certain device has been realized using a microprogram method. It is well known that in this case, the processing speed is slower than when the same function is implemented using wire logic. Therefore, when microprogram processing is applied to control computers or their peripheral devices that require particularly high-speed processing, low processing performance has been a problem. Furthermore, in this microprogram method, a microprogram that processes sequentially at one level is used from the viewpoint of program simplification and restrictions on the amount of hardware. Therefore, there was a problem that sufficient processing performance could not be obtained.

In recent years, LSIs with interrupt level control functions for use in multilevel processing of microprograms have become available.
etc. have also been developed and commercialized, but these have the following drawbacks. In these interrupt processing methods, first, when a high-level interrupt occurs in a currently executing program and the interrupt is accepted, the executing program is interrupted and the cause of the interrupt is read and determined. Next, the start address of the corresponding process is set as the execution address of the microprogram to be jumped, and the corresponding interrupt process is entered. In this method, each time an interrupt occurs, the cause of the interrupt is determined and the jump destination is determined, so it takes a processing time equivalent to two steps in program processing, which is different from the one-level processing described above. Similarly, there is a problem of low processing performance. The following methods can be considered to solve the above problem. In other words, a program level control circuit is added to the conventional microprogram address control circuit, and the execution timing of the microprogram is used as is for the interrupt processing timing to determine interrupt acceptance, level conversion, and interrupt processing start. This is a method of reading addresses and performing these operations in parallel with the processing of the microprogram itself. Here, the following problems occur. Normally, in order to prevent the microprogram being executed from accepting other high-level interrupts, a mask register is provided and control is performed by setting the corresponding bit (mask bit) in this register. . However,
This method requires processing to set and reset the mask bits, which requires extra processing time for the original processing. Furthermore, when controlling registers that are commonly used at a plurality of levels, a problem arises in that processing performance deteriorates. For example, when controlling a memory address register, consider a case where a low-level program sets an address in the register and then jumps the interrupt to a high level before accessing the memory. In the interrupt processing, if the process returns to the original level after memory access processing, when the memory access processing is executed at a lower level, the contents of the address register have changed and the correct memory address is returned. will no longer be able to access it. Therefore, as described above, it is necessary to set and reset the mask bits of the mask register every time a memory is accessed at a low level, which greatly reduces processing performance.

SUMMARY OF THE INVENTION It is an object of the present invention to provide a multi-level microprogram control method that overcomes the drawbacks of the prior art described above and achieves high-speed interrupt processing.

The main point of the present invention is that in a microprogram control method for controlling a conventional interrupt control circuit that can execute interrupt processing and program execution in parallel,
One mask bit is added to each microprogram instruction, and each step of the program is
This bit can be controlled independently, and by setting this bit, the step can be placed in an interrupt-disabled state. Hereinafter, the present invention will be explained in detail with reference to Examples. FIG. 1 is a block diagram showing an example of a conventional microprogram control device to which the present invention is applied. From the microprogram memory (ROM) 2, the address control unit (ROMAR)
The contents are read out according to the address given from 4 and set in the program register (PR) 3. The output of PR3 appears on the control bus (CTLBUS) and the arithmetic circuit (μ-P)1
The register address, data, or instruction decoder (DEC) 5 is applied to μ-P1. Furthermore, the CTLBUS is provided in a control circuit (details will be described later) for controlling equipment including this control device. Used to specify the setting and clearing of various flip-flops and registers. The input bus (INBUS) carries the contents of an external source register (not shown), and μ-P1 uses it to process data. The processing result of μ-P1 is output to the output bus (OUTBUS),
External destination register (not shown)
given to. Also, ROMAR4 normally updates the built-in program counter (not shown) by 1, but when executing a jump instruction etc.
Import and use the contents of CTLBUS or OUTBUS.

Since the microprogram control system has lower processing performance than wire logic, it executes one step and the next step at the same time.
In FIG. 1, execution of one step begins from the beginning of the clock. In other words, at the rising edge of the clock, the ROM that had been read up to that point
The contents of step 2 are set in PR3, output on CTLBUS, and execution of step 1 begins. On the other hand, the ROMAR 4 updates the address with the rising edge of the clock and starts reading the contents of the next step from the ROM 2. The interrupt control circuit in the present invention is
It controls ROMAR4. Of these, the circuit diagram of the level control section and the clock used therein are shown in FIGS. 2 and 3, respectively.

Various interrupt requests from the outside are stored in interrupt register (INTLATCH) 6, and this register 6
is triggered by the clock TP2 input to the T terminal. Here, when a certain interrupt occurs, at the rising edge of clock TP2, the output of register 6 becomes
It is given to the priority encoder (PE) 7. The output of PE7 is provided via line 7A to an interrupt-only jump address register (not shown) and is further sent via CTLBUS to ROMAR4 for use in determining its output. At the same time, the output of this PE 7 is given to the level division circuit 15. This division circuit 15 can be constructed only from gates, and selects whether to set both two output bits to 1 or to set only the lower bit to 1 in response to various interrupt requests. On the other hand, the program level that has been executed up to that point is indicated in the lower two bits of the level register (LEVEL REG) 10, and a comparator (COMP) 8 determines whether or not the interrupt request is accepted. this
For COMP8, the output of the dividing circuit 15 is LEVEL REG
When the output is larger than the output of 10, it outputs "1", and when it is smaller, it outputs "0". For example, if the currently executing program level is (0, 0) and the level of the interrupt request is (0, 1), the output of COMP8 will be "1", indicating that the interrupt request is accepted, and this output will indicate that the interrupt request is accepted. At the next rising edge of clock TP1, flip-flop (F/F) 11 is set, and gates 13 and 14 turn on clock TP.
LEVEL REG10 is triggered at the rising edge of 3. On the other hand, the 4-bit selector (SEL) 9 outputs the A side input when the selection signal (S) input is "0", and outputs the B side input when it is "1". , F/F11 are set, so the S input is "1", and the lower bit of LEVEL REG10 is divided into the upper 2 bits.The level of the interrupt request given from the dividing circuit 15 is set as the lower 2 bits.
It will be given to the input of REG10. Therefore,
After inputting the clock TP3, the output of the LEVEL REG10 has the upper two bits (0,0) and the lower two bits (0,1), indicating that the execution level has moved from (0,0) to (0,1). become. Thereafter, when the clock TP1 rises, the output of COMP8 indicates "0", so the F/F 11 is reset. On the other hand, for ROMAR4, F/F11
By controlling the contents of the jump address register to be selected as the output of ROMAR 4 when is set, it is possible to jump to the interrupt destination (the circuit is not shown for this purpose).

Next, in the interrupt processing microprogram, when a return instruction is issued, this return instruction is input to the gate 13 via the CTLBUS, and the return instruction is input to the gate 14 via the CTLBUS.
The bird is entered into LEVEL REG10 as before via . On the other hand, in this case, F/F11 is cleared by clock TP1, so the S input is "0", and SEL9 is the A side input, that is, the upper 2
Select the bit (0,0), the lower 2 bits select the level (0,0) that was saved before, and select LEVEL REG.
Give to 10 inputs. Therefore, when the RETURN command is issued, all outputs of LEVEL10 become 0, and the program level returns to (0, 0). level (1, 1) while level (0, 1) is running.
FIG. 3 shows a time chart in which exactly the same operation is performed when step 1) is interrupted. FIG. 3a shows a time chart when interrupt processing is accepted, and FIG. 3b shows a time chart when processing a return command. FIG. 4 shows an interrupt control circuit in which an interrupt mask bit according to the present invention is added within a microprogram. In this figure, elements with the same numbers or symbols as in FIG. 2 refer to the same elements as in FIG. This circuit is similar to the circuit shown in Figure 2.
LOMP8 is a 3-bit structure comparator (COMP)8'
and the most significant bit on the interrupt source side is always “0”.
and input the mask bit field output input via CTLBUS to the most significant bit on the opposite side. This mask bit field is provided in each microprogram and is input via the CTLBUS when the microprogram is read out to PR3 by the circuit shown in FIG.
The comparator 8' outputs "1" when the input on the LEVEL REG 10 side is smaller than the input on the dividing circuit 15 side, and outputs "0" otherwise. According to this circuit, even if an interrupt occurs and is set in the interrupt register 6, if the mask bit is set in the mask bit field of the microprogram at that time, the output of the comparator 8' will not be output. The interrupt processing shown in FIG. 3 does not work, and the interrupt is forced to wait until the mask bit falls in the next instruction. As a result, interrupt mask control can be performed independently for each step of the microprogram, and processing performance can be greatly improved.

According to the present invention, in addition to being able to perform interrupt processing and program execution in parallel, it is also possible to specify interrupt prohibition using a simple circuit without spending additional processing time.

[Brief explanation of the drawing]

Fig. 1 is a block diagram of a microprogram control device to which the present invention is applied, Fig. 2 is a conventional interrupt control circuit diagram to which the present invention is applied, and Fig. 3 is a program level transition for the circuit of Fig. 2. FIG. 4 is a time chart showing the interrupt control circuit according to the present invention. 1... Arithmetic circuit, 2... Micro program memory, 3... Program register, 4... Address control section, 5... Instruction decoder, 6... Interrupt register, 8... Comparator, 8'... Comparator .

Claims (1)

[Claims] 1. A program memory that stores a microprogram, an address control means that controls the read address of the memory, a register that latches a 1-step instruction to be executed, an arithmetic circuit that performs various operations depending on the contents of the program, and an execution means for storing the level of the program therein; means for storing the level of the input interrupt request; interrupt control means for comparing the outputs of the two storage means and controlling execution of the interrupt request; In a microprogram control circuit consisting of a clock generation circuit, a field for storing a mask bit for inhibiting all interrupts is provided in each 1-step instruction, and the mask bit storage field in the 1-step instruction read into the register is used for the interrupt control. the interrupt control means outputs a signal for inhibiting execution of the input interrupt when a mask bit for inhibiting the interrupt is stored in the input mask bit storage field; A microprogram control system characterized by a similar structure.