JPS60108973A - Method for finding the minimum value of array elements and element number of the minimum element - Google Patents

Abstract

PURPOSE:To reduce the number of steps of a program by finding out the minimum value of array elements and the element No. of the minimum element only by one instruction. CONSTITUTION:Data read out from a main storage device 1 are set in registers 4, 5. A comparator 6 compares the contents of the registers 4, 5, and if a data value inputted to the register 5 is smaller than a data value inputted to the register 4, a signal line 108 is turned to ''1''. A selector is controlled so as to select the contents of a signal line 104. Consequently, the contents of the register 5 are transferred to the register 4 and the contents of a register 8 are transferred to a register 9. Hereafter, similar operation is repeated. The contents of the register 4 are transferred to a register 11 and the contents of the register 9 are transferred to a register 12. Thus, the contents of the register 11 is the minimum value of n elements and the contents of the register 12 are equal to the element number.

Description

TECHNICAL FIELD The present invention relates to a method for determining the minimum value of array elements and the element number of the minimum element of array data stored in the main memory of an information processing system.

Prior Art Conventionally, array data is often handled in scientific and technical calculations. Operations on array data often involve repeating the same operation on each element. In conventional information processing systems, this reversal is achieved by looping a specific sequence of instructions using a branch instruction. , the disadvantage is that the execution time is not faster because extra instructions such as branch instructions are required. One way to eliminate this drawback is to use instructions that specialize in array data, so-called vector instructions. This vector instruction performs an operation on one array in one instruction, and there is also no need to wait for a branch instruction for loop control or confirmation of an index register, so the operation can be performed at high speed. Among operations on array data, operations that calculate the minimum value of the elements of array data or the element number of the minimum element are also often used. For example, when executing the problem ``In two arrays A and B with the same number of elements, replace the element with the minimum value of array A with the corresponding element of array B'', use the element number of the minimum element. It is necessary to There are also cases where the minimum value of the array elements itself is required. However, conventional vector instructions cannot simultaneously set the minimum value of an array element and the element number of the minimum element, resulting in the following drawbacks. In other words, the above-mentioned "element replacement" operation cannot be performed with an instruction that only calculates the minimum value. Since the minimum value itself is not fitted with the instruction to only read the element number of the largest element, it is necessary to read the corresponding element from the main memory based on the minimum value itself or, if necessary, the fitted element number.

OBJECTS OF THE INVENTION An object of the present invention is to provide a method for calculating the minimum value of array elements and the element number of the minimum element using one instruction in order to solve the above-mentioned drawbacks.

Structure of the Invention The method of calculating the minimum value of an array element and the element number of the minimum element according to the present invention uses an operation code field that specifies the Pji class of the operation, an address specification field and element that specifies the address of the first element of the array. An array element is read from the main memory according to the instruction word having an inter-element distance specification field that specifies the distance between the elements, and an element count specification field that specifies the number n of elements to be operated on, and the first of the read array elements ( The minimum value of the elements up to i2112+n) is stored in the first holding means, the element number of the element having the minimum value is stored in the second holding means, and the contents of the first holding means are stored. Compare the (i+1)th element with i
+1)th element has a smaller value, stores that value in the first holding means, stores the element number of the (i+1)th element in the second holding means, and stores the element number of the (i+1)th element in the second holding means;
When the comparison up to the th element is completed, the contents of the first holding means are stored in the first register, and the contents of the second holding means are stored in the first register.
This consists of a procedure for storing the contents of the holding means in the second register.

Next, an embodiment of the present invention will be described with reference to the drawings. Referring to FIG. 1, an information processing apparatus embodying the method of the present invention includes a main storage device 1, a memory buffer unit 2. Selector 3. Registers 4 and 5. Comparison circuit 6. Control unit 7° registers 8 and 9. ANDGATE 10. Registers 11 and 12. and selector 13
It consists of The main storage device 1 stores programs and data. When data is written into the main memory 1 via signal #101, the contents are read out via signal line 102. The memory buffer unit 2 is a unit that performs read access and write access to the main memory device 1. The data read from the main memory device 1 is stored in the memory buffer unit 2. Signal line 103. #1 is transferred to the register 4 via the selector 3, or directly transferred to the register 5 via the signal 8103. and outputs the result to the signal line 108. That is, when the value stored in the register 5 is smaller than the value stored in the register 4, the signal line 108 becomes "1". The control unit 7
is a unit for controlling the circuit of FIG. 1 according to the method according to the present invention. Referring to FIG. 4, the control unit 7 includes an instruction preemption control circuit 701. Order preemption Shibat 7 702. First instruction register 7031 second instruction register 704. Index register file 705, selectors 706 and 707. Effective address adder 708
．． Effective address register 709°Base address register 710. Base address adder 711. Virtual address register 712. Microaddress control circuit 713. Control memory 714° microinstruction register 715. It has an element number register 716 and a zero detection circuit 717.

This control unit 7 performs the following operations. In response to an instruction preemption request sent from the instruction preemption control circuit 701 to the memory buffer unit 2 via the signal line 116, the control unit 7 The instruction word is read out via the instruction buffer 702 and stored in the instruction prefetch buffer 702. Instruction words to be processed are sequentially read from the instruction pre-fetcher 702. If the read instruction is an instruction of the present invention, the first word of the instruction is stored in the first instruction register 703.
Second instruction register 704 is set with the second word of the instruction. The effective address of the first element of the array data can be obtained by adding the values of the index registers specified by the (f[(t) and MP fields of the instruction word Sofield.There are a total of 8 index registers. , are stored in the index register file 705.

Further, generation of an effective address is performed by an effective address adder 708. The generated effective address is stored in the effective address register 709. The contents of the effective address register 709 are added to the contents of the base address register 710 by a base address adder 711 and stored in the virtual address register 712. The contents of virtual address register 712 are sent to memory buffer unit 2 by signal line 118. After address conversion is performed in the memory buffer unit 2, the address is used as a read address of an array element. Generation of read addresses for the second and subsequent elements is accomplished by adding the value of the Vl field of the instruction word to the address of the previous element. This addition is performed by effective address adder 708, and switching of its input is performed by selector 706 and selector 707.

On the other hand, the OF field of the first instruction register 703 is sent to the microaddress control circuit 713.

The micro-address control circuit 713 generates the start address of the micro-instruction in accordance with the operation code, reads out the micro-instruction from the control memory 714, and sets it in the micro-instruction register 715. Subsequent reading of the microinstruction is performed based on the information in the branch control field of the microinstruction. Second instruction register 7040
The number of elements of the array data is stored in the index register specified by the RN field, and the value is set in the number of elements register 716. Element number register 716
The value is counted down by 1 each time the processing of one element is completed, and becomes zero when the processing of all elements is completed. This is used by the zero detection circuit 717, sent to the microaddress control circuit 713, and becomes a branch condition for the microinstruction.

The contents of the register 8 are incremented by "1" according to instructions from the control unit 7. The output of the register 8 is set in the register 9 according to instructions from the control unit 7. The register 4 is connected to the register 11.
The contents of the register 9 are set in the register 12. The contents of the registers 11 and 12 are obtained by the selector 13 and written to the main memory 1 via the memory buffer unit 2.

'The processing operations for determining the minimum value and minimum element of the array data stored in the main storage device 1 according to the method of the present invention are shown in the flowchart of FIG. 2, and are performed in the following order. be exposed.

When a request for discarding an instruction is output from the control unit 7 to the memory buffer unit 2 via the signal line 116, the command word of the instruction to be executed is read from the main memory 1 and sent to the memory buffer unit 2 and the signal line. 117 to the control unit 7. The control unit 7 decodes the extracted command word. Now, consider the case where the extracted instruction word indicates an instruction to find the minimum value and minimum element of an array element using the method of the present invention. This instruction word has a length of 2 words (=72 bits) and has a format as shown in FIG.

In FIG. 3, UP is an operation code field that specifies the type of operation. Y is an address field for specifying the first address of the array element, and the address modification specified by the address modification field MP is passed to the value of address field Y as #1,
The resulting value represents the start address of the element. ~
■! It specifies the difference in addresses between elements that match each other, that is, the distance between elements, and RN specifies the register in which the number of elements is stored. When this instruction is decoded by the control unit 7, the address of the first element is first calculated, and the first element is read from the address resulting from the calculation. Reading of the leading element is performed from the main memory device 1 via the memory buffer unit 2 in the same manner as reading of the command word. The read data is set in register 4 and register 5 via signal interrupter 103. At this time selector 3
is controlled by the content of signal #105, and selects the content of signal line 103. Element number is "0"
Since the first element is set in registers 4 and 5, register 8 is cleared to "0", and thereafter is counted up by "1" each time an element is read out. The address of the second element (element number "1") is obtained by adding the inter-element distance to the first element G address.

The second element is read from the address of main memory 1 thus obtained and set in register 5. At this time, register 4 is controlled as follows. In other words, the contents of register 4 and register 5 are compared in comparison circuit 6, and if the value of data in register 5 is smaller, signal line 108 becomes rlJ. Also, selector 3 selects signal line 104, that is, register 5. It is controlled to select the contents of 5. When the second element is set to register 5, the signal line to6 (the set signal of register 5) becomes "1", but at this time, the signal line 107 also becomes "1".
1”. The contents of the signal line 107 and the contents of the signal line 10B are ANDed by the AND gate 10, and when the output signal line 109 becomes 11'', the contents of the register 5 are stored in the register 4. At the same time, the contents of register 8 are transferred to register 9. Similarly, the third to nth elements are read out in order, and the above-described processing is repeated. In this way, finally register 4
The value stored in is the most lJS of n element values.
The value stored in the J register 9 is equal to the element number starting from "0" of the element having the minimum value. The contents of register 4 are further transferred to register 11, and register 9
The contents of are transferred to the register 12, and this instruction ends.

The contents of register 11 and register 12 are transferred to signal line 115.
The data is transferred to the memory buffer unit 2 through the memory buffer unit 2 and can be written to the main memory 1 or used by other instructions.

Effects of the Invention The present invention has the effect that the minimum value of an array element and the element number of the minimum element can be determined with one instruction, thereby reducing the number of steps in a program.16 Therefore, processing can be performed at high speed. .

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an embodiment of the present invention, FIG. 2 is a flowchart showing the operation of the circuit shown in FIG. 1, and FIG. 3 is a format of a command word for instructing the operation shown in FIG. 2. and FIG. 4 are diagrams showing a detailed configuration of the control unit 7 in FIG. 4. In FIGS. 1 to 4, 1...main storage device, 2
...Memory Huffer Unit), 3.13...
...Selector, 4, 5, 8, 9.11.12...
・Register, 6... Comparison circuit, 7... Control unit, 10... AND gate, 701...
...Instruction prefetch control circuit, 702...Instruction prefetch completion, 703...First instruction register, 7
04...Second instruction register, 7o5...
・Index register 7 completed, 706.707...
... Selector, 708 ... Effective address adder, 709 ... Effective address register, 710 ...
Base address register, 711 Base address adder, 712...Virtual address register, 713...
... Micro address control circuit, 714 ... Control memory, 715 ... Micro instruction register, 71
6...Element number register, 717...Zero detection circuit. Noon 1 Figure early 2 Figure 3

Claims (1)

[Claims] A method for calculating the minimum value of array elements in which each element is given an element number, and the element number of the minimum element, comprising an operation code field that specifies the type of operation and an array. An array element is extracted from the main memory according to an instruction word that has an address specification field that specifies the address of the first element of , an inter-element distance specification field that specifies the distance between elements, and a number-of-elements specification field that specifies the number n of elements to be operated on. The first step is to read out the minimum value of the elements up to the i-th (i=1.2...+n) of the read array elements, and store the minimum value in the first holding means. a second step of storing the element number of the element having in the second holding means; a step M3 of comparing the contents of the first holding means with the (j+1)th element; a fourth step of storing the smaller value in the first holding means and storing the element number of the (i+1)th element in the second holding means; When the comparison up to the element is completed, the first
an array element characterized by comprising: a fifth step of storing the contents of the holding means in the first register; and a sixth step of storing the contents of the second holding means in the second register. How to calculate the minimum value of and the element number of the minimum element.