JPS5823993B2 - Video signal playback device - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION As shown in FIG. 1, when a video signal is recorded on a magnetic tape by forming diagonal tracks TV, an absolute address is assigned to each frame of the video signal, and this absolute address is code and extend the code signal in the longitudinal direction of the tape.
That is, recording is performed on an auxiliary track TQ parallel to the audio track TA and the control track TC.

Note that the figure shows a case where one track Ty is formed for one field of the video signal.

A specific example of this is SMPTE time code1. As shown in Figure 2, one frame has 80 bits, so the bit frequency is 2.4kHz, and this 80-bit Of these, 32 bits are used as a time code, 32 bits are used as free bits for the user, and 16 bits are used as a sync word.

The 32-bit time code is composed of a frame code, a second code, a minute code, and an hour code, and is designed to indicate the hour, minute, and second frame.
Each is divided into two parts of 4 bits each, with 4 user bits inserted between each part.

The 16-bit sync word indicates whether the tape is running in the forward direction and therefore this SMPTE time code signal is read in the direction indicated by arrow F, or the tape is running in the reverse direction and therefore this SMPTE time code signal is read out in the direction indicated by arrow F. The time code is set so that it can be determined whether the time code is being read out in the direction indicated by arrow R, and the time code can be read out without error when traveling in any direction.

Note that this code signal is a so-called pie-phase signal in which information of "1" and "0" is expressed as shown in the figure.

In this way, the track TQ extending in the longitudinal direction of the tape
In addition, it is convenient when editing a tape to record a signal indicating the absolute address of each frame of the video signal.

On the other hand, as shown with diagonal lines in FIG. 3, it is also conceivable to record a code signal Sc indicating the absolute address of this track TV in track 2 of the video signal.

In this case, as shown in the figure, this signal SC is inserted and recorded in both the odd and even fields of each frame.

Specifically, as shown with diagonal lines in FIG.
It is inserted into the video section after the burst signal sB in a predetermined horizontal section excluding the vertical synchronizing pulse section TVP and the equalization pulse section TEP within the vertical retrace period.

This code signal is, for example, 80 bits like the SMPTE time code signal in FIG. 2, and its bit frequency is f.
For example, B is the color subcarrier frequency fsc horizontal frequency fH,
If the vertical frequency is fy, then there is a relationship as follows.Therefore, when fy, then 80 bits easily fit within the video section of the horizontal section.

Of the 80 bits, 32 bits are time code and 3
Two bits are used as user bits, and 16 bits are used as a sync word.

The arrangement relationship between time code and user bits is S in Figure 2.
It may be the same as that of the MPTE time code signal, and the same time code is inserted in the odd and even fields of the same frame.

The sync word comes at the beginning, that is, immediately after the burst signal sB.

The position of the head of this sync word, ie, the start position of the code signal, is always set at a constant time Ts from the horizontal periodic pulse PH.

Note that this code signal is "1".

The information on "O" may be expressed in different levels as shown in the figure. For example, "O" is the pedicle level, "1" is the level of 50 IRE units or more, Each can be as shown.

The SMPTE time code signal recorded on the track TQ extending in the longitudinal direction of the tape has the disadvantage that it cannot be read out in the case of slow or still motion playback, but the SMPTE time code signal recorded on the track T-y of the video signal If the above-mentioned code signal SC is used, it can be read even in slow motion or still motion playback.

In view of this point, the present invention reads out the SMPTE time code signal from the track TQ when the tape speed is set to the same normal speed as during recording or a certain range of speeds before and after that, and the SMPTE time code signal is read out from the track TQ, When the tape speed is slow or the tape stops, as in the case of still motion playback, the code signal inserted into the video signal as described above is read out from the track TV.

FIG. 5 shows an example of its configuration, in which a video signal to be recorded from an input terminal 1 is supplied to a code signal forming/inserting circuit 2, and a code signal SC is input to one output terminal of the circuit 2 as described above.
is inserted, the SMPTE time code signal shown in FIG. The latter is recorded as a diagonal track Ty, and the latter is supplied to the fixed head HQ via the recording side contact R of the switch 5 and recorded as a trunk TQ extending in the longitudinal direction.

During playback, the playback video signals from the heads HA and HB are supplied to the playback circuit 6 via the playback side contact P of the switch 3 and led out to the output terminal 7, and the playback video signals are sent to the first readout circuit. 8 to read the code signal SC from the track Ty, and on the other hand, the reproduction output of the head HQ is supplied to the second readout circuit 9 via the reproduction side contact P of the switch 5 to read the SMPTE time code from the trunk TQ. Read out the signal.

Then, the reproduction output of the head HQ is supplied to the tape speed detection circuit 10 to detect the tape speed from the SMPTE time code signal, and the detection output is used to connect the switch 11 to the contact S.
When the tape speed is at the same normal speed as during recording or within a certain range around it,
SMPTE from trunk TQ from readout circuit 9
When the tape speed is slower than this, the readout output of the time code signal is sent to the track TV from the readout circuit 8.
The readout outputs of the code signals SC are respectively taken out and supplied to the display device 12 to display the absolute address of the track Ty.

Note that it is conceivable to use control pulses recorded on the tape 4 to detect the tape speed.

For example, as shown in FIG. 6, a control pulse from a control head HC is supplied to a tape speed detection circuit 10, and the tape speed is detected from the frequency of the control pulse.

However, this detection method is not very advisable.

This is because when using an absolute address signal, the frequency of the absolute address signal obtained from the head HQ is higher than that of the control pulse signal, so even when the tape speed is slow, it is possible to accurately detect the tape speed. For,
This is because when a control pulse signal is used, the reproduction frequency becomes extremely low, making it difficult to accurately detect the tape speed.

Furthermore, when using the SMPTE time code signal as in the present invention, a part of the reading circuit 9 can also be used as a means for detecting the tape speed. In this case, it is impossible to use a part of the reading circuit 9 as the tape speed detection circuit 10, which has the disadvantage of complicating the circuit configuration and requiring a lead wire from the head HC to the detection circuit 10. There is a hassle of having to move around.

FIG. 7 shows an example of the code signal forming and inserting circuit 2 described above.

21 is an input terminal for a video signal to be recorded, and the video signal is supplied to a synthesizer 22.

The video signal is also supplied to a synchronization signal separation circuit 23 to extract a composite synchronization signal including an equalization pulse, which is supplied to a frame pulse formation circuit 24 to form a frame pulse, and which is output from a variable frequency oscillator 25. The frame pulse and the frequency-divided signal from the counter 26 are phase-compared in the phase comparator circuit 27, and the oscillator 25 is controlled by the comparison error voltage. The frequency of the frequency-divided signal from is set as the frame frequency.

The counter 26 also provides pulses with frequencies 80 times and 80×2 times the frame frequency.

The output of this counter 26 is then supplied to a sync word pulse generation circuit 28 to obtain a sync word pulse in the section that should be the sync word position in one frame, and this is supplied to a time calculator 29 to generate a sync word pulse. Time calculations are performed at the beginning of the section that should be the position.

And this time calculation output is stored in two memories 30 and 31.
supplied to

Memories 30 and 31 are also supplied with user bit input from terminal 32.

Then, the output of the counter 26 is supplied to the memory 31, a code signal is read out from the memory 31, and this is supplied to the phase modulation circuit 33, and the output of the counter 26 is supplied to the phase modulation circuit 33, S recorded on the above-mentioned track TQ, which is made into a pie-phase signal.
An MPTE time code signal is obtained.

On the other hand, the composite synchronization signal from the synchronization signal separation circuit 23 is supplied to the monostable multi-bi break 34 to obtain the horizontal synchronization pulse excluding the equalization pulse, and the variable frequency oscillator 35
The horizontal synchronizing pulse and the frequency-divided signal from the frequency divider 36 are phase-compared in the frequency divider 36, and the oscillator 35 is controlled by the comparison error voltage, so that the oscillation frequency of the oscillator 35 becomes 455 times fH, that is, 2fsc, and the frequency of the divided signal from the frequency divider 36 is fH.

Then, it is synchronized with the horizontal synchronizing pulse from another output terminal of the frequency divider 36.

FIG. 8 shows a specific example of this frequency divider 36.
Consisting of a decimal counter 38 and a NAND circuit 39, a pulse with a frequency of 2fsc from an oscillator 35 is supplied to the counter 38, which is divided in frequency as shown in FIG. 10, and the outputs of the lower 3 bits and upper 3 bits are When it becomes "1",
That is, when a pulse with a frequency of 2fsc is counted 455 times, the output of the NAND circuit 39 becomes "0" and the counter 3
8 is reset.

Therefore, it becomes the lower number pulse of the counter 38.

This pulse with a frequency of fB is supplied to the gate circuit 40, and on the other hand, the composite synchronization signal from the synchronization signal separation circuit 23 is supplied to the vertical synchronization signal separation circuit 41 to extract the vertical synchronization signal, which is combined with the horizontal synchronization pulse. The gate pulse is supplied to a gate pulse forming circuit 42, and the gate pulse obtained therefrom is supplied to a gate circuit 40, from which a pulse having a frequency of fB is extracted only in a predetermined horizontal interval within the vertical retrace interval.

The extracted pulses are then supplied to the memory 30 to read out a code signal as shown in FIG. is obtained.

FIG. 9 is an example of the above-mentioned first readout circuit 8 that reads out the inserted code signal SC from this video signal.

51 is an input terminal for a reproduced video signal, and this reproduced video signal is supplied to a clamp circuit 52.

The reproduced video signal is also supplied to a synchronization signal separation circuit 53 to extract a composite synchronization signal, which is supplied to a monostable multi-by-break 54 to obtain horizontal synchronization pulses excluding equalization pulses, which are sent to a phase synchronization circuit called a PLL 55. A pulse synchronized with the horizontal sync pulse is obtained,
This is supplied to a clamp pulse forming circuit 56 to form a clamp pulse for pedestally clamping the reproduced video signal, and this clamp pulse is supplied to the clamp circuit 52 to pedestally clamp the reproduced video signal.

This clamped reproduced video signal is supplied to a code signal separation circuit 57 and compared with a level higher than the pedestal level, thereby separating the above-mentioned inserted code signal, which is then supplied to a gate circuit 58.

The clamped reproduced video signal is also sent to the synchronization signal separation circuit 5.
9 to extract the composite synchronizing signal, which is supplied to the vertical synchronizing signal separation circuit 60 to extract the vertical synchronizing signal, and the composite synchronizing signal and the vertical synchronizing signal are supplied to the gate pulse forming circuit 61, from which the composite synchronizing signal is extracted. A gate pulse is supplied to the gate circuit 58, from which the code signal inserted in the above-mentioned predetermined horizontal interval is extracted.

This code signal is supplied to memory 62.

On the other hand, the composite synchronization signal (first
1 A) is supplied to the monostable multi-bi break 63 to form a narrow pulse (B in the same figure), which is then supplied to the gate circuit 64 to generate a pulse from the PLL 55 (C in the same figure).
The signal from the variable frequency oscillator 65 is gated by the gate circuit 64 to extract a narrow pulse with a horizontal frequency fH (D in the same figure), and the signal from the variable frequency oscillator 65 is sent to a comparator circuit 67 between the horizontal frequency fH pulse from the gate circuit 64 and the frequency divider 66. The phases of the frequency-divided signals from
sc, and the frequency of the divided signal from the frequency divider 66 is fH.
It is said that

This frequency divider 66 is constructed as shown in FIG. 8 in the same way as the frequency divider 36 described above, and receives the horizontal synchronizing pulse from its other output terminal.

This clock pulse with a frequency of fB is supplied to a timing pulse generation circuit 68, and is also supplied to a gate pulse formation circuit 6.
A pulse indicating that this is the horizontal section in which the above-mentioned code signal from 1 is present is supplied to the timing pulse generation circuit 68, which gives a timing pulse for 80 bits to the memory 62. A code signal consisting of bits is written into memory 62.

When writing in one horizontal section is completed, a pulse indicating that writing has been completed is sent from the timing pulse generation circuit 68, and another timing pulse generation circuit 69 is activated.
A timing pulse is obtained which is supplied to the memory 62 to read out the code signal.

The read code signal is sent to the 4-bit shift register 7.
The 4-bit output of this shift register 70 is supplied to the memory 71, and written into it by the timing pulse from the timing pulse generation circuit 69. 4 to 71 different addresses
The code signal written bit by bit and read out from the memory 71 is supplied to the display device 12 through the switch 11 as described above, and the absolute address of the track Ty is
That is, the hour, minute, second, and number of the frame is displayed.

As described above, according to the present invention, the SMPTE time code signal recorded on the track TQ extending in the longitudinal direction of the tape and the time code signal recorded on the magnetic track TV of the video signal are selected according to the speed of the tape. Since the absolute address of the track T-y of the video signal can be known with certainty no matter what the tape speed is, this is extremely convenient for editing and the like.

In this invention, the SMP recorded on the track TQ
Since the tape speed is detected from the TE time code signal, not only the circuit configuration can be simplified, but also the tape speed can be detected accurately at all times.

[Brief explanation of the drawing]

FIG. 1 is a diagram showing an example of a recording pattern of a tape on which an SMPTE time code signal is recorded, FIG. 2 is a diagram showing the state of an SMPTE time code signal, and FIG. 3 is an example of a recording pattern of a magnetic tape used in the present invention. 4 is a diagram showing an example of a signal indicating an absolute address inserted into the video signal, FIG. 5 is a system diagram of an example of a device according to the present invention, and FIG. 6 is an explanation of the present invention. FIG. 7 is a system diagram of an example of a circuit for forming and inserting a signal indicating an absolute address, FIG. 8 is a system diagram of a specific example of a part of the circuit, and FIG. FIGS. 10 and 11 are waveform diagrams for explaining an example of a system diagram of a readout circuit for a signal indicating an absolute address recorded on a track. 1 is a video signal input terminal, 2 is a code signal forming and inserting circuit,
4 is a magnetic tape, 8 and 9 are first and second reading circuits, 10 is a tape speed detection circuit, and 12 is a display device.

Claims (1)

[Claims] 1. A video signal is recorded as one diagonal track per one field or one frame, and a signal indicating the absolute address of this diagonal track is recorded at a predetermined position in the diagonal track and in the longitudinal direction of the magnetic track. a first reading circuit for reading a signal indicating an absolute address recorded in the diagonal track from a magnetic tape recorded at a position corresponding to the diagonal track of the extending track; and a track extending in the longitudinal direction. a second reading circuit for reading out a signal indicating an absolute address recorded on the magnetic tape; and a circuit for obtaining a signal corresponding to the running speed of the magnetic tape from the absolute address signal recorded on a track extending in the longitudinal direction of the magnetic track. , a video signal reproducing device provided with a switching circuit that switches between the first and second readout circuits according to the output of the circuit.