JPH04129485A - Still picture signal output device - Google Patents

Abstract

PURPOSE:To obtain a still picture with high quality without deterioration in the resolution in the vertical direction of the screen and uneven movement by detecting the movement in one frame period and outputting a video signal by one frame of a picture having no substantial movement repetitively from the start of the frame. CONSTITUTION:A delay circuit 11 delays an input video signal by one frame. A movement detection circuit 12 takes a difference between the input video signal and an output delay video signal of the delay circuit 11, compares the difference with a prescribed value and detects the presence of the movement of the picture of the input video signal for a frame period. An output discrimination circuit 13 includes a frame memory and outputs selectively the output delay video signal of the delay circuit 11 when a detection signal representing no movement is applied from the movement detection circuit 12. Thus, a still picture without movement is obtained from the start of the frame and the optimum still picture is obtained without deterioration in the resolution in the vertical direction like a field still picture.

Description

[Detailed Description of the Invention] [Summary] Regarding a device that outputs a still image signal, the purpose of which is to output a still image signal of good image quality, the device includes a delay circuit that delays an input video signal by one frame, and a delay circuit that delays an input video signal by one frame. a motion detection circuit that calculates the difference between the output delayed video signal of the input video signal and the output delayed video signal of the delay circuit, and compares the difference value with a predetermined value to detect the presence or absence of movement of the image of the input video signal in a frame period; and a frame memory. and when a detection signal indicating no motion is supplied from the motion detection circuit, switches and outputs the output delayed video signal of the delay circuit,
and an output determination circuit that stores the delayed video signal in the frame memory and then repeatedly outputs the delayed video signal stored in the frame memory.

[Industrial application field]

The present invention relates to a device that outputs still image signals.

In recent years, image output devices are increasingly required to have higher functionality and higher image quality, and still image signals obtained by playing back still images from video signals recorded on recording media are also required to have higher image quality. or required.

[Conventional technology]

VT traditionally records video signals on magnetic tape and plays them back.
2. Description of the Related Art Disk recording and reproducing apparatuses that record and reproduce R and video signals on disks (magnetic disks, optical disks, etc.) are widely known. It is well known that in such VTRs and disc recording and reproducing apparatuses, still image signals are output by repeatedly reproducing the same track.

In a helical scan VTR, a video signal is recorded and played back by a rotary head one field at a time on a video track that is inclined with respect to the longitudinal direction (travel direction) of the magnetic tape, but when playing still images, the running of the magnetic tape is stop, 1
Video signals of a book or two adjacent tracks are reproduced by a rotating head.

In this case, by reproducing the recorded video signal of one track, a still image signal consisting only of the same field can be obtained (this is called a field still), and on the other hand, the recorded video signal of two adjacent tracks can be obtained. It is well known that by alternately reproducing each field, video signals of adjacent fields or still image signals arranged alternately for each field can be obtained (this is called a frame still). . Similarly, in the case of a disk recording/reproducing device, for example, a spiral track has two
When a video signal of a field (that is, one frame) is recorded, a still image signal based on the frame still can be obtained by repeatedly reproducing one track, and the video signal reproduced during a half-rotation period of the disk is electrically converted. If the circuit means is used to repeatedly output the signal, a still image signal based on a field still image can be obtained.

[Problem to be solved by the invention]

However, conventionally, only field still or frame still is performed regardless of the video content, so while it is possible to obtain a still image without blur with a device that only performs field still, on the other hand, still images are figure(
As schematically shown in B), for example, only the information of the scanning lines of odd fields is displayed, and the image information of one screen is thinned out by half and reproduced in two fields, so the resolution in the vertical direction of the screen is reduced to 172. do.

On the other hand, in a device that only performs frame still, the system shown in Fig. 5 (
As schematically shown in A), in order to reproduce all the image information for one screen using the odd field scanning lines shown as solid lines and the even field scanning lines shown as broken lines, the vertical resolution in the case of the above field still is However, on the other hand, when playing a still image of a fast-moving moving image in which there is a portion that moves within one frame period, a still image is obtained in which that portion is blurred, making it unsightly.

The present invention has been made in view of the above points, and an object of the present invention is to provide a still image signal output device that can output a still image signal of good image quality.

[Means to solve the problem]

FIG. 1 shows a basic configuration diagram of the present invention. In the figure, 11 is a delay circuit that delays the input video signal by one frame. Reference numeral 12 denotes a motion detection circuit which calculates the difference between the input video signal and the output delayed video signal of the delay circuit 11, and compares the difference value with a predetermined value to determine whether or not there is movement in the image of the input video signal in a frame period. To detect.

Reference numeral 13 denotes an output determination circuit which includes a frame memory, and when a detection signal indicating no motion is supplied from the motion detection circuit 12, it switches and outputs the output delayed video signal of the delay circuit 11 and stores it in the frame memory. Then, the delayed video signal stored in the frame memory is repeatedly output.

[Effect]

In the present invention, after the motion detection circuit 12 supplies the detection signal indicating no motion to the output determination circuit 13, the delayed video signal of one frame at that time is repeatedly output. Here, since the motion detection circuit 12 performs the detection operation at frame intervals, the switching point of the output video signal of the output determination circuit 13 is performed in synchronization with the beginning of the frame, and the same l frame with almost no motion is detected. Since the video signal is repeatedly output, the output determination circuit 13 outputs a frame still image with little or no movement.

〔Example〕

FIG. 2 shows a block diagram of one embodiment of the invention. In the figure, the same components as those in FIG. In FIG. 2, a composite video signal from a magnetic tape, optical disk, magnetic disk, or other video source is supplied to a decoder 21, where the synchronization signal and the video signal (video section signal) are removed by known means.
It is separated into Among the separated synchronization signals, the vertical synchronization signal is applied as a reference clock to the delay circuit 11 and a comparator 24, which will be described later.

On the other hand, the separated video signals are input to the subtraction circuit 22 and the delay circuit 11, respectively. The subtraction circuit 22 constitutes the motion detection circuit 12, together with an integration circuit 23 and a comparator 24, which will be described later. The subtraction circuit 22 subtracts the input video signal of the delay circuit 11 and the delayed video signal delayed by one frame period in the delay circuit 11 to obtain a difference value between the two signals, which is converted into one frame by the integration circuit 23. Integrate over.

The difference value (subtraction result) smoothed by the integrating circuit 23 is compared in magnitude by a comparator 24 with a threshold value set in advance to distinguish whether there is movement in the image. If the image of the input video signal has a movement more than a predetermined value, the difference value becomes a large value greater than the threshold value, so the comparator 24
At this time, outputs a motion detection signal of "L" level. On the other hand, when the image has no movement less than a predetermined value, the difference value becomes a small value less than the threshold value, and the comparator 24 outputs a motion detection signal of "H" level at this time. Note that the comparator 24 is configured to perform a comparison operation at a frame period in synchronization with every other vertical synchronization signal, and to hold the comparison result until the next frame comparison operation. The point in time when the output motion detection signal of the detector 24 changes from "H" level to "L" level or from "L" l/bell to "H" level is always the beginning of a frame.

The output motion detection signal of the comparator 24 is input to the output determination circuit 13 together with the delayed video signal and still command signal from the delay circuit 11, and a still image signal is output.

FIG. 3 shows a circuit diagram of an embodiment of the output determination circuit 13.

In the figure, 31 is a D-type flip-flop, a still command signal is input to a clock terminal, and a trigger pulse from a trigger pulse generation circuit 32 is input to a clear terminal. The trigger pulse generation circuit 32 is configured to receive the comparison judgment output (motion detection signal) from the comparator 24, differentiate it, and output a pulse synchronized with a rising edge. Reference numeral 33 denotes an output control unit which has a built-in frame memory for storing the video signal for one frame, and outputs one of the delayed video signal from the delay circuit 11 and the video signal stored in the built-in frame memory to the flip-flop 3.
Selective output is performed based on the Q output signal (still flag) of 1.

Next, the operation of this output determination circuit 13 and the second embodiment will be described. Assuming that the comparator 24 inputs the comparison judgment output (motion detection signal) shown in FIG. It is taken out in phase synchronization with the rising edge of the motion detection signal, and the flip-flop 31 is set in a clear state.

On the other hand, a still command signal as shown in FIG. 4(B) is input to the clock terminal of the flip-flop 31 at an arbitrary timing according to the user's intention. When the still command signal is input, the flip-flop 31 outputs an "H" level signal from its Q output terminal until the pulse is input. Therefore, a signal as shown in FIG. 4(C) is taken out from the Q output terminal of the flip-flop 31 and inputted to the output control section 33 as a still flag.

The output control unit 33 receives a delayed video signal schematically shown in FIG. 4(E) obtained by delaying the input video signal schematically shown in frame units in FIG. 4(D) by one frame in the delay circuit 11. At the falling edge of the still flag from the D flip-flop 31 (indicated by j+ and is in FIG. 4), the input delayed video signal is outputted through and writing to the built-in frame memory begins, and then at the falling edge of the still flag. When one frame has elapsed from this point, the delayed video signal that has been written for one frame into the built-in frame memory starts to be selectively output in place of the input video signal. Thereafter, the output control section 33 repeatedly outputs the stored delayed video signal of the built-in frame memory until the still flag falls.

Therefore, as schematically shown in FIG. 4(F), the output control unit 33 outputs a delayed video signal of the same frame (in the example of FIG. 4, a delayed video signal of the 3rd frame or 8th frame) from the falling point of the still flag. A frame still image signal obtained by chronologically synthesizing the signals) is extracted. As can be seen from Figure 4, this still image signal switches in phase synchronization with the falling edge of the still flag, that is, the beginning of the frame, and the delayed video signal that switches is an image signal with no or almost no movement. In this example, it is possible to obtain a still image with no blur (or virtually negligible) from the beginning of the frame, and since it is a frame still image, it has a vertical resolution similar to that of a field still image. Optimal still images can be obtained without any deterioration.

〔Effect of the invention〕

As described above, according to the present invention, motion within one frame period is detected and the video signal for one frame of an image with substantially no motion is repeatedly output from the beginning of the frame. It is possible to obtain high-quality still images with no deterioration in resolution in the vertical direction of the screen and no blur in movement.
In addition, since the input video signal can be a normally reproduced video signal, good still images can be obtained without being affected by S/N deterioration or jitter that occurs when playing still images. It has the following.

[Brief explanation of the drawing]

Fig. 1 is a diagram showing the principle of the present invention; Fig. 2 is a block diagram of an embodiment of the invention; Fig. 3 is a block diagram of an embodiment of the output determination circuit; Fig. 4 is for explaining the operation of the embodiment. The time chart, FIG. 5, is a comparative explanatory diagram of frame still and field still. In the figure, 11 is a delay circuit, 12 is a motion detection circuit, I3 is an output determination circuit, 22 is a subtraction circuit, 23 is an integration circuit, and 24 is a comparator. Time chart for explaining the operation of the time example (A) Comparison diagram of frame still and fee (B) Rudo still

Claims (3)

[Claims] (1) Delay circuit that delays the input video signal by one frame (1
1), and calculates the difference between the input video signal and the output delayed video signal of the delay circuit (11), and compares the difference value with a predetermined value to determine whether or not there is movement in the image of the input video signal. The motion detection circuit (12) is configured to include a motion detection circuit (12) that detects periodically, and a frame memory.
2) When a detection signal indicating no movement is supplied from the delay circuit (11), the output delayed video signal of the delay circuit (11) is switched and outputted, and is stored in the frame memory, and the delayed video signal stored in the frame memory is then repeatedly output. 1. A still image signal output device comprising: an output determination circuit (13). (2) the output determination circuit (13) is cleared in synchronization with the leading edge of the output detection signal of the motion detection circuit (12);
A flip-flop (31) is set in synchronization with the still command signal, and when the output signal is input when the flip-flop (31) is cleared, the output delayed video signal of the delay circuit (11) is outputted, and the delayed video signal is outputted from the delay circuit (11). An output control section (33) stores the signal in an internal frame memory, and after outputting the delayed video signal, continuously reads and outputs the video signal stored in the frame memory until the next flip-flop (31) is cleared. ) The still image signal output device according to claim 1, characterized in that it has a still image signal output device. (3) The motion detection circuit (12) includes a subtraction circuit (22) that subtracts the input video signal and the output delayed video signal of the delay circuit (11), and an output signal of the subtraction circuit (22). an integrating circuit (23) for integrating;
) and the threshold value of the predetermined value at a frame period, and outputs a logical value detection signal according to the comparison result. 1. The still image signal output device according to 1.