JPS5818035B2 - TV channel channel - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a channel display device for a television receiver, and more particularly to a channel display device for displaying channel numbers on a picture tube screen for an appropriate time after channel switching.

In conventional television receivers, channel numbers are generally displayed by rotating a channel display board in conjunction with the rotation of a channel knob.

However, due to the structure of conventional channel display devices, it is not possible to make the individual channel numbers too large.
Even if it could be made larger, there is a risk that it would end up being unsightly.Moreover, recently there are television receivers on the market that switch channels by remote control, especially in such television summer receivers. ,
In a receiver, channel switching can be performed at a considerable distance from the receiver, but in this case the channel numbers are difficult to see.

In view of the above, the present invention provides a channel display device that projects the number of the receiving channel on the picture tube screen for a short time every time the channel is changed.

The present invention will be explained below with reference to the drawings.

FIG. 1 is a basic block diagram of the present invention, where 1
is an antenna, 2 is a tuner circuit, 3 is a tuning device, 4 is an intermediate frequency amplification circuit, 5 is a video detection circuit, 6 is a video amplification circuit, 7 is a picture tube, 8 is an audio intermediate frequency amplification circuit, 9 is an audio Detection circuit, 10 is an audio amplification circuit, 11 is a speaker, 12
13 is a synchronization separation circuit, 13 is a vertical oscillation circuit, 14 is a vertical deflection circuit, 15 is a horizontal oscillation circuit, and 16 is a horizontal deflection circuit, and these constitute a normal television receiver circuit.

In particular, the present invention further adds a signal synthesis switching circuit 17, a display time setting circuit 18, a selection circuit 19, and a character generation circuit 20 to such a television receiver circuit. When this is done, based on the signal from the selection circuit 19, the character generation circuit 20 generates a numeric signal (
or a character signal), and supplies the character signal to the picture tube 7 in place of the video signal from the video amplification circuit 6 for a predetermined period of time after channel switching in the signal synthesis switching circuit 17, or superimposes it on the video signal. By supplying the composite signal to the picture tube T, the characters (including numbers) of the receiving channel are displayed on the picture tube T for a short time after channel switching.

Here, the display time setting circuit 18 of the channel arbitrarily sets the display time.

Next, each of the above circuits according to the present invention will be explained in detail one by one.

. First, the display time setting circuit 18 will be explained.
When the channel is switched, the circuit 18 generates a composite signal in which a channel character signal (including a numeric signal) is superimposed on a video signal for a short period of time (for example, about 065 seconds) from the moment of channel switching. A signal synthesis switching circuit 17 so that the character signal or the character signal is supplied to the picture tube 1 alone.
This circuit 18 includes transistors 21, 22, resistors 23, 24,
, 25° 26, capacitors 27, 28, etc., and a one-shot circuit in which a diode 29, a resistor 30, and a capacitor 31 are added to the usual monostable multivibrator circuit.

When a positive pulse signal is supplied to the input terminal 32 of such a one-shot circuit every time the channel is switched as shown in FIG. 4a, the output terminal 33 outputs a high level for a fixed time T1 after switching. A rectangular wave signal similar to the one shown below can be obtained.

Note that the certain time TI is determined by the product RICI of the resistance value R1 of the resistor 24 and the capacitance value C1 of the capacitor 27.

Therefore, character signals can be superimposed or switched in the signal synthesis switching circuit 17 based on the rectangular wave signal obtained in this way.

Hereinafter, this rectangular wave signal will be referred to as a display command pulse.

The pulse time TI of this display command pulse becomes the character display time.

By the way, when the display time setting circuit 18 is configured with a conventional general one-shot circuit as shown in FIG. 2 mentioned above, the character display time T1 is particularly short as shown in FIG. 4C. When switching channels at time intervals, the circuit 18 does not respond to all channel switching pulses, and now only responds to the HchLch3tic 115 pulse to determine the display time.

Therefore, at this time, the display time when switching between ch2 and ch4 is extremely short, and from ch2 to ch3 and from ch4 to ch5.
Regardless of the channel switching time interval to ch
2 and channel 7 characters of ch4 instantly disappear from the picture tube screen.

The present invention has been made especially in view of this point, and FIG. 3 shows one embodiment of a display time setting circuit used in the channel display device of the present invention.
, 35, resistors 36, 37, 38゜39, 40, 41. A charging/discharging circuit consisting of a transistor 42, a capacitor 43, and a resistor 44 is added to the input circuit of a normal Schmitt trigger circuit, and the channel can be switched. A negative pulse is supplied from the OR gate ν45 to the transistor 420 through the resistor 46 at each time.

That is, the input terminals of the OR gate 45 are provided in the number corresponding to each channel of television broadcasting, and the positive voltage Vcc is applied to the input terminals via a switch 41 which is switched in conjunction with channel switching. It is configured.

Therefore, when a specific channel is currently being received, a positive voltage (1Vcc in this case) is applied to the specific input terminal of the OR gate 45 via the slider of the switch 47.
At this time, the output terminal 0 of the OR gate 45 is at a high positive potential.

However, when the channel is changed, the switch 41
The moment the slider moves from one input terminal of the OR gate 45 to the next input terminal, the slider becomes open, so the potential of the output terminal (2) of the OR gate 45 momentarily becomes a low potential.

Therefore, when the channel is switched, a negative pulse signal as shown in FIG. 4e is obtained from the output terminal (2) of the OR gate 45.

A negative pulse signal is supplied to the base of this waste transistor 42 via a resistor 46 to the channel switching terminal, and during this pulse period, the transistor 42 is conductive and a collector current flows.

In this way, each time the transistor 42 becomes conductive, the capacitor 43 is charged to approximately the power supply voltage Vcc, and the charge in the capacitor 43 is discharged through the resistor 44 during the cut-off period of the transistor 42.

Note that the charge in the capacitor 43 is also discharged through the transistor 34 and resistors 37 and 38 of the Schmitt circuit, but the amount of discharge is small and the discharge time constant is mainly due to the resistor 4.
4 and capacitor 43.

The collector voltage of the transistor 42 at this time, ie, the voltage waveform at the 0 point, is shown in FIG. 4f.

In this way, the transistor 42, the capacitor 43, the resistor 44
A charging/discharging voltage as shown in FIG. 4(f) of a charging/discharging circuit according to the above is applied to the base of a transistor 34 constituting a Schmitt circuit.

In this Schmitt circuit, when a voltage higher than a certain value vth is applied to the base of the transistor 34, the transistor 34 becomes conductive, while the transistor 35 is cut off, and when the base voltage of the transistor 340 falls below a certain value vth, the transistor 34 becomes conductive. , transistor 34 is cut off, and transistor 35 is turned on.

Therefore, when a voltage as shown in FIG. 4f is applied to the base of the transistor 34, a rectangular wave voltage as shown in FIG. 4g is obtained from the collector of the transistor 35, that is, the output terminal 2 of the Schmitt circuit.

That is, for a certain period of time (T2 in this case) after channel switching, the output voltage of terminal (2) is always at a high level.

Note that the length of this fixed time T2 is determined by the capacitor 43 and the resistor 4.
4.

As described above, if the embodiment shown in FIG. 3 is used as the channel display time setting circuit according to the present invention, even if channel switching is performed far compared to this fixed time T2, Channel display follows this channel switching, and the channel display time of certain channels (ch2 and ch4 in the above example) does not become extremely short as in the conventional example shown in FIG.

In the embodiment shown in FIG. 3, two resistors 37 and 38 are used as the emitter resistor of the transistor 34.
Generally, the resistor 37 is not used in a general Schmitt circuit.

In order to prevent the discharge time constant of the charging/discharging circuit from being influenced by the Schmitt circuit, it is sufficient to increase the value of the emitter resistance, but simply increasing the value of the resistor 38 causes the output voltage of the Schmitt circuit to decrease. Therefore, a resistor 37 is inserted separately from the resistor 38 to increase the value of the emitter resistance.

Next, the selection circuit 19 and character generation circuit 20 will be explained in detail.

Note that in the embodiment of the character generation circuit described below, VHF
When receiving broadcasts, each channel is a number from 1 to 12, and when receiving UHF broadcasts, each channel is a number from U1 to U8 (however, this U1 to U8
A character signal is created so that it is displayed on the picture tube screen with the characters `` (' is an appropriate correspondence between UHF broadcasting channels that can be received on the receiver side), but this is different from this example. For example, it would be possible to create a character generation circuit that generates signals that display all VHF-UHF channels from 1 to 62.

However, in order to simplify the circuit configuration of the character generation circuit 20 and the like as much as possible, a case will be described here in which numbers 1 to 12 and letters U1 to U8 are displayed.

In this embodiment, the numbers 1 to 12 and the letters U1 to U8 are displayed in the center of the picture tube screen as picture elements A, B, C, etc., as shown in FIG.
・Displayed as a combination of N.

Note that each picture element A, B, C, --N is I, If,
m, IV, V, Vl, VI[(D7-')(
7) Can be defined by a horizontal position and five vertical positions: 1.2, 3, 4.5.

That is, when expressed schematically, A=(I-x), B=(I・4), C=(II・
5).

D=(III・2), E=(III・4), F=(IV
・2).

G=(IV・4), H=(V・1), I=(V・3
).

J=(V・5), K=(■・2), L=(■・4)
.

M=(■・2), N=(VI・4) becomes.

Therefore, in other words, horizontal positions I, III, IV.

Horizontal unit signal that determines v, vi, ■ and vertical position 1°2.
1 to 12 based on the vertical unit signal that determines 3, 4, and 5.
and all channel character signals U1 to U8 can be created.

Therefore, the character signal generation operation by the character generation circuit 20 and the channel selection operation by the selection circuit 19 will be explained based on the specific embodiment shown in FIG.

Here, 47 is a switch that is switched in conjunction with the channel heir, etc. when switching channels, and 48 is a switch that changes the reception channel at the time according to the switching of the switch 47.
,0,0. This is an encoder circuit that converts into a code signal consisting of [F].

The encoder circuit can be constructed of a diode matrix using diodes and resistors, as shown in FIG. 7, for example.

Here, each channel of 1 to 12 and Ul is ■, ■, 0,
It is taken out as a binary encoded signal from the 0 output terminal,
In addition, each channel of U2 to U8 has a signal from the O output terminal and ■, ■.

It is taken out as a combination with the binary encoded signal from the C20 output terminal.

Now write the output codes of the ■, ■, 0, 0.0 terminals for all channels as lr1. When expressed as J, , rOi, it is as shown in Table 1.

Incidentally, a trigger pulse necessary for driving the display time determining circuit 18 at the time of channel switching is also taken out from the diode matrix circuit shown in FIG.

Next, 49 is a decoder circuit that separates and converts the code once encoded in the encoder circuit 48 into restringed channel signals of 1 to 12 and Ul.

Although a specific example of the decoder circuit 49 is not shown here, the circuit 49 can be constructed of a diode matrix like the encoder circuit 48.

In the circuit example of FIG. 6, the encoder circuit 48 and decoder.

The selection circuit 19 in FIG.
In terms of ■, eD, 0.0. The decoder circuit 49 encodes the signal into a channel signal and then restores it to a channel signal again in the decoder circuit 49. This is generally done when the decoder circuit 49 is integrated into a single device including other circuits. Since it is desirable that the number of output terminals be as small as possible, it is once coded in this way.

Here, the input terminals are ■, ■, 0, 0 . All you need is 5 [F].

・Also, 50 is 8 flip-flop circuits FF1°FF
2. ...A counter circuit composed of FF8,
The counter circuit 50 counts horizontal pulse signals obtained from the horizontal oscillation circuit 15 of the television receiver, and the counting state is reset each time a vertical pulse signal arrives from the vertical oscillation circuit 13.

Here, especially the fourth to eighth flip-flop circuits FF4. of the counter circuit 50. FF5...FF8 peak terminal [
F], 0. A rectangular wave signal as shown in FIG. 8 is extracted from ①, ②, and 0.

・ 51 is a vertical unit signal generation circuit composed of a combination of various gate circuits, and this circuit 51 generates 1 and 2 signals based on the rectangular wave signals [F], O20, ■, and CD of the counter circuit 50. , 3, 4, and 5 vertical unit signals are created.

The waveform of each unit signal is shown in FIG.

Here 1. 2. Each unit signal in 3.4.5 is obtained from a logic gate expressed by the following formula.

1=(GHIJ), 2=(GnIJ″ten HIJ).

3=(GHIJ), 4=(IJ), 5=(GHIJ
) Each vertical unit signal thus obtained is located approximately at the center of the vertical scanning period of the television receiver, and this signal serves as a vertical positioning signal for projecting channel letters at the center of the picture tube screen Ω as shown in FIG. becomes.

Reference numeral 52 denotes a pulse oscillator, and the oscillator 52 generates a pulse signal of a sufficiently high frequency, here 230 KC, compared to the horizontal scanning wave number (15.75 KC) of the television receiver.

53 are four flip-flop circuits FF1. FF2゜F
F3. The counter circuit 53 is composed of an FF4, and the counter circuit 53 counts the 230 KC pulse signal generated by the pulse oscillator 52, and the counting state is reset by the horizontal pulse signal of the television receiver.

The input terminal (2) of the counter circuit 53 and each flip-flop circuit FFI, FF2 . FF3. FF4 output terminal [F
]■, [phase], and 0, a rectangular wave signal as shown in FIG. 9 is obtained.

54 is a horizontal unit signal generation circuit constructed by a combination of various gate circuits, similar to the upper=m direct unit signal generation circuit 51, and in this circuit 54, [F] of the counter circuit 53,
, ■, [phase], and 0 based on the rectangular wave signals I, I[,
Horizontal unit signals of III, IV, V, VI, and ■ are created.

The waveform of each unit signal is shown in FIG. 9, and the unit signal is obtained from a logic gate expressed by the following formula.

I=(KLMNO) II=(MNO) II[=(KLMNO) IV=(KLMNO) V=KLMNO+LMNO+LMNO) VI=(KLMNO) ■=(KLMNO) The horizontal unit signal obtained in this way is located approximately at the center of the horizontal scanning period. This signal becomes a horizontal positioning signal for displaying channel letters on the picture tube.

Next, 55 is a pixel signal generation circuit composed of a large number of gates and circuits. Signals 1, 2, 3, 4, 5 and horizontal unit signals I, II.

. . . Based on ■, picture element signals A, B, C, . . . N are created.

Each pixel signal is a combination signal of horizontal direct and direct unit signals, and the contents of this combination are as described above.

56 is also a character signal generation circuit composed of a large number of gate circuits, and in this character signal generation circuit 56, A is obtained from the picture element signal generation circuit 55.

Based on the picture element signals B, C, . . . N, numeric signals 1 to 12 and character signals U1 to U8 are created.

Actually, the generating circuit 56 obtains numeric signals 0 to 9 and 1- and character signals U- and Ul.

These signals are expressed as A, B, C...N as shown in the following equation.
is obtained as an appropriate OR gate output of the pixel signal.

1=F+G 2=H+I+J+G+M 3=H+I+J+M+N 4=F+I++L 5=F+H+IfJ10N 6=F+G+H+I+J+N 7=F+H+M+N; 8=F+G+H+I+J+M+N9=F+H
+I+J+M+N 0=F+G+H+J+M+N 1-=A+B U-=A+B +C+D +E Ul =A+B +C+D 1E +M1N57 is also a character output signal generation circuit composed of a large number of gate circuits, and in this circuit 57, the above-mentioned encoder circuit The U-channel signal obtained from the output terminal [F] of 48, each channel signal of 1 to 12 and U11 channel signal obtained from the decoder circuit 49, and the corresponding channel signal obtained from the character signal generation circuit 56 9.1-, [
The J- and Ul character signals are AND gated, and an appropriate character signal is extracted from the character output signal generating circuit 56.

For example, when a television receiver receives 12 channels, a 12-channel signal is obtained from the decoder circuit 49, and at this time, the character output signal generating circuit 5
7, a character signal generating circuit 56 based on the channel signal.
Only the 1- and 2 character signals obtained from the 1- and 2-character signals are gated and extracted.

Similarly, the 3rd level of UHF broadcasting on a television receiver.
When 4 channels are received (however, this 34 channel is temporarily associated with the U2 channel for display on the receiver side).

) A U-channel signal is obtained from the encoder circuit 48, and a 2-channel signal is obtained from the decoder circuit 49, and at this time, the character output signal generation circuit 57 generates only the U- and 2 character signals based on both channel signals. is gated and extracted.

Reference numeral 58 is an AND gate circuit which gates the character signal thus obtained from the character output signal generation circuit 57 only for a certain period of time after channel switching in accordance with the display command pulse signal obtained from the display time setting circuit 18.

In the embodiment shown in FIG. 6 described above, a counter circuit 50, a vertical unit signal generation circuit 51, a pulse oscillator 52, a counter circuit 53, a horizontal unit signal generation circuit 54, and a pixel signal generation circuit 5 are provided.
5. Character signal generation circuit 56, character output signal generation circuit 57
, and gate circuit 58 constitute the character generation circuit 20.

According to the channel display device of the present invention, each channel character signal is created based on the horizontal pulse signal and vertical pulse signal of the television receiver in the character generation circuit 20 configured as shown in FIG. A specific channel signal corresponding to the receiving channel is created in the channel selection device 3 and the selection circuit 19, a specific character signal is selected and extracted from the character generation circuit 20 based on the channel signal, and the channel The character signal is superimposed on the video signal of the television receiver only for a certain period of time after the channel is switched, or the character signal is supplied to the picture tube 1 independently in place of the video signal, and the picture tube 1 is thus displayed on the picture tube screen after the channel has been switched. It displays the characters of the receiving channel only for a certain period of time.

According to the channel display device according to the embodiment illustrated in FIG. Creating a signal, but in this case television reception.

Regardless of whether there is television broadcasting in the area where the device is installed, in other words, even if the television receiver is set to an empty channel and horizontal and vertical synchronization signals cannot be obtained, the vertical oscillation circuit 13 and horizontal oscillation are activated. The circuit 15 continued its oscillating operation for some time.

Therefore, a channel character signal is always generated in the character generating circuit 20, and therefore, the channel character is displayed on the picture tube screen for a certain period of time even immediately after switching to an empty channel.

According to such a channel display device, even if reception is set to an empty channel, the channel letters will be displayed on the picture tube screen, but in this case, the vertical oscillation circuit 13 and the horizontal oscillation There is a risk that the oscillation frequency of the circuit 15 will fluctuate, causing the font of the channel letters on the picture tube screen to become distorted and unsightly.

In view of this point, the embodiment shown in FIG. 10 detects the presence or absence of a horizontal or vertical synchronizing signal, and if there is no horizontal or vertical synchronizing signal, stops extracting the channel character signal from the character generating circuit 20 and switches to an empty channel. To provide a channel display device configured so that channel letters are not displayed on a picture tube screen when the picture tube screen is turned off.

In particular, only the main parts are shown here, and the same parts as in the embodiment shown in FIG. 6 are given the same reference numerals.

Here, 59 is an R8S flip-flop circuit, and the input terminal S of the flip-flop circuit 590 is supplied with a horizontal synchronization signal obtained from the synchronization separation circuit 12 of the television receiver, and the reset input terminal R is supplied with a vertical oscillation circuit. A vertical oscillation pulse signal obtained from 13 is supplied.

Generally, the logic of the R8S flip-flop circuit 59 is as shown in Table 2.

Therefore, when the channel selection device 3 of the television receiver sets reception to an empty channel, the horizontal synchronizing signal is not supplied to the set input terminal S of the R8S flip-flop circuit 59, so that the circuit 59 only receives the reset input terminal R. It is always in a reset state by the vertical oscillation pulse supplied to the output terminal Q, and the output of the output terminal Q is at a high level, that is, "1".

Therefore, at this time, the output of the OR gate 60 is always "1" regardless of the display command signal supplied from the display time setting circuit 18, and therefore, the output of the OR gate 60 is always "1".
The output of the counter circuits 50 and 5 is always "O", and the output of the counter circuits 50 and 5
3 are both recessed and sorted.

On the other hand, the output of the inverter circuit 63 is always "0", and therefore the output of the AND gate 58 is also "0".

As a result, when the channel is switched to an empty channel, the character signal generation operation in the character generation circuit 20 is stopped and no character signal is obtained from the AND gate 58.

Next time you set reception to a broadcast channel,
A horizontal synchronizing signal is supplied to the set input terminal S of the R8S flip-flop circuit 59, and the output of the output terminal Q is normally "0".
", and the output is reset to "1" each time a vertical oscillation pulse is supplied to the reset input terminal R, but is immediately returned to "0" by the subsequent horizontal synchronization signal.

FIG. 11 shows the output waveforms of each part in the embodiment shown in FIG. 10 in this case.

When the reception is switched so that any result broadcast ≠ channel, a display command pulse of negative polarity is supplied from the display time setting circuit 18 to the OR gate circuit '6 (j) for a certain period of time immediately after this, so that both counter circuits between the temples are 50 and 53 start a counting operation, and the counting state is reset at the vertical oscillation pulse and horizontal oscillation pulse periods, respectively.

Thus, the character generating circuit 20 performs a character signal generating operation.

On the other hand, a character signal is extracted from the AND gate of the gate i character generation circuit 20 during the pulse period of this display command signal.

However, during this period, especially during the vertical oscillation pulse period, the extraction of character signals from the AND gate 58 is stopped.

In the channel display device of the embodiment shown in FIG. 10, only when the reception is switched to the broadcast channel as described above, the channel letters are displayed on the picture tube screen for a certain period of time after the switch is made, and the channel display is blank. When switching to Chachinel, no Chichinnel characters are displayed.

In addition, according to the channel display device of the N embodiments described above, all the channel letters are displayed on the picture tube screen at the fifth position.
It is displayed in a more upright font than shown in the figure.

In the embodiment described below, a channel display device is provided in which channel letters are displayed in a somewhat slanted font as shown in FIG. 12 in order to eliminate unnaturalness and make the channel letters projected on the picture tube screen as easy to see as possible. There are some people who try.

This is the channel display device of the embodiment already described in FIG. A circuit 64 integrates the horizontal pulse signal, and an integrator circuit 65 integrates the vertical pulse signal.

Here, the operation of each of these circuits will be explained with reference to FIG. 13, but in order to make the explanation of the operation easier to understand, a case will be described here taking as an example a case where there are five horizontal scanning lines in one vertical scanning period.

(In actual Japanese television broadcasting, there are 2,625 horizontal scanning lines.

) That is, when the horizontal pulse signal is supplied to the integrating circuit 64, a sawtooth wave signal rising to the right is obtained from the integrating circuit 64.

On the other hand, when a vertical pulse signal is supplied to the integrating circuit 6, a sawtooth wave signal downward to the right is obtained from the integrating circuit 65.

However, the amplitude of the horizontal sawtooth wave signal is set to be approximately twice as large as the amplitude of the vertical sawtooth wave signal.

The comparison circuit 66 compares the horizontal sawtooth wave signals, and each time the horizontal sawtooth signal becomes larger than the vertical sawtooth signal, the output of the comparison circuit 66 becomes a low level.

Immediately after the horizontal pulse period, ie, when the horizontal sawtooth signal is less than the vertical sawtooth signal, the output of the comparator circuit 66 is at a high level.

As a result, a rectangular wave pulse signal of positive polarity synchronized with the horizontal pulse signal is obtained from the comparison path 66, and the pulse signal has a pulse width that gradually becomes shorter during one vertical scanning period.

In this embodiment, the i-wave pulse signal thus generated is used to control the output of the pulse oscillator 52.

Either the Cy<yless oscillator 52 is made to oscillate in response to the falling edge of the square wave pulse signal, or the output signal of the oscillator 52 is constantly oscillated and the output signal of the oscillator 52 is appropriately gated by the square wave pulse signal. do it.

In this way, the actual oscillation operation of the pulse oscillator 52 occurs at the rising edge of the rectangular wave pulse signal (81, 8 in FIG. 13).
2, 83, 84, 85) and stops at the rising edge of the pulse signal, and this start time becomes earlier as the vertical scan progresses.

Therefore, based on the oscillation output of the pulse oscillator 52, the counter operation of the counter circuit 53 and the gate operation of the horizontal unit signal generation circuit 54 as described above are performed.
For example, the horizontal unit signals I, I of the horizontal unit signal generation circuit 54
[, .

As a result, if the channel letters are displayed on the picture tube picture tube based on the channel letter signals generated by the letter generating circuit 20 of this embodiment, all the channel letters will be displayed in the first channel.
As shown in Figure 2, the font is uniformly slanted, making it relatively easy to read.

In addition, in the embodiment shown in FIG. 6, the circuit sections added specifically for creating the slanted character signal, that is, the integration circuits 64 and 65, the comparator circuit 66, and the pulse oscillator 52, are changed to the specific embodiment shown in FIG. Therefore, it will be explained in more detail.

. Here, the integrating circuit 64 includes a transistor 67, a resistor 68 .
69, is composed of a semi-fixed variable resistor 70 and a capacitor 11, and when a positive horizontal pulse signal is supplied to the base of the transistor 7 through the resistor 69, a horizontal sawtooth wave on the upper right side is generated from the collector of the transistor 67. A signal is obtained.

Note that the amplitude of the sawtooth wave signal can be arbitrarily changed by a semi-fixed variable resistor "!0".

Also, is the integration circuit 65 a transistor? 2, 73, resistance 74
, 75, 76, a semi-fixed variable resistor 77, 78, and a capacitor 79. When a negative vertical pulse signal is supplied to the base of the transistor 72 through the resistor 74, the right F from the emitter of the transistor 73 A vertical sawtooth signal is obtained.

The amplitude of the vertical sawtooth signal is set by a semi-fixed variable resistor of 77.78
It can be arbitrarily changed by

In addition, the comparison circuit 66 includes a transistor 80 and a resistor 81.82.
, an inverter circuit 83, the base of the transistor 80 is supplied with a vertical sawtooth wave signal from the integration circuit 65, and the emitter of the transistor 80 is supplied with a horizontal sawtooth signal from the integration circuit 64. be done.

Actually, the emitter of the transistor 80 is connected to the co-receiver of the transistor 7.

In the comparison circuit 66, the transistor 80 is turned on only when the vertical sawtooth voltage exceeds the horizontal sawtooth voltage, and at other times, that is, when the horizontal sawtooth voltage is larger than the vertical sawtooth voltage, the transistor 80 is turned on. is in a non-conducting state.

Therefore, the output of the comparator circuit 66, that is, the output of the inverter circuit 83, is at a high level immediately after the arrival of the horizontal pulse, and then becomes a low level when the vertical sawtooth voltage exceeds the horizontal sawtooth voltage.

That is, a square wave pulse signal is obtained from the comparator circuit 66. It will be done.

The pulse oscillator 52 includes a Nant gate circuit 8485, a capacitor 86.87, a diode 88°89, and a resistor 90.
, 91, and an inverter circuit 92, and the rectangular wave pulse signal is supplied to the Nant gate circuit 84 from the comparison circuit 66 via the inverter circuits 9 and 2.

Therefore, the pulse oscillator 52 oscillates when the falcon wave pulse signal obtained from the comparator circuit 66 becomes a low level output, and stops the oscillation operation when the output is another high level.

Here, the inventor has experimentally determined that the resistors 90 and 91 are both 1.2 KO, and the capacitors 86, 87 and 1 are 1.
When a value of 00OPF is used, the pulse oscillator 5
It was confirmed that the oscillation frequency of 2 was approximately 230 KHz.

In the embodiment shown in FIG. 14, the oscillation operation of the pulse oscillator 52 is intermittently stopped based on the output of the comparator circuit 83, but the oscillator 52 is kept oscillating all the time, and the oscillation output is sent to the comparator circuit. The configuration may be such that the output is gated and taken out when desired based on the output of 66.

In addition, according to the channel display device of the present invention, channel letters are displayed on the picture tube screen for a certain period of time immediately after changing the channel, but if the channel display device of the present invention is applied, it can be used in other ways. It would also be possible to use a touch switch or the like to display channel letters on the screen for a certain period of time immediately after simply touching the channel switching heir.

[Brief explanation of drawings]

FIG. 1 is a block diagram of a television receiver equipped with a channel display device according to the present invention, FIG. 2 is a circuit configuration diagram of a conventional example of a display time setting circuit according to the channel display device of the present invention, and FIG. 4 is a circuit configuration diagram of one embodiment of the display time setting circuit, FIG. 4 is a signal waveform diagram of each part in FIGS. 2 and 3, and FIG. 5 is a diagram showing the signal waveforms displayed on the picture tube screen by the channel display device of the present invention. 6 is a block diagram of one embodiment of the channel display device according to the present invention, FIG. 1 is a circuit diagram of one encoder→° circuit related to the same channel display device, and FIG. , FIG. 9 is a signal waveform diagram for explaining the operation of the vertical unit signal generation circuit in the channel display device of FIG. 6, FIG. 9 is a signal waveform diagram for explaining the operation of the horizontal unit signal generation circuit in the channel display device, and FIG. The figure is a block diagram of the main parts of another embodiment of the channel display device according to the present invention. 11 is a waveform diagram of each part of the channel display device in FIG. 10, FIG. 12 is a diagram showing an example of the font of characters displayed on the picture tube screen by the channel display device of one embodiment of the present invention, and FIG. 13 14 is a signal waveform diagram for explaining the operation of a channel display device equipped with a slanted character generation circuit according to the present invention, and FIG. 14 is a specific circuit configuration diagram of the slanted character generation circuit. 1 is an antenna, 2 is a tuner circuit, 3 is a channel selection device, 4 is an intermediate frequency amplification circuit, 5 is a video detection circuit, 6 is a video amplification circuit, 7 is a picture tube, 8 is an audio intermediate frequency amplification circuit, 9 is a sound image Detection circuit, 10 is an audio amplification circuit, 11 is a speaker, 12
13 is a synchronous separation circuit, 13 is a vertical oscillation circuit, 14 is a vertical deflection circuit, 15 is a horizontal oscillation circuit, 16 is a horizontal deflection circuit, 17
18 is a signal synthesis switching circuit, 18 is a display time setting circuit, 19 is a selection circuit, 20 is a character generation circuit, 34 and 35 are transistors forming a simomit trigger circuit in the display time setting circuit, and 42 is a charging/discharging circuit. Component transistors, 43 are the same capacitors, 44 are the same resistors, 48
49 is an encoder circuit forming a selection circuit; 49 is a decoder circuit; 50 is a counter circuit forming a character generating circuit; 51 is a vertical unit signal generating circuit; 52 is a pulse oscillator; and 53 is a counter circuit. , 54 is the same horizontal unit signal generation circuit, 55 is the same pixel signal generation circuit, 56 is the same character signal generation circuit, 57 is the same character signal output circuit, 58 is the same AND gate circuit, 59 is the horizontal or vertical synchronizing signal. R8S flip-flop circuit for detecting presence, 64
and 65 is an integration circuit constituting a slanted character generation circuit;
66 is a comparison circuit.

Claims (1)

[Claims] 1. In a television receiver, a display time setting circuit that creates a display command pulse signal having a constant pulse time and in synchronization with the switching of the receiving channel in the tuning device; a selection circuit for separating into individual channel signals that can be identified accordingly; and a character generator for generating a channel character signal corresponding to the received channel based on the channel signal from the selection circuit and the horizontal and vertical pulse signals in the television receiver. and a signal synthesis switching circuit that superimposes the channel character signal from the character generation circuit on the video signal of the television receiver or switches the video signal to the channel character signal for a certain period of time after channel switching. ,
A channel display device that displays channel characters on the picture tube screen for a certain period of time after channel switching is equipped with a switching element, a charging capacitor, and a discharging resistor. A one-shot circuit consisting of a charging/discharging circuit that charges a capacitor and a Schmitt trigger circuit that receives the charging/discharging voltage of the charging/discharging circuit and is driven based on the charging/discharging voltage is used for the display time ν setting circuit. A channel display device for a television receiver, characterized in that the channel display time is not too short even when channel switching is performed quickly.