JPS6261191B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a broadcast reception discrimination circuit in a television receiver or the like.

Such a discrimination circuit is necessary in order to stop the automatic search at the reception position during automatic search tuning in the tuning device.

FIG. 1 shows a channel selection device for a television receiver having an auto search channel selection function, in which 1 is a 4-bit microcomputer driven by a keyboard 2, and a PLL channel selection IC 3. Its basic function is to set the tuner 5 to a desired reception state in combination with the band switch circuit 4,
At this time, when the auto-search button on the keyboard 2 is pressed, an auto-search signal is applied from the microcomputer 1 to the tuning IC 3, and the tuning voltage applied from the PLLIC 3 to the tuner 5 through the low-pass filter 6 changes in the up or down direction. When a horizontal synchronizing pulse is obtained from a television circuit (not shown) connected to tuner 5, search control circuit 7 operates to stop the search operation of microcomputer 1. In such a case, the search control circuit 7 must determine whether or not the signal given from the television circuit is a correct signal, that is, it must determine reception. In order to determine reception, not only the output from the horizontal synchronization separation circuit of the television circuit, but also horizontal frequency pulses such as flypack pulses generated by the receiver are provided. Furthermore, apart from such reception determination,
In order to also perform AFT control, the search control circuit 7 includes
An AFT signal is also provided. In addition, in Figure 1, 9
is a channel display means, and 8 is its drive circuit.

By the way, as shown in FIG. 2, the conventional reception discrimination circuit applies the horizontal synchronization pulse _P1 from the synchronization separation circuit to the first terminal 10, and uses the flypack pulse (hereinafter referred to as "horizontal pulse") P generated by the receiver. ₂ to 2nd
In addition to terminal 11, capacitor C ₁ and resistor R ₁
The signals from the first and second terminals 10 and 11 are ANDed by an AND circuit formed by diodes D ₁ and D ₂ , and the AND output is sent to the first comparator 12 via a separate resistor. The waveform is shaped by comparing it with a reference voltage applied from the connection midpoint of R ₂ and R ₃ , and a waveform like A is obtained at the output terminal 13 . This signal is connected to resistors R ₄ , R ₅ and capacitor C ₂ ,
The DC voltage B is converted into DC by an integrating circuit composed of _C3 , and the DC voltage B is compared with a reference voltage separately provided from a volumetric volume 15 by a second comparator 14 to determine reception.

However, in this conventional circuit, when a broadcasting station is not being received, the waveform-shaped output output from the first comparator 12 becomes A' due to the noise N given from the synchronization separation circuit, and its DC conversion output Since the voltage also becomes B' and there is not much difference in level from the DC converted output voltage B during broadcast reception, it is difficult to set the reference voltage of the second comparator 14, which may cause malfunction.

In view of this, it is an object of the present invention to accurately determine the presence or absence of a broadcast station by making the level of the DC voltage input to the second comparator significantly different between the presence of a broadcast station and the absence of a broadcast station.

The following will explain the embodiments shown in the drawings.

FIG. 3 shows the configuration of the present invention in blocks, where 16 is a first comparator that inputs the output voltage of the horizontal sync separation circuit and compares it with a predetermined reference voltage, and 17 is the horizontal A first input pulse that generates a pulse having the same polarity as the horizontal synchronizing pulse appearing at the output of the first comparator 16 and having a smaller peak value than the horizontal synchronizing pulse.
18 is a second means for ORing the output of the comparator and the first means; 19 is an integrating circuit for converting the output of the second means into a DC voltage; and 20 is a reference for predetermining the output of the integrating circuit. This is a second comparator that compares the voltage and outputs a reception determination signal to its output terminal.

Fig. 4 shows a specific example of Fig. 3, in which the output of the horizontal synchronization separation circuit is inputted from terminal 21 to the negative terminal of the first comparator 16 via resistor _R6 , and +12V is applied to the positive terminal of resistor R6. A reference voltage obtained by dividing the voltage with ₇ and R ₈ is applied. First means 17
consists of a PNP transistor whose emitter is connected to a +12V power supply and whose base is connected to the horizontal pulse input terminal 22 via a resistor _R9 , and whose collector is coupled to point F via a resistor _R10 . .
On the other hand, the output terminal of the first comparator 16 is also connected to the resistor R ₁₁
It is connected to point F via. F point is also resistance
It is also the connection midpoint of R ₁₂ and R ₁₃ . Such resistance R ₁₀ ,
The connection of R ₁₁ , R ₁₂ and R ₁₃ to point F forms a second means 18 as an OR circuit. Next, the integrating circuit 19 has a resistor R ₁₄ and a capacitor O ₄ as well as a switching diode D ₄ for increasing the charging time constant and decreasing the discharging time constant. The output of this integrating circuit is applied to the negative terminal of the second comparator 20. The reference voltage applied to the positive terminal of the second comparator 20 is obtained by dividing the +12V power supply voltage by resistors R ₁₅ and R ₁₆ , and its value is set as E ₁ in FIG. 9.

Next, the operation shown in FIG. 4 will be explained with reference to FIGS. 5 to 9.

First, when there is a broadcast station and there is a strong electric field, the horizontal synchronizing pulse input to the terminal 21 is as shown in FIG. 5A. At this time, the output of the first comparator 16 is as shown in FIG. 6A. On the other hand, the PNP transistor 17 is conductive when no horizontal pulse (Fig. 7a) is input to the terminal 22, and maintains the potential at point F at almost +12V, but when a horizontal pulse is input, it is cut off. The potential at point F is resistance
It drops to 6V determined by R ₁₂ and R ₁₃ [Figure 7b] This
When PNP transistor 17 is cut off, the first
When the pulse shown in FIG. 6A is applied from the comparator 16, the low level of this pulse is almost close to the ground level, so the voltage at point F becomes the voltage shown in FIG. 8A.

Next is the broadcast station, but in the case of a weak electric field, terminal 2
The horizontal synchronizing pulse input to 1 is shown in Figure 5B,
The output of the comparator 16 is shown in FIG. 6 (b), and the F point voltage is shown in FIG. 8 (b).

When there is no broadcasting station and there is noise, the input to the first comparator 16 is as shown in FIG. 5C, its output is as shown in FIG. 6C, and the voltage at point F is as shown in FIG. 8C.

When there is no broadcasting station and no noise, the input to the first comparator 16 is as shown in FIG. 5D, its output is as shown in FIG. 6D, and the voltage at point F is as shown in FIG. 8D.

The results of integrating the F point voltage in each of these cases by the integrating circuit 19 are shown in FIG. 9, A, B, C, and D, respectively. As a result, there will be a large level difference in the integral output between A and B when there is a broadcast station (i.e., when the broadcast is received) and C and D when there is no broadcast station (i.e., when the broadcast is not received). It is easy to set the reference voltage of the second comparator 20, and no malfunction occurs in reception discrimination.

The output of the second comparator 20 is output from the connection point between the resistor R ₁₇ connected to the +5V power supply and the output terminal of the second comparator 20 in the form of high level (when receiving broadcasts) and low level (when not receiving broadcasts). terminal 2
3, the microcomputer 1 shown in FIG. 1 is controlled.

As explained above, according to the present invention, it is possible to obtain a large level difference between when a broadcast is received and when it is not received, and it is easy to set the reference voltage of the second comparator, and there is no possibility of malfunction in reception discrimination. It is effective and extremely effective.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an outline of a channel selection device, and FIG. 2 is a circuit diagram showing a conventional reception discrimination circuit. FIG. 3 is a block diagram of the reception discrimination circuit of the present invention, and FIG. 4 is a specific circuit diagram thereof. Figures 5, 6, 7, 8 and 9 are
It is an explanatory waveform chart of a figure. 16...first comparator, 17...first means, 18...second means, 19...integrator circuit, 20
...Second comparator.

Claims (1)

[Claims] 1. A first comparator that inputs the output voltage of the horizontal synchronization separation circuit and compares it with a predetermined reference voltage, and an output of the first comparator that inputs the horizontal frequency pulse generated by the receiver. a first means for generating a pulse having the same polarity as the horizontal synchronizing pulse appearing in the horizontal synchronizing pulse and having a smaller peak value than the horizontal synchronizing pulse; a second means for ORing the output of the comparator and the output of the first means; A reception discrimination circuit comprising: an integrating circuit that smoothes the outputs of the two means; and a second comparator that compares the output of the integrating circuit with a predetermined constant level and outputs a reception discrimination signal to its output terminal. 2. Claim 1, wherein the integrating circuit has a large charging time constant and a small discharging time constant.
Receiving discrimination circuit described in section.