JPS60235592A - Television receiver - Google Patents

Abstract

PURPOSE:To display a reception diveo signal at tuning period by displaying a specific picture data stored in advance in place of the reception video signal in the state of untuning when the automatic tunig is executed. CONSTITUTION:A radio wave received by an antenna 21 is fed to an electronic tuner 22. The electronic tuner 22 selects a desired radio wave in received radio waves, converts it into an intermediate frequency A and the result is outputted to a television linear circuit 23. A control circuit 27 outputs a mute signal MU to a switch circuit 24 and a sound circuit 30 is response to the tuning state of the channel. The switch circuit 24 selects the video signal from the television linear circuit 23 when the level of the mute signal MU is at ''1'' level and selects a picture signal VS from the control circuit 27 when the level od the mute signal MU is logical 0, and gives an output to a liquid crystal drive circuit 25. The liquid crystal drive circuit 25 displays and drives respectively a video display section 12 a channel display section 13 and a sound volume display section 14 on a liquid crystal display panel 15 according to the signal from the switch circuit 24 and the control circuit 27.

Description

DETAILED DESCRIPTION OF THE INVENTION [Technical Field of the Invention] The present invention relates to a television receiver equipped with a tuning function.

[Prior art and its problems] Conventionally, some television receivers are equipped with an auto-tuning function. The television receiver having the above-mentioned auto-tuning function is provided with a tuning up key and a down key, and when the above-mentioned up key or down key is operated, the tuner tuning voltage is automatically swept, The sweep of the tuner tuning voltage is stopped where the channel was. However, conventional television receivers equipped with the auto-tuning function display video signals even when the channel is not tuned. The video signal at this time is noise, and it is completely unknown at what level it is output. Therefore, when the channels are not matched, a noise or striped image is displayed, which is very difficult to see.

[Object of the Invention] The present invention has been made in view of the above points, and provides a television that can prevent noise, striped patterns, etc. from being displayed on the image even when the channel is not tuned when performing auto-tuning. The purpose is to provide a John receiver.

[Summary of the Invention] The present invention provides a television receiver equipped with an auto-tuning function.
When the tuning is not correct, pre-stored specific image data is displayed instead of the received video signal,
The received video signal is displayed when tuning is performed.

(Embodiment of the Invention) An embodiment of the present invention will be described below with reference to the drawings. First, the external configuration of the present invention will be explained with reference to FIG. 1. In FIG. is provided with a video display section 12, a channel display section 13, and a volume display section 14.The video display section 12, channel display section 1
3. The volume display section 14 is configured, for example, integrally on one display panel 15, but is configured to be displayed separately by display windows formed on the front surface of the case 11. In the channel display section 13, numerical values indicating VHF and UHF channels are displayed by printing or the like on both sides of the case 11. Further, on the front surface of the case 11, an up key 16a and a down key 16b for tuning are provided, as well as an up key 17a and a down key 17b for adjusting the volume. Furthermore, the case 11 includes an auto/manual changeover switch 18 and a V)-IF/1JHF changeover switch 19.
, a power switch 20 is provided, and a Rondo antenna 21 is provided on the upper part of the case 11.

Next, the configuration of the electronic circuit provided in the case 11 will be explained with reference to FIG. 2. Radio waves received by the antenna 21 are supplied to an electronic tuner 22 . This electronic tuning tuner 22 selects a desired radio wave from among the received radio waves and converts it to an intermediate frequency.
Output to. This TV linear circuit 23 consists of 1, an intermediate frequency amplification circuit, a video detection circuit, a synchronous separation circuit, etc.
While outputting the audio signal to the audio circuit 30, the video signal B
, an intermediate frequency signal D, and a synchronization signal (horizontal synchronization signal, vertical synchronization signal) E. The video signal B output from the television linear circuit 23 is sent to the switch circuit 24.

This switch circuit 24 selects the video signal B from the TV linear circuit 23 or specific image data from the control circuit 21, the details of which will be described later, and sends it to the liquid crystal drive circuit 25 to display the video display section 12 on the liquid crystal display panel 15. drive Further, the intermediate frequency signal outputted from the television linear circuit 23 is sent to a frequency detection circuit 26, and the synchronization signal E is sent to a control circuit 27. The frequency detection circuit 26
discriminates the intermediate frequency signal input from the TV linear circuit 23, and outputs an A F T (A auto F
(requency tuning) signal is output and given to the control circuit 27. Further, a key manual section 28 is connected to this control circuit 27 . This key manual unit 28 is the up key 16 for tuning shown in FIG.
a1 Down key 16b1 Up key 17a for volume adjustment
1 down key 17b, an auto/manual changeover switch 18, a VHF/IJHF changeover switch 19, and a power switch 20. However, the control circuit 2
7 outputs a tuning control signal to the tuner tuning voltage control circuit 29 in accordance with the operation of the tuning up key 16a and down key 16b from the key power unit 28, and outputs a tuning signal Vt from the tuner tuning voltage control circuit 29 to the electronic tuning tuner 22. Output. In this case, the control circuit 27 outputs a mute signal MU to the switch circuit 24 and the audio circuit 30 according to the tuning state of the channel. This audio circuit 30 prohibits audio output from the speaker SP while the mute signal MU sent from the control circuit 21 is, for example, 'OL', and when the mute signal MU reaches '1°', the audio output is disabled. The control circuit 27 restarts the output operation.The control circuit 27 is equipped with an internal image memory as will be described in detail later, and outputs the mute signal MU(
When outputting “O”), the data stored in the image memory V
S is output to the switch circuit 24. This switch circuit 2
4 selects the video signal from the TV linear circuit 23 when the mute signal MtJ is "1", and outputs the mute signal F.
When tll is “0°”, the image signal S from the control circuit 27 is selected and output to the liquid crystal drive circuit 25.

Further, the control circuit 27 outputs a volume adjustment signal to the audio circuit 30 in accordance with the operation of the volume adjustment up key 17a1 and the down key 17b from the key input unit 28. Further, the control circuit 27 outputs a volume display signal and a channel display signal F to the liquid crystal drive circuit 25 in accordance with each key operation in the key manual section 28, and also outputs a volume display signal and a channel display signal F to the liquid crystal drive circuit 25 in accordance with a synchronization signal E from the television linear circuit 23.
A display timing signal is output to 5. The liquid crystal drive circuit 25 controls the video display section 12 in the liquid crystal display panel 15 according to signals from the switch circuit 24 and the control circuit 27.
The channel display section 13 and the volume display section 14 are each driven to display.

FIG. 3 shows details of the control circuit 27. Reference numeral 271 is a reference clock generation circuit that generates reference clock pulses φ1, φ2, φ3, and φ4 in response to the horizontal synchronizing signal φh from the television linear circuit 23. The above clock pulse φ1,
φ2 and φ3 are three-phase clocks having twice the frequency of the horizontal synchronizing signal φh, and the clock pulse φ4 is obtained by dividing the clock pulse φ1 by four. Further, 272 is a key control circuit which judges the key force from the key force section 28 and outputs it to the control section 273. This control section 273 includes
The AFT signal from the frequency detection circuit 26 is inputted at high level. The control section 273 operates according to the AFT signal L1H, and controls the tuning voltage force counter 215 during tuning.
When a channel is selected, a vertical synchronization detection circuit 274 (details of which will be described later)
A channel match signal CH is output. The vertical synchronization detection circuit 274 operates according to the control signal from the control section 273 and the vertical synchronization signal φV from the TV linear circuit 23, and transmits the synchronization signal to the display drive control circuit 276, the reset signal R to the control section 273, and the mute signal MtJ. is output to the switch circuit 24, the audio circuit 30, and the image memory 217.

Then, the display drive control circuit 276 generates a display timing signal according to the synchronization signal from the synchronization detection circuit 274 and outputs it to the liquid crystal drive circuit 25 and the image memory 277. For example, specific image data is written in the image memory 277 as shown in FIG. The signal is sent to the drive circuit 25. on the other hand,
The tuned voltage power counter 275 performs a count-up operation based on a signal from the control section 273 and outputs the count value to the tuned voltage pulse width modulated wave generation circuit 278. The tuning voltage pulse width modulated wave generating circuit 278 generates a tuning voltage pulse width modulated wave according to the count value of the tuning voltage power counter 275, and outputs it to the tuner tuning voltage control circuit 29.

Next, details of the vertical synchronization detection circuit 274 will be explained with reference to FIG. In FIG. 5, 31 is a mismatch counter, which outputs a "1" signal from its output terminal when the count value reaches "64". 32 is a match counter, equipped with output terminals 01.02, and when the count value reaches "64". When the count value is "2", the "1" signal is output from the output terminal 01, and when the count value is "4", the "1" signal is output from the output terminal 02., 33 is 5
It is a 25-decimal counter, and is equipped with output terminals 01.02.The output terminal 01 outputs the count contents, and the output terminal O2 outputs a signal. 34 is a synchronization detection counter, and the output terminal O
f, 02, outputs a ``1'' signal from the output terminal Os when the count value is ``7'', and outputs a ``°1'' signal from the output terminal 02 when the count value is ``8''. The vertical synchronizing signal φ■ sent from the synchronization separation circuit of the TV linear circuit 23 in FIG. 32 clock terminal CK and mismatch counter 31 reset terminal R
, are input to the clock terminal GK of the synchronization detection counter 34 via the NOR circuit 38, respectively. Further, the clock terminal GK of the 525-decimal counter 33 has a horizontal synchronization signal φ
A reference clock pulse φ1 having a frequency twice that of h is input. The latch circuit 36 includes a NOR circuit 361, an AND circuit 362, and an inverter 363, and is set by the clock pulse 11 input to the AND circuit 362 and reset by the output of the OR circuit 35. Then, the output of the counter 31 is inputted to the small reset terminal R, and also inputted to the latch circuit 41 as a reset signal. The output of this latch circuit 41 is input to a NAND circuit 43 via a NOR circuit 42. The above latch circuit 41
consists of a NAND circuit 411, an AND circuit 412, and an inverter 413, and is connected from the coincidence counter 32 to the inverter 4.
It is set by a signal input to AND circuit 412 via 4. Further, the vertical synchronization signal φ■ sent from the synchronization separation circuit is sent to the NAND circuit 43 to the OR circuit 43.
5 and a NAND circuit 46. Furthermore, the output of the inverter 413 is input to the NAND circuit 4G. Then, the output of the NAND circuit 43 is outputted to the display drive control circuit 2 as the output signal φ■ of the vertical synchronization detection circuit 2γ4.
76 and input to the reset terminal R of the 525-decimal counter 33. The signal output from the output terminal 02 of this 525-decimal counter 33 is output from the flip-flop 4.
Sent to 1. This flip 70 tube 47 reads the output of the 525-decimal counter 33 in synchronization with the clock pulse φ2, and reads the output of the NAND circuit 42, the OR circuit 45, and the AND circuit 31.
is input to the OR circuit 3 via the inverter 48.
Enter 5. Further, the count contents outputted from the output terminal 01 of the 525-decimal counter 33 are decoded by the decoder 49 and then read into the flip 70 tube 50 in synchronization with the clock pulse φn2. This clock pulse φrL2 is a clock for latching 1H display data in the liquid crystal drive circuit 25. The data held in this flip-flop 50 is transferred to the display drive control circuit 27.
6 as a signal [ ) out to start vertical scanning.

On the other hand, the channel matching signal CH sent from the control section 273 is input to the flip 70 knob 51.

The flip-flop 51 reads input data in synchronization with the clock pulse φ1 and inputs it to the flip-flop 52 and the AND circuit 53. The above flip-flop 52
reads input data in synchronization with clock pulse φ2 and outputs it in synchronization with clock pulse φ1. The output of the flip-flop 52 is input to the reset terminal R of the coincidence counter 32 via an AND circuit 53 and an OR circuit 39. Further, the channel coincidence signal CH is inputted to the reset terminal R of the synchronization detection counter 34 via the inverter 54. This synchronization detection counter 34 has a carry output connected to its own clock terminal GK via a NOR circuit 38.
The count output is sent as a reset signal R to the control unit 273 in FIG. 3 via the inverter 55 and the NOR circuit 56. Further, the channel match signal CH is input to the reset terminal of the flip-flop 57 and the AND circuit 58.

Further, the signal output from the output terminal 01 of the coincidence counter 32 is inputted to the set terminal of the flip-flop 570 via the inverter 59. The output of the flip 70 knob 57 is taken out via the AND circuit 58 and input to the NOR circuit 56, and the mute signal M
It is sent to the switch circuit 24 and the audio circuit 30 as tJ.

Next, the operation of the above embodiment will be explained. In FIG. 2, a television signal induced in an antenna 21 is tuned and frequency-converted by an electronic tuner 22, band-amplified and image-detected by a television linear circuit 23, and taken out as a video signal B. This video signal is sent to the liquid crystal drive circuit 25 via the switch circuit 24, and is sent to the video display section 1.
2. Further, an audio signal is output from the television linear circuit 23 and sent to the audio circuit 30. This audio circuit 30 amplifies the audio signal from the television linear circuit 23 and outputs it from the speaker SP. In this case, while the video signal is normally received as described above, the mute signal MU output from the control circuit 27 is "1", so the switch circuit 24 is connected to the TV linear circuit 2.
3 is selected and output to the liquid crystal drive circuit 25, and the audio circuit 30 drives the speaker SP according to the audio signal from the television linear circuit 23.

However, when the tuning up key 16a or down key 16b is operated while a predetermined channel is selected as described above, the auto-tuning operation is started, but at this time, the digital tuning control circuit 273 outputs an output signal. The coincidence signal CH becomes 0'', thereby resetting the flip-flop 57 in the vertical synchronization detection circuit 274° of FIG. 5, and the mute signal MU output from the AND circuit 58 becomes 0''. When this mute signal MU becomes 11011, the audio circuit 3
0 prohibits output from speaker SP. Further, when the mute signal MLI becomes '0'', the image data shown in FIGS. 4(a) to 4(d), for example, is read out from the image memory 277 in FIG. In FIG. 4 above, the image data shown in (a) is the text rTVJ, the image data shown in (b) is an upward arrow indicating that up-tuning is being performed by operating the up key 16a, and the image shown in (C) is The data is a downward arrow indicating that the down key 16b is operated and down tuning is being performed, (d) is VHF
rVHF indicates the status when receiving television.
” character data. In this case, the above image data is
The present invention is not limited to the example shown in FIG.

The image data read from the image memory 277 is sent to the switch circuit 24. switch circuit 24
When the mute signal MU becomes 0'', the image data from the image memory 277 is sent to the liquid crystal drive circuit 25 instead of the received video signal to be displayed on the video display section 12.

On the other hand, as mentioned above, the tuning up key 16
When a or the down key 16b is operated, the following auto-tuning process is performed. That is, the television linear circuit 23 transmits the intermediate frequency signal amplified by the internal intermediate frequency amplification circuit 231 to the frequency detection circuit 2.
At the same time, the vertical synchronizing signal φV and horizontal synchronizing signal φh separated by the synchronizing separation circuit 234 are output to the control circuit 21. The frequency detection circuit 26 inputs the intermediate frequency signal from the TV linear circuit 23 to a frequency discriminator, converts the frequency change into a voltage change, and performs auto-tuning using the first and second comparators. AF
Create T signals H and L. Currently, in Japan, an upper hetero gain method is used in which the local oscillation frequency is higher than the received radio signal. Therefore, the local oscillation frequency is always higher than the video carrier of the receiving channel by the intermediate frequency. As the tuner tuning voltage increases, the local oscillation frequency also gradually increases. As a result, the intermediate frequency, which is the difference between the local oscillation frequency and the received video frequency, also gradually increases. When the output of the frequency discriminator 261 is equal to or higher than the first reference voltage, a first comparator generates a signal that provides a level of 1°. Similarly, when the output of the frequency discriminator is lower than the second reference voltage, the second comparator generates a signal H which gives a "1" level.Then, the frequency detection circuit 26 outputs the AFTF signals in the order of -H. If the tuner tuning voltage is fixed at this time, the intermediate frequency can be correctly set to a predetermined frequency, for example, 58.75M1-1z.

Conversely, if the tuner tuning voltage is lowered, the intermediate frequency will gradually become lower, so the AFTF signal will become H-L.
If the tuner tuning voltage is fixed when output from the frequency detection circuit 26 in this order, the intermediate frequency can be set correctly as in the above case. AFTF No.H outputted from the frequency detection circuit 26 is sent to a control circuit 27, where the tuner tuning voltage is controlled.

That is, in the auto mode, when the tuning up key 16a is pressed, the frequency detection circuit 26
If the down key 16b is pressed, the AF lower low signal is output in the order of HL. If the up key 16a is operated now, the control section 273 sends a count-up signal to the tuning voltage force counter 275, increments the content of the tuning voltage force counter 275 by "+8", and exits from the current channel area. The count value of the tuning voltage force counter 275 is sent to a modulated wave generation circuit 278, modulated into a pulse width, and sent to a tuner tuning voltage control circuit 29 shown in FIG. This tuner tuning voltage control circuit 29 integrates the modulated wave from the modulated wave generating circuit 278 using an integrating circuit, and then amplifies the modulated wave from the modulated wave generating circuit 278.
The voltage is converted to 1 m pressure and applied to the electronic tuner 22 to change the local oscillation frequency. After that, the tuning voltage power counter 27
5 is sequentially counted up to raise the reception frequency of the electronic tuning tuner 22, and the AFT signals output from the frequency detection circuit 26 in the order of L-H are detected. When the frequency detection circuit 26 outputs the AFT signals in the order of L-H, the control section 273 outputs the channel coincidence signal CH to the vertical synchronization detection circuit 274 shown in FIG.

When the vertical synchronization detection circuit 274 receives the channel coincidence signal OH from the control section 273, it resets the synchronization detection counter 34 and also resets the coincidence counter 32. That is, the channel matching signal CH is
It is input to the reset terminal R of the synchronization detection counter 34 via the inverter 54, and the flip-flop 51.
52, the pulse signal is waveform-shaped into a constant width pulse signal by the AND circuit 53, and is inputted to the reset terminal R of the coincidence counter 32 via the OR circuit 39. As a result, the synchronization detection counter 34 and the coincidence counter 32 are reset. Thereafter, the 525-decimal counter 33 counts up in response to the clock pulse φ1, but the vertical synchronization signal φ is sent from the synchronization separation circuit.
When the vertical synchronization signal φV is sent, the vertical synchronization signal φV is input to the synchronization detection counter 34 via the NOR circuit 38, and the synchronization detection counter 34 is incremented by "+1". Next, it is determined whether the value of the coincidence counter 32 is "2", that is, whether the vertical synchronization signal φ■ sent from the synchronization separation circuit has the correct period. If the vertical synchronization signal φ■ has the correct period, the coincidence counter 32 counts up, and when the count value reaches "2", the "1" signal is output from the output terminal 01, and the signal is passed through the inverter 59. The signal is sent to the flip 70 block 57, and the synchronization latch, that is, the flip-flop 57 is set.Then, it is determined whether the content of the synchronization detection counter 34 is "7". Furthermore, if the content of the coincidence counter 32 has not reached "2", the synchronization detection counter 3
4, it is determined whether the content has become "7" or not. If the content of the synchronization detection counter 34 has not reached [7], 52
The quinary counter 33 is counted up and the above operation is repeated. When the content of the synchronization detection counter 34 becomes "7", it is determined whether the flip-flop 57 is set or not. It is determined whether or not it has become "2". That is, if the count value of the coincidence counter 32 reaches "2" by the time the count value of the synchronization detection counter 34 reaches r7J, it is determined that the receiving channel has been correctly selected. If the reception state is not normal and the count value of the coincidence counter 32 does not reach "2" before the count value of the synchronization detection counter 34 reaches "7", the flip 70 knob 57
is not set, the mute signal MU output from the AND circuit 58 is held at the "0°" state. In this state, when the count value of the synchronization detection counter 34 reaches "7" and a signal "1" is output from the output terminal 01, the signal is inverted to O' by the inverter 55 and input to the NOR circuit 56.

At this time, as mentioned above, from the AND circuit 58 to the NOR circuit 56
Since the 'O°' signal is input to the NOR circuit 56, the reset signal R output from the NOR circuit 56 becomes "1°', and the control unit 273 is reset. Therefore, the control unit 273 performs the above-described tuning operation. resume.

When the receiving state becomes normal and a coincidence count is made, a "1°' signal is output from the output terminal 01 and the flip-flop 57 is set. After that, the count value of the synchronization detection counter 34 becomes "7". Then, the output terminal O1
A signal “1°” is output from the inverter 55, inverted to O”, and input to the NOR circuit 56. However, at this time, the flip-flop 57 is set and the output signal “1” is outputted through the AND circuit 58. Since the reset signal R output from the NOR circuit 56 is input to the NOR circuit 56, the reset signal R output from the NOR circuit 56 is held in the P O'' state.Furthermore, as described above, the coincidence output of the coincidence counter 32 causes the flip 70 knob 57 to be input to the NOR circuit 56.
When is set, the mute signal MU output from the AND circuit 58 becomes ii 1 ++ and the image memory 277
is input to the switch circuit 24 and the audio circuit 3.
Sent to 0. After that, the synchronization detection counter 34
When the count value of becomes “8”, “1” is output from output terminal 02.
"The signal is output and input to the NOR circuit 38, and the clock input to the synchronization detection counter 34 is prohibited. At this time, the control unit 273 stops the clock of the tuned voltage counter 275, fixes the count value, and performs the tuning operation. end.

When the mute signal MtJ outputted from the AND circuit 58 reaches 1 as described above, the output inhibition of the audio circuit 30 is canceled, and the audio circuit 30 outputs the TV linear fn.
Amplify the audio signal sent from 123 and send it to speaker S.
Output from P. Further, when the mute signal MU becomes 1'', the output operation of the image memory 271 in FIG. 3 is prohibited, and the switch circuit 24 is switched to the TV linear circuit 23 side.

Therefore, the video signal of the receiving channel selected by the tuning process is sent from the TV linear circuit 23 to the liquid crystal drive circuit 25 via the switch circuit 24, and is displayed on the video display unit 12 instead of the specific image data. .

The above description has been made for the case where the up key 16a is operated, but when the down key 161) is operated, the operation of the down key 16b is detected in the control circuit 27, and the down process is performed in the same manner as in the case of the up process. It is done.

Also in the manual mode, when the up key selection is made, the same operation as in the auto mode is performed.

In addition, although the above embodiment has been explained by taking as an example a television receiver equipped with an auto-tuning function, it is also applicable to manual tuning.

[Effects of the Invention] As described in detail above, according to the present invention, in a television receiver equipped with an auto-tuning function, when the auto-tuning function is performed, a specific Since the video signal is displayed and the received video signal is displayed when tuning is performed, noise, stripes, etc. will be avoided until the next channel is tuned or when the received radio waves are disturbed. This can be reliably prevented from being displayed.
A stable screen can be displayed at all times.

[Brief explanation of drawings]

The drawings show one embodiment of the present invention; FIG. 1 is an external configuration diagram, FIG. 2 is a block diagram showing the overall configuration of an electronic circuit, and FIG. 3 shows details of the control circuit in FIG. 2. FIG. 4 is a block diagram showing an example of data storage in the image memory in FIG. 3, and FIG. 5 is a block diagram showing details of the vertical synchronization detection circuit portion in FIG. 3. 11... Case, 12... Video display section, 13...
Channel display section, 14...Volume display section, 15...
Display panel, 16a... Up key for tuning, 16b... Down key, 17a... Up key for adjusting sound 1, 17b... Down key, 18... Auto/manual changeover switch, 19 ...VHF/UH
F selector switch, 20...power switch, 21...
Antenna, 22... Electronic tuning tuner, 23... Television linear circuit, 24... A/D conversion circuit, 25...
・Liquid crystal drive circuit, 26...Frequency detection circuit, 27...
・Control circuit, 28... Key human power section, 29... Tuner same 111! Pressure control circuit, 30... Audio circuit, 271
. . . Reference clock generation circuit, 212 . . . Key control circuit, 213 . . . Control unit, 274 . 31... Mismatch counter, 32... Coincidence counter, 33... 525-decimal counter, 34... Synchronization detection counter, 36.41... Latch circuit. Applicant's agent Patent attorney Takehiko Suzue

Claims (1)

[Claims] A television receiver equipped with a tuner, a display section that displays the video signal output from the television receiver, an image memory that stores specific image data, and a reception channel in the television receiver that is correctly selected. If the receiving channel is out of alignment based on the signal from the judging means during tuning, the data stored in the image memory 277 is read out and displayed on the display section to check whether the receiving channel is correct. A television receiver comprising means for displaying a received video signal on the display section when selected.