JPS6135434U - Digital tuning circuit - Google Patents

Digital tuning circuit

Info

Publication number
JPS6135434U
JPS6135434U JP11965284U JP11965284U JPS6135434U JP S6135434 U JPS6135434 U JP S6135434U JP 11965284 U JP11965284 U JP 11965284U JP 11965284 U JP11965284 U JP 11965284U JP S6135434 U JPS6135434 U JP S6135434U
Authority
JP
Japan
Prior art keywords
tuning
frequency
signal
circuit
control circuit
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11965284U
Other languages
Japanese (ja)
Other versions
JPH066620Y2 (en
Inventor
実 臼井
孝弘 布施
三朗 小林
Original Assignee
カシオ計算機株式会社
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by カシオ計算機株式会社 filed Critical カシオ計算機株式会社
Priority to JP1984119652U priority Critical patent/JPH066620Y2/en
Publication of JPS6135434U publication Critical patent/JPS6135434U/en
Application granted granted Critical
Publication of JPH066620Y2 publication Critical patent/JPH066620Y2/en
Anticipated expiration legal-status Critical
Expired - Lifetime legal-status Critical Current

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  • Channel Selection Circuits, Automatic Tuning Circuits (AREA)

Abstract

(57)【要約】本公報は電子出願前の出願データであるた
め要約のデータは記録されません。
(57) [Summary] This bulletin contains application data before electronic filing, so abstract data is not recorded.

Description

【図面の簡単な説明】[Brief explanation of drawings]

図面は本考案の一実施例を示すもので、第1図はパネル
型テレビジョン受像機の外観構成図、第2図はテレビジ
ョン受像機の全体の回路構成を示すブロック図、第3図
は周波数検出回路の構成を示すブロック図、第4図は第
3図の周波数休出回路の動作を説明するためのタイミン
グチャート、第5図は制御回路の詳細を示すブロック図
、第6図は第5図における同調電圧カウンタの詳細を示
す回路構成図、第7図は第5図におけるデジタルチュー
ニング制御回路部分の詳細を示すブロック図、第8図a
, bは同調電圧カウンタをアップ/ダウンさせた場合
のチューニング電圧の変化を示す図である。 11・・・ケース、12・・・映像表示部、13・・・
チヤンネル表示部、14・・・音量表示部、15・・・
表示パネル、16a・・・チューニング用のアップキー
、16b・・・ダウンキー、17a・・・音量調整用の
アツプキー、17b・・・ダウンキー、18・・・オー
ト/マニュアル切換スイッチ、19・−VHF /UH
F 切換スイツチ、20・・・電源スイッチ、21・・
・アンテナ、22・・・電子同調チューナ、23・・・
テレビリニア回路、24・・・A/D変換回路、25・
・・液晶駆動回路、26・・・周波数検出回路、27・
・・制御回路、28・・・キー人力部、29・・・チュ
ーナ同調電圧制御回路、261・・・周波数弁別器、2
62,’263・・・コンパレータ、264,265・
・・基準電源、27j,・・・基準クロツク発生回路、
272・・・キー制御回路、273・・・デジタルチュ
ーニング制御回路、274・・・同期検出回路、275
・・・同調電圧カウンタ、276・・・′メモリ、27
7・・・変調波作成回路、278・・・音量表示回路/
チャンネル表示回路、2・79・・・表示制御用回路、
2710・・・4ビットカウンタ、2711・・・D/
A変換回路、67・・・AFTカウンタ、79・・・デ
コーダ、84・・・64進カウンタ。
The drawings show one embodiment of the present invention; FIG. 1 is an external configuration diagram of a panel type television receiver, FIG. 2 is a block diagram showing the overall circuit configuration of the television receiver, and FIG. 3 is a block diagram showing the overall circuit configuration of the television receiver. FIG. 4 is a block diagram showing the configuration of the frequency detection circuit, FIG. 4 is a timing chart for explaining the operation of the frequency rest circuit in FIG. 3, FIG. 5 is a block diagram showing details of the control circuit, and FIG. FIG. 5 is a circuit configuration diagram showing details of the tuning voltage counter; FIG. 7 is a block diagram showing details of the digital tuning control circuit portion in FIG. 5; FIG. 8a
, b are diagrams showing changes in the tuning voltage when the tuning voltage counter is turned up/down. 11... Case, 12... Video display section, 13...
Channel display section, 14...Volume display section, 15...
Display panel, 16a...Up key for tuning, 16b...Down key, 17a...Up key for volume adjustment, 17b...Down key, 18...Auto/manual changeover switch, 19.- VHF/UH
F Selector switch, 20...Power switch, 21...
・Antenna, 22... Electronic tuning tuner, 23...
TV linear circuit, 24...A/D conversion circuit, 25.
...Liquid crystal drive circuit, 26...Frequency detection circuit, 27.
... Control circuit, 28 ... Key human power section, 29 ... Tuner tuning voltage control circuit, 261 ... Frequency discriminator, 2
62,'263... Comparator, 264,265.
...Reference power supply, 27j, ...Reference clock generation circuit,
272...Key control circuit, 273...Digital tuning control circuit, 274...Synchronization detection circuit, 275
... Tuning voltage counter, 276...'Memory, 27
7...Modulated wave creation circuit, 278...Volume display circuit/
Channel display circuit, 2.79...display control circuit,
2710...4-bit counter, 2711...D/
A conversion circuit, 67...AFT counter, 79...decoder, 84...64-decimal counter.

Claims (1)

【実用新案登録請求の範囲】[Scope of utility model registration request] 電子同調チューナと、この電子同調チューナによる受信
信号の周波数を弁別し、その入力周波数と設定周波数と
の周波数差に応じて弁別信号を出力する周波数弁別器と
、この周波数弁別器から出力される弁別信号を検出して
上記一子同調チューナに対するチューニング制御信号を
出力するチューニング制御回路と、チューニング時上記
チューニング制御信号が急激に変化する予め設定したチ
ューニング周波数近傍において、上記周波数弁別器から
チューニング制御回路へ入力される弁別信号をマスクす
る手段とを具備したことを特徴とするデジタルチューニ
ング回路。
An electronic tuning tuner, a frequency discriminator that discriminates the frequency of a signal received by the electronic tuning tuner and outputs a discrimination signal according to the frequency difference between the input frequency and a set frequency, and a discrimination output from the frequency discriminator. a tuning control circuit that detects a signal and outputs a tuning control signal to the one-child tuning tuner; and a tuning control circuit that detects a signal and outputs a tuning control signal to the one-child tuning tuner, and a tuning control circuit that outputs a tuning control signal from the frequency discriminator to the tuning control circuit when the tuning control signal changes rapidly near a preset tuning frequency during tuning. A digital tuning circuit comprising means for masking an input discrimination signal.
JP1984119652U 1984-08-03 1984-08-03 Digital tuning circuit Expired - Lifetime JPH066620Y2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP1984119652U JPH066620Y2 (en) 1984-08-03 1984-08-03 Digital tuning circuit

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP1984119652U JPH066620Y2 (en) 1984-08-03 1984-08-03 Digital tuning circuit

Publications (2)

Publication Number Publication Date
JPS6135434U true JPS6135434U (en) 1986-03-04
JPH066620Y2 JPH066620Y2 (en) 1994-02-16

Family

ID=30678521

Family Applications (1)

Application Number Title Priority Date Filing Date
JP1984119652U Expired - Lifetime JPH066620Y2 (en) 1984-08-03 1984-08-03 Digital tuning circuit

Country Status (1)

Country Link
JP (1) JPH066620Y2 (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63179092U (en) * 1987-05-12 1988-11-18

Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55118216A (en) * 1979-03-05 1980-09-11 Sanyo Electric Co Ltd Digital preset tuner

Patent Citations (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS55118216A (en) * 1979-03-05 1980-09-11 Sanyo Electric Co Ltd Digital preset tuner

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS63179092U (en) * 1987-05-12 1988-11-18

Also Published As

Publication number Publication date
JPH066620Y2 (en) 1994-02-16

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