JPH0652856B2 - Tuning device - Google Patents

Description

TECHNICAL FIELD OF THE INVENTION The present invention relates to a tuning device such as a television receiver.

[Prior Art] In recent years, a small-sized television receiver using a liquid crystal display panel for a display unit has been put into practical use. Some of the conventional small-sized television receivers of this type have an automatic mode in which the tuner tuning voltage is automatically swept, and a manual mode in which a channel is manually selected by tuning. In this case, in the auto mode, the tuning is automatically performed by pressing the up key or the down key, and in the manual mode, the tuner tuning voltage is changed by manually operating the tuning volume to select the desired channel. . As described above, in the conventional television receiver, the up key and the down key for auto-tuning must be provided as well as the tuning volume for manual operation, which makes the tuning operation troublesome and increases the number of parts, resulting in cost reduction. There is the problem of becoming expensive.

[Problems to be Solved by the Invention] Therefore, it is possible to provide an auto / manual switch and use the up key and the down key as the manual key when the manual mode is set by this switch.

However, in such a tuning device,
When you operate the up and down keys, you may not get out of the currently tuned channel. In such a case, there is a problem that the up key or the down key must be operated again.

Further, in the manual mode, since the sweep is performed while the tuning key is held down, fine adjustment is possible, but there is a problem that it is annoying if the sweep takes too long.

The present invention has been made in view of the above circumstances, and when trying to change a channel in the auto mode, make sure that the synchronization is out of sync with the currently tuned channel, and keep pressing the tuning in the manual mode. The purpose is to be able to perform high-speed tuning when tuning.

[Means for Solving the Problems] In order to achieve the above object, the present invention provides an electronic tuning tuner, an auto / manual tuning mode selecting means,
A tuning device having an up key, a down key, and a sweeping means for changing the tuning voltage of an electronic tuning tuner in steps of 1 step, when the manual tuning mode is selected by the auto / manual tuning mode selecting means. Means for operating the sweeping means while is operated, and if the up key or the down key is operated while the auto tuning mode is selected by the auto / manual tuning mode selecting means, the sweeping means is operated. At the same time, the first step amount is set to a step number sufficient to get out of synchronization from the tuned channel, and a means for stopping the sweeping means on the receiving channel,
Judging means for judging whether or not the sweep position by the sweeping means is near the receiving channel, and if this judging means judges that it is near the receiving channel, the sweeping speed of the sweeping means is switched to a low speed and it is judged that it is not near the receiving channel. In this case, a means for switching the sweep speed of the sweep means to a high speed is provided.

[Operation] With this configuration, in auto mode,
By operating the up key and down key once, you can definitely get out of the currently synchronized channel, so you do not need to operate the up key and down key again, you can get comfortable operability and in the manual mode , Which can be finely adjusted and swept at high speed.

[Embodiment of the Invention] An embodiment of the present invention will be described below with reference to the drawings. First, the external structure of the present invention will be described with reference to FIG.
In FIG. 1, 11 is a case, and a video display section 12, a channel display section 13, and a volume display section 14 are provided on the front surface thereof. The video display section 12, the channel display section 13, and the volume display section 14 are integrally formed on, for example, one display panel 15, but are separately displayed by a display window formed on the front surface of the case 11. It has become so. Then, on the channel display section 13, numerical values indicating channels of VHF and UHF are displayed by printing or the like on both sides of the case 11. Further, on the front surface of the case 11, there are an up key 16a and a down key 16 for tuning.
b is provided, and an up key 17a and a down key 17b for adjusting the volume are provided. Furthermore, in case 11,
An auto / manual switch 18, a VHF / UHF switch 19, and a power switch 20 are provided, and a rod antenna 21 is provided above the case 11.

Next, the configuration of the electronic circuit provided in the case 11 will be described with reference to FIG. The radio wave received by the antenna 21 is supplied to the electronic tuning tuner 22. The electronic tuning tuner 22 selects a desired radio wave from the received radio waves, converts it into an intermediate frequency A, and outputs it to the television linear circuit 23. The television linear circuit 23 is composed of an intermediate frequency amplifier circuit, a video detection circuit, a sync separation circuit, etc. and outputs an audio signal to an audio circuit (not shown), and at the same time, a video signal B, an intermediate frequency signal D, and a sync signal E Is output. The video signal B output from the television linear circuit 23 is an A / D conversion circuit.
Sent to 24. The A / D conversion circuit 24 converts the video signal B from the television linear circuit 23 into a 4-bit digital signal C and sends it to the liquid crystal drive circuit 25 to drive the video display unit 12 in the liquid crystal display panel 15 for display. Further, the intermediate frequency signal D output from the television linear circuit 23 is sent to the frequency detection circuit 26, and the synchronization signal E is sent to the control circuit 27.
The frequency detection circuit 26 discriminates the intermediate frequency signal input from the television linear circuit 23, and determines H (High) or L
Two types of pulse signals of (Low) are output and given to the control circuit 27. Further, the control circuit 27 includes the above A / D conversion circuit.
While the 24-bit 4-bit digital signal C is input,
Key data is input from the key input unit 28. The key input section 28 is an up key 16a for tuning, a down key 16b for tuning, and an up key 17 for volume adjustment in FIG.
An auto / manual changeover switch 18, a VHF / UHF changeover switch 19, and a power switch 20 are provided together with a and a down key 17b. Then, the control circuit 27 outputs a tuning control signal to the tuner tuning voltage control circuit 29 to the electronic tuning tuner 22 according to the operation of the tuning up key 16a and the down key 16b from the key input section 28,
From this tuner tuning voltage control circuit 29, electronic tuning tuner
The tuning signal Vt is output to 22. In this case, the control circuit 27, while the tuning operation is being performed,
That is, until the next station is selected, the mute signal is output to the audio circuit to prohibit the audio output. Further, the control circuit 27 outputs a volume adjustment signal to the audio circuit according to the operation of the volume adjusting up key 17a and down key 17b from the key input unit 28. Furthermore, the above control circuit
The reference numeral 27 designates a volume display signal and a channel display signal F in accordance with each key operation in the key input section 28, and a liquid crystal drive circuit 25.
And a display timing signal to the liquid crystal drive circuit 25 in accordance with the synchronizing signal E from the television linear circuit 23. The liquid crystal drive circuit 25 drives the video display unit 12, the channel display unit 13, and the volume display unit 14 in the liquid crystal display panel 15 for display in accordance with signals from the A / D conversion circuit 24 and the control circuit 27.

Next, details of each part in FIG. 2 will be described.
FIG. 3 shows the details of the electronic tuning tuner 22. The antenna coupling circuit 221, the high frequency coupling circuit 222, and the mixing circuit 22 are shown.
3, consisting of a local oscillator circuit 224. Then, the received signal from the antenna 21 is input to the antenna coupling circuit 221, and the tuning signal Vt from the tuner tuning voltage control circuit 29 is input to the local oscillation circuit 224. The local oscillation circuit 224 changes its local oscillation frequency according to the tuning signal Vt from the tuner tuning voltage control circuit 29. In accordance with the change in the local oscillation frequency, the mixing circuit 223 outputs the intermediate frequency signal A to the receiving station and sends it to the television linear circuit 23.

FIG. 4 shows the details of the television linear circuit 23. The intermediate frequency amplification circuit 231, the detection circuit 232, and the video amplification circuit 233.
, A sync separation circuit 234, and an intermediate frequency amplification circuit 231.
The intermediate frequency signal A is input from the electronic tuning tuner 22 to. The intermediate frequency amplifier circuit 231 amplifies the input intermediate frequency signal A, outputs the amplified intermediate frequency signal A to the audio circuit, and detects the detected signal.
It outputs to the image amplification circuit 233 via 232. Then, the video signal B output from the video amplifier circuit 233 is A / D.
The signal is sent to the conversion circuit 24 and the sync separation circuit 234. The sync separation circuit 234 separates the horizontal sync signal φv and the vertical sync signal φh included in the video signal from the video amplifier circuit 233, and outputs them to the control circuit 27.

FIG. 5 shows the details of the frequency detection circuit 26, which comprises a frequency discriminator 261, comparators 262 and 263, and the intermediate frequency signal D sent from the television linear circuit 23 is inputted to the frequency discriminator 261. . And the frequency discriminator 26
The output of 1 is input to the “+” terminal of the comparator 262 and the “−” terminal of the comparator 263.
Also, the “−” terminal of the comparator 262 and the comparator
Reference power sources 264 and 265 are connected to the “+” terminal of the 263, respectively. The outputs of the comparators 262 and 263 are output as the auto tuning control signals L and H and sent to the control circuit 27. The above frequency discriminator 26
1 indicates that the input frequency is the set frequency fp as shown in FIG.
If it is lower, a positive discrimination signal is output, and if it is higher, a negative discrimination signal is output.
When the discrimination signal becomes higher than the reference voltage V ₁ ,
During that time, the signal L is output from the comparator 262, and when the discrimination signal becomes lower than the reference voltage V _{2, the} signal H is output from the comparator 263 during that time. Then, the output signals L and H of the comparators 262 and 263 are sent to the control circuit 27 and the auto tuning process is performed.

FIG. 7 shows the details of the control circuit 27. 270 is a power-on-clear circuit which outputs a power-on-clear signal POC to each circuit when the power is turned on. Reference numeral 271 is a reference clock generation circuit including a crystal oscillator 271a, which generates reference clock pulses φ1, φ2, φ3, and φ4. The clock pulses .phi.1, .phi.2, .phi.3 are three-phase clocks having twice the frequency of the horizontal synchronizing signal .phi.h, and the clock pulse .phi.4 is the clock pulse .phi.1 divided by four.
A key control circuit 272a determines a key input from the key input unit 28 and outputs it to the digital tuning control circuit 273. This digital tuning control circuit 273 has
AFT (Auto Frequency) from the frequency detection circuit 26
Tuning) signals L and H are input. The digital tuning control circuit 273 operates according to the AFT signals L and H, and outputs a channel coincidence signal CH to a synchronization detection circuit 274 whose details will be described later. Also. The digital tuning control circuit 273 outputs a control pulse φB and an up / down command U / D to the tuning voltage counter 275. The tuning voltage counter 275 counts up according to the signal from the digital tuning control circuit 273. The count data is written in the memory 276, and the tuning voltage pulse width modulated wave generation circuit 277 and the volume display circuit / channel display circuit are also used. Output to 278. The tuning voltage pulse width modulation wave generation circuit 277 is
A tuning voltage pulse width modulation wave is generated according to the count value of 5, and is output to the tuner tuning voltage control circuit 29. The synchronization detection circuit 274 operates according to the control signal from the digital tuning control circuit 273 and the vertical synchronization signal φv and the horizontal synchronization signal φh from the television linear circuit 23, and outputs the synchronization signal to the display control circuit 279, the reset signal R and the synchronization signal. The presence / absence signal M is output to the digital tuning control circuit 273. The display control circuit 279 outputs the common control timing signal to the liquid crystal drive circuit 25, and outputs the segment control timing signal to the liquid crystal drive circuit 25 and the volume display circuit / channel display circuit 278. Also, 272b is a key control circuit, which is an up key 17a and a down key 17 for volume adjustment.
When b is operated, the key input is performed by the 4-bit counter 27
Output to 10. The 4-bit counter 2710 counts up or down according to the operation of the up key 17a and the down key 17b, and outputs the count value to the volume display circuit / channel display circuit 278 and the D / A conversion circuit 2711. . The D / A conversion circuit 2711 converts the count value of the 4-bit counter 2710 into an analog signal and outputs it as a volume level setting signal to a volume control circuit (not shown). Then, the volume display circuit / channel display circuit 278 sends the segment drive signals of the channel display unit 13 and the volume display unit 14 to the liquid crystal drive circuit 25 according to the count outputs of the 4-bit counter 2710 and the tuning voltage counter 275. Output. 2712 is an auto level control circuit, which receives 4-bit data from the A / D conversion circuit 24 and a frame signal φf from the display control circuit 279, and outputs a level control signal according to 4-bit data. . The level control signal output from the D / A conversion circuit 2712 is converted into an analog signal by the D / A conversion circuit 2713 and sent to a reference voltage generation circuit (not shown), and the second voltage is generated by the reference voltage generation circuit. Level control is performed on the A / D conversion circuit 24 in the figure.

Next, details of the synchronization detection circuit 274 will be described with reference to FIG. In FIG. 8, reference numeral 31 is a mismatch counter, which outputs a "1" signal from the output end when the count value becomes "64". 32 is a coincidence counter, which has output terminals O ₁ and O ₂
The output terminal O ₁ outputs a “1” signal when the count value is “2”, and the output terminal O ₂ outputs a “1” signal when the count value is “4”. 33 is a 525-ary counter, which has output terminals O ₁ and O ₂ , outputs the count content from the output terminal O ₁ , and outputs a “1” signal from the output terminal O ₂ when the count value reaches “525”. Output. Reference numeral 34 is a synchronization detection counter, which has output terminals O ₁ and O ₂ and outputs a “1” signal from the output terminal O ₁ when the count value is “7” and an output terminal O ₂ when the count value is “8”. To “1”
Output a signal. Then, the sync separation circuit 234 of FIG.
The vertical synchronizing signal φv sent from the clock signal CK of the mismatch counter 31 via the OR circuit 35 and the latch circuit 36, the clock terminal CK of the match counter 32 and the reset terminal R of the mismatch counter 31 via the AND circuit 37. , The clock terminal CK of the synchronization detection counter 34 via the NOR circuit 38
Are input respectively. The reference clock pulse φ1 having a frequency twice that of the horizontal synchronizing signal φh is input to the clock terminal CK of the 525-ary counter 33. The latch circuit 36 comprises a NOR circuit 361, an AND circuit 362 and an inverter 363. The latch circuit 36 is set by the clock pulse 1 input to the AND circuit 362 and reset by the output of the OR circuit 35. The output of the counter 31 is input to the reset terminal R of the coincidence counter 32 via the OR circuit 39 and the reset signal to the latch circuit 41. The output of the latch circuit 41 is a digital tuning control circuit as a presence / absence signal M of the synchronization signal.
Sent to 273 and also through NAND circuit 42 to NAND circuit
Entered in 43. The latch circuit 41 is a NAND circuit 411.
, AND circuit 412 and inverter 413, and is reset by a signal input from the coincidence counter 32 to the AND circuit 412 via the inverter 44. The vertical synchronizing signal φv sent from the sync separation circuit 234 is input to the NAND circuit 43 via the OR circuit 45 and the NAND circuit 46. Further, the output of the inverter 413 is input to the NAND circuit 46. Then, the NAND circuit 43
Is sent to the display control circuit 279 as the output signal φV of the synchronization detection circuit 274 and is also input to the reset terminal R of the 525-ary counter 33. The signal output from the output terminal O ₂ of the 525-ary counter 33 is a flip-flop 47.
Sent to. The flip-flop 47 reads the output of the 525-ary counter 33 in synchronization with the clock pulse φ2, inputs it to the NAND circuit 42, the OR circuit 45, and the AND circuit 37, and inputs it to the OR circuit 35 via the inverter 48. The count content output from the output terminal O ₁ of the 525-ary counter 33 is decoded by the decoder 49 and then read into the flip-flop 50 in synchronization with the clock pulse φ _{n 2} . This clock pulse φ _{n 2} is applied to the liquid crystal drive circuit 25
Is a clock for latching 1H display data. Then, the data held in the flip-flop 50 is sent to the display control circuit 279 as a signal for starting vertical scanning.

On the other hand, the channel matching signal CH sent from the digital tuning control circuit 273 is a flip-flop.
Entered in 51. The flip-flop 51 reads the input data in synchronization with the clock pulse φ1 and inputs it to the flip-flop 52 and the AND circuit 53. The flip-flop 52 reads the input data in synchronization with the clock pulse φ2 and outputs it in synchronization with the clock pulse φ1. The output of the flip-flop 52 is input to the reset terminal R of the coincidence counter 32 via the AND circuit 53 and the OR circuit 39. The channel coincidence signal CH is input to the reset terminal R of the synchronization detection counter 34 via the inverter 54. The carry output of the synchronization detection counter 34 is input to its own clock terminal CK via the NOR circuit 38, and the count output is supplied to the digital tuning control circuit 273 in FIG. 7 via the inverter 55 and the NOR circuit 56. Sent as. Further, the channel coincidence signal CH is input to the reset terminal of the flip-flop 57 and the AND circuit 58. Further, the signal output from the output terminal O ₁ of the coincidence counter 32 is input to the set terminal of the flip-flop 57 via the inverter 59. Then, the output of the flip-flop 57 is taken out via the AND circuit 58, inputted to the NOR circuit 56, and sent to the audio circuit as a mute signal MU.

Next, the digital tuning control circuit shown in FIG.
Details of 273 will be described in detail with reference to FIG. The operation signal UP of the tuning up key 16a from the key control circuit 272a is input to the set terminal S of the flip-flop 61, and the operation signal DOWN of the down key 16b is input to the reset terminal R of the flip-flop 61. The output of the flip-flop 61 is sent to the tuning voltage counter 275 as the up / down signal U / D via the EX OR circuit 62. Then, the above tuning up key input U
The P and down key inputs DOWN are input to the flip-flop 65 via the NOR circuit 63 and the NAND circuit 64. Further, a signal indicating that the manual key has been operated is input from the 3 digital tuning control circuit 273 to the flip-flop 65 via the NAND circuit 64. The flip-flop 65 reads the input signal in synchronization with the vertical synchronizing signal φv, and its output is input to the reset terminal R of the quaternary counter via the OR circuit 66.
Further, it is input to the AND circuit 69 via the OR circuit 68. Further, the reset terminal R of the quaternary counter 67 is
The reset signal R from the synchronization detection circuit 274 is input via the OR circuit 66. The signals H and L from the frequency detection circuit 26 are supplied to the clocked inverters 71 and 72, respectively.
Input to the AND circuits 73 and 74 via the clocked inverters 75 and 76, and the other AND circuit via the clocked inverters 75 and 76.
Input to 72, 71. The above clocked inverters 71, 72
Is gated by the output of the above-mentioned 61, and the clocked inverters 75 and 76 are gated by the output of the flip-flop 61 inputted through the inverter 77.
The outputs of the AND circuits 73 and 74 are input to the clock terminal of the quaternary counter 67 via the OR circuit 78. The count content of the quaternary counter 67 is decoded by the decoder 79, the output at the time of "0" count is input to the AND circuit 74 via the OR circuit 80, and the output at the time of "1" count is input to the AND circuit 73. To be done. Further, the output of the decoder 79 at the time of counting “2” is the NOR circuit 62 and the AND circuit 8
1, input to the OR circuits 80 and 82, and the "3" count output is the manual mode signal MA from the key control circuit 272a.
It is input to the OR circuit 68 via the NOR circuit 83 together with the NU. The output of the decoder 79 at the time of counting "3" is 6
Reset terminal R of quaternary counter 84, flip-flop 8
6, input to the AND circuit 87. And the above NOR circuit 8
The synchronization presence / absence signal M from the synchronization detection circuit 274 is input to the second circuit 2 via the AND circuit 88, and the manual key presence signal from the key control circuit 272a is input to the inverter 2 via the inverter 89 and the AND circuit 88. The output of the OR circuit 82 is input to the gate terminal of the clocked inverter 90 and the gate terminal of the clocked inverter 91 via the inverter 92. Inverter 90, 91
, A clock pulse φ4 and a clock pulse φ3, respectively, and their outputs are input to the clock terminal of the 64-ary counter 84. And this 64-base counter
The AND circuit 69 and 81 of 84 input the output of this AND circuit 69 as a clock pulse φB.
Are sent to the tuning voltage counter 275 as latch timing signals φA. The flip-flop 86 reads the input signal in synchronization with the horizontal synchronizing signal φh and outputs the held data to the synchronization detecting circuit 274 via the AND circuit 87 as the channel coincidence signal CH. Further, the digital tuning control circuit 273 has a power-on clear signal POC from the power-on clear circuit 270.
Thus, the timing signal φC is output to the tuning voltage counter 275 as a load signal.

Next, the operation of the above embodiment will be described. In FIG. 2, the television signal induced in the antenna 21 is the electronic tuning tuner 22.
After being tuned and frequency-converted by, it is band-amplified and video-detected by the television linear circuit 23 and is taken out as a video signal B. This video signal is converted into a 4-bit digital signal C in the A / D conversion circuit 24, sent to the liquid crystal drive circuit 25, and displayed on the video display unit 12. An audio signal is output from the television linear circuit 23 and sent to the audio circuit. This audio circuit is a TV linear circuit 23
The audio signal from is amplified and output from the speaker.

Further, the television linear circuit 23 is a frequency detecting circuit for the intermediate frequency signal D amplified by the internal intermediate frequency amplifying circuit 231.
In addition to outputting to the control circuit 27, the vertical sync signal φv and the horizontal sync signal φh separated by the sync separation circuit 234 are output to the control circuit 27. Therefore, the frequency detection circuit 26 detects the intermediate frequency signal D from the television linear circuit 23 by the frequency discriminator 261.
The frequency change is converted into a voltage change by inputting to A, and the AFT signals H and L for auto tuning are created by the comparators 262 and 263. Currently, in Japan, the upper heterodyne method is used in which the local center frequency is higher than that of the received radio wave signal. Therefore, the local oscillation frequency is always higher than the image carrier of the reception channel by the intermediate frequency. Then, as the tuner tuning voltage is increased, the local oscillation frequency also gradually increases. As a result, the intermediate frequency, which is the difference between the local oscillation frequency and the received video frequency, also gradually increases. FIG. 6 shows changes in the output voltage of the frequency discriminator 261 with the horizontal axis representing the intermediate frequency at this time. AFT signal L which gives a "1" level when the output of the frequency discriminator 261 is equal to or higher than the reference voltage V ₁
Is created by the comparator 262. Similarly, frequency discriminator 26
The AFT signal H which gives a "1" level when the output of 1 is the reference voltage V ₂ or less is generated by the comparator 263. And
If the tuner tuning voltage is fixed when the AFT signal is output from the frequency detection circuit 26 in the order of L-H, the predetermined intermediate frequency, for example, 58.75 MHz can be correctly set.

On the contrary, when the tuner tuning voltage is lowered, the intermediate frequency is gradually lowered, so that the AFT signal becomes HL.
If the tuner tuning voltage is fixed when output from the frequency detection circuit 26 in this order, the intermediate frequency can be set correctly as in the above case. Therefore, the AFT signals L and H output from the frequency detection circuit 26 are controlled by the control circuit.
The tuner tuning voltage is sent to the control circuit 27, and the tuner tuning voltage is controlled by the control circuit 27 as described above, the details of which will be described later.

On the other hand, the control circuit 27 detects the synchronizing signals φv and φh from the television linear circuit 23 and controls the scanning of the image display unit 12. First, regarding the detection processing of the synchronization signal in the synchronization detection circuit 274 in the control circuit 27,
This will be described with reference to the flowchart of FIG. 0 and the timing chart of FIG. The sync detecting circuit 274 is provided with a mismatch counter 31, a match counter 32, a latch circuit as shown in step A1 of FIG. 10 when the power switch 20 is turned on.
41 is reset. When the latch circuit 41 is reset, the output of the inverter 413 becomes "1" and the NAND circuit
Entered in 46. In this state, the sync separation circuit 234
When the vertical synchronizing signal .phi.v shown in FIG. 1 is given, the output of the NAND circuit 46 becomes "0", the "1" signal is outputted from the NAND circuit 43, and the 525-base counter 33 is reset as shown in step A2. . The 525-ary counter 33 thereafter counts clock pulses φ1 having a frequency twice that of the horizontal synchronizing signal φh, and when the count value reaches “525”, outputs a “1” signal from the output terminal O ₂ . this
The output of the 525-ary counter 33 is read by the flip-flop 47 in synchronization with the clock pulse φ2. As a result, the output of the flip-flop 47 becomes "1", which is input to the AND circuit 37 and also inverted by the inverter 48 into a "0" signal and input to the OR circuit 35.
As indicated by 3, the presence / absence of the vertical synchronizing signal φv is determined.
That is, if the next vertical synchronizing signal .phi.v is normally received, the output of the AND circuit 37 becomes "1", and step A
The coincidence counter 32 is incremented by "+1" as shown at 4 and the non-coincidence counter 31 is reset at step A5. Thereafter, in step A6, it is judged whether or not the count value of the coincidence counter 32 is "4", and if it is "4", the "1" signal is output from the output terminal O ₂ . As a result, the latch circuit 41 is set as shown in step A7, and then the process proceeds to step A8. If the count value of the coincidence counter 32 is not "4" in step A6, the process proceeds to step A8 to determine whether the latch circuit 41 is set or reset. When the latch circuit 41 is set, its output becomes "1" and is input to the NAND circuit 42. Therefore, as shown in step A9, the output of the 525-base counter 33 is held in the flip-flop 47 and the output of the 52-ary counter 33 is NAND. circuit
It is output from 42. As a result, the output of the NAND circuit 42 becomes "0" and the output of the NAND circuit 43 becomes "1", and the output of the NAND circuit 43 becomes the vertical synchronizing signal φV as the liquid crystal drive circuit.
Sent to 25. The vertical synchronizing signal φV causes the frame signal φ in the liquid crystal drive circuit 25 as shown in FIG.
f is created. When the latch circuit 41 is reset, the output of the inverter 413 becomes "1" and is input to the NAND circuit 46. Therefore, as shown in step A10, the vertical sync signal φv from the sync separation circuit 234
And a 52-bit counter held in flip-flop 47
The output of the OR circuit 45 with 33 is output from the NAND circuit 46.
As a result, the output of the NAND circuit 46 is “0”, and the NAND circuit 43 is
Becomes "1", and the output of the NAND circuit 43 is sent to the liquid crystal drive circuit 25 as the vertical synchronizing signal φV. After that, the process returns to step A2 and the output of the NAND circuit 43 causes 52
The quinary counter 33 is reset and the above operation is repeated.

Then, in step A3 above, the 525-ary counter
When the output of 33 is read into the flip-flop 47, for example, when the next vertical synchronizing signal φv is not given due to deterioration of the receiving state, the output of the OR circuit 35 becomes “0” and the latch circuit 36 becomes Set. This allows the latch circuit 36
Becomes "1", and the content of the mismatch counter 31 is incremented by "+1" as shown in step A11. Next, as shown in step A12, it is judged whether or not the count value of the mismatch counter 31 has reached "64". If it has not reached "64", the output of the mismatch counter 31 is "0", so immediately. As shown in step A8, the latched state of the latch circuit 41 is judged and the operation proceeds to the next step. If the count value of the non-coincidence counter 31 reaches "64", the non-coincidence counter 31 outputs a "1" signal, the coherence counter 32 is reset as shown in step A13, and at the same time as shown in step A14. Then, the latch circuit 41 is reset. After that, as shown in step A8, it is determined whether the latch circuit 41 is set or reset.
If the latch circuit 41 is set, step A9
As shown in, the output of the 525-ary counter 33 held in the flip-flop 47 is output to the liquid crystal drive circuit 25 as a vertical synchronizing signal φV via the NAND circuits 42 and 43. If the latch circuit 41 is reset, step A10
Vertical sync signal φv from sync separation circuit 234
And the OR output of the output signal of the 525-ary counter 33 is a NAND circuit
It outputs to the liquid crystal drive circuit 25 via 46 and 43. Further, if the vertical synchronizing signal φv from the sync separation circuit 234 is given before the count value of the mismatch counter 31 reaches “64”, the match counter 32 is incremented by “+1” and the mismatch counter 31 is cleared to a normal value. Return to operating state. On the other hand,
The mismatch counter 31 is decoded by the decoder 49 every time the count value reaches "525", and is read by the flip-flop 50 in synchronization with the clock φ _{n 2} . The output of the flip-flop 50 is sent to the liquid crystal drive circuit 25 as a vertical scanning start signal Dout as shown in FIG.

Next, the automatic tuning operation of the control circuit 27 shown in FIGS. 7, 8 and 9 will be described. There are two types of auto tuning: auto mode and manual mode. In the auto mode, the frequency detection circuit 26 is used to automatically select a channel. In manual mode, the tuner tuning voltage is swept by key operation. First,
Regarding the tuning operation in the auto mode, first
This will be described with reference to the flowchart of FIG. In auto mode, the up key 16 for tuning
When a is pressed, the frequency detection circuit 26 outputs the AFT signal in the order of L-H, and when the down key 16b is pressed, the AFT signal is output in the order of H-L. Then, the control circuit 27
As shown in step B1 in FIG. 12, it is always judged whether or not the tuning key is operated, and if there is no key input, it stands by. In the digital tuning control circuit 273 shown in FIG. 9, when the predetermined channel is selected and the television signal is normally received, the count value of the quaternary counter 67 is “3” and the decoder 79 The "1" signal is output from the output terminal "3" and the 64-base counter 84 is held in the reset state. When the "1" signal is output from the output terminal "3" of the decoder 79, the output of the NOR circuit 83 is "0", and the gate of the AND circuit 69 is closed. When the tuning key is operated in this state, the quaternary counter 67 is reset as shown in step B2, and then step B
In step 3, it is determined whether the operation key is the up key 16a. If the up key 16a is operated, as shown in step B4, the tuning voltage counter is controlled by the control unit 273.
Sending a count-up signal to the 275, and the tuning voltage counter 27
Add “+8” to the contents of 5. This is to ensure that the current channel is exited. That is, when the up key 16a is operated, the one-shot up key signal UP (high level) is output from the key control circuit 272a, and the flip-flop 61 is set. The set output of the flip-flop 61 is sent from the EX OR circuit 62 to the tuning voltage counter 275 as an up count command. Further, by the output of the flip-flop 61, the clocked inverter 71,
72 is selected, the AFT signal H from the frequency detection circuit 26,
L is ready for input to the AND circuits 73 and 74. Also,
The up key signal UP is a NOR circuit 63 and a NAND circuit 64.
Is input to the flip-flop 65 via. The flip-flop 65 reads the input signal in synchronization with the vertical synchronizing signal φv, holds it for one cycle (about 16 ms) of the vertical synchronizing signal φv, opens the gate of the AND circuit 69, and resets the quaternary counter 67. Hold on. This quaternary counter 67
Is reset, the output from the output terminal "3" of the decoder 79 becomes "0", and the reset state of the 64-base counter 84 is released. At this time, the clock pulse φ3 is input to the 64-ary counter 84 via the clocked inverter 91. Therefore, the 64-base counter 84 counts up by the clock pulse φ3, and the above-mentioned flip-flop
While the output of 65 is “1”, that is, eight pulse signals are output in one cycle of the vertical synchronizing signal φv. The output of the 64-ary counter 84 is sent to the tuning voltage counter 275 via the AND circuit 69 as the clock pulse signal φB. As a result, the content of the tuning voltage counter 275 becomes "+".
8 ”, and the count value is sent to the modulated wave generation circuit 277. This modulated wave generation circuit 277 is a tuning voltage counter 27
The count value of 5 is modulated into a pulse width and output to the tuner tuning voltage control circuit 29 shown in FIG. This tuner tuning voltage control circuit 29 integrates the modulated wave from the modulated wave creating circuit 277 by an integrating circuit, then amplifies and converts it into a tuner tuning voltage, and supplies it to the electronic tuning tuner 22 to change the local oscillation frequency. Let After that, the next vertical synchronization signal φv
Is given, "0" is read into the flip-flop 65 and the reset state of the quaternary counter 67 is released. Also, at this time, the signal output from the output terminal "3" of the decoder 79 is "0" as described above,
The output of the NOR circuit 83 becomes "1" and the gate of the AND circuit 69 is held open. Then, in this state, it is determined whether or not the signal L is output from the frequency detection circuit 26 as shown in step B5. That is, when the quaternary counter 67 is reset, a “1” signal is output from the output terminal “0” of the decoder 79 and input to the AND circuit 74 via the OR circuit 80. Therefore, the gate of the AND circuit 74 is opened and the AFT signal L is received. If the AFT signal L has not been sent at this time,
The count-up operation of the 64-base counter 84 is continued and the output thereof causes the tuning voltage counter 275 to be "+1" as shown in step B6 and the reception frequency of the electronic tuning tuner 22 to be increased. The processing of steps B5 and B6 is repeated until the AFT signal L is output from the frequency detection circuit 26. Then, the AFT signal L is sent from the frequency detection circuit 26, and this signal L is input to the quaternary counter 67 via the inverter 72, the AND circuit 74, and the OR circuit 78. As a result, the contents of the quaternary counter 67 are counted up to "1" as shown in step B7, and the "1" signal is output from the output terminal "1" of the decoder 79. During this time, the counting operation of the 64-base counter 84 is continued, and the output thereof outputs the tuning voltage counter as shown in step B8.
The 275 is incremented by "+1". The "1" signal output from the output terminal "1" of the decoder 79 is input to the AND circuit 73 to open its gate, and the AFT signal H can be received. As a result, from the output of the AND circuit 73, as shown in step B9, the frequency detection circuit 26 outputs the AF signal.
Whether or not the T signal H is output can be determined. If the signal H is not output, the tuning voltage counter 275 is incremented by "1" by the output of the 64-base counter 84 as shown in step B8. The processes of steps B8 and B9 are repeated until the AFT signal H is output from the frequency detection circuit 26. When the AFT signal H is sent from the frequency detection circuit 26, this signal H is output via the inverter 71, the AND circuit 73, and the OR circuit 78, and the quaternary counter 67 is set to "2" as shown in step B10. To count up. As a result, the output terminal “2” of the decoder 79 is changed to “1”.
A signal is output and the gates of the AND circuits 74 and 81 are opened. Also, from the output terminal "2" of the decoder 79 to "1"
When the signal is output, the gate of the clocked inverter 91 is closed and the gate of the clocked inverter 90 is opened, and the clock pulse φ4 having a low frequency is input to the 64-bit counter 84 instead of the clock pulse φ3 as shown in step B11. As a result, the count-up operation of the 64-base counter 84 is delayed. Further, when a "1" signal is output from the output terminal "2" of the decoder 79, the EX OR circuit 62
Becomes "0" and a down command is sent to the tuning voltage counter 275 as shown in step B12. Therefore, thereafter, when the output of the 64-base counter 84 is sent to the tuning voltage counter 275 via the AND circuit 69, the content of the tuning voltage counter 275 is decremented by "-1" as shown in step B13. Further, the output of the 64-bit counter 84 is sent to the memory 276 as the latch timing φA via the AND circuit 81, and the name of the tuning voltage counter 275 is latched in the memory 276. Further, as described above, when the “1” signal is output from the output terminal “2” of the decoder 79, the AND circuit 74
The gate is opened, and the presence or absence of the AFT signal L is determined as shown in step B14. If the AFT signal L has not been sent, the process returns to step B13 and the tuning voltage counter 27
5 is incremented by "-1". And this tuning voltage counter 27
When the AFT signal L is sent from the frequency detection circuit 26 by the count-up process of 5, the quaternary counter 67 is incremented by "1" and its count value becomes "3" as shown in step B15. Therefore, the output terminal "3" of the decoder 79 outputs a "1" signal, the output of the NOR circuit 83 becomes "0", the gate of the AND circuit 69 is closed, and the tuning voltage counter is closed.
The output of clock pulse φB to 275 is prohibited. Also,
When a "1" signal is output from the output terminal "3" of the decoder 79, the 64-base counter 84 is reset and
A one-shot pulse is output by the flip-flop 86 and the AND circuit 87. This one-shot pulse is output to the synchronization detection circuit 274 as the channel coincidence signal CH as shown in step B16. At this time, the output of the AND circuit 81 becomes "0", and the data written from the tuning voltage counter 275 to the memory 276 is fixed and held as it is, as shown in step B17. This memory 276 is supplied with an operating voltage even when the power is turned off so that the stored contents are protected. Then, the contents stored in the memory 276 are loaded into the tuning voltage counter 275 by the timing signal φC when the power is next turned on, and the count value of the tuning voltage counter 275 is held at the same value as before the power was turned off. As a result, when the power is turned on, the same channel as when the power is turned off is selected. On the other hand, when the channel matching signal CH is sent from the digital tuning control circuit 273, the synchronization detection circuit 274 shown in FIG.
The synchronization detection counter 34 is reset as shown in step B21 and the coincidence counter 32 is reset as shown in step B19. That is, the channel coincidence signal CH is input to the reset terminal R of the tuning detection counter 34 via the inverter 54, and at the same time, the flip-flops 51, 52 and the AND circuit 53 perform waveform shaping on the pulse signal of a constant width, and the OR circuit. It is input to the reset terminal R of the coincidence counter 32 via 39. This resets the tuning detection counter 34 and the coincidence counter 32. After that, as shown in step B21, it is judged whether or not the vertical synchronizing signal φv is sent from the sync separation circuit 234, and the 525-ary counter 33 is counted up until the vertical synchronizing signal φv is sent. When the vertical synchronizing signal φv is sent, the vertical synchronizing signal φv is input to the synchronizing detection counter 34 via the NOR circuit 38, and as shown in step B22, the synchronizing detection counter 34
34 is incremented by "+1". Next, as shown in step B23, it is judged whether the count value of the coincidence counter 32 is "2", that is, whether the vertical synchronizing signal φv sent from the synchronizing separation circuit 234 has a correct cycle. To do. If the vertical synchronizing signal φv has a correct cycle, the coincidence counter 32 is counted up, so that when the count value becomes “2”, the “1” signal is output from the output terminal O ₁ thereof, and the inverter 59 outputs the signal. Is sent to the flip-flop 57, and the latch with synchronization, that is, the flip-flop 57 is set as shown in step B24. Then, as shown in step B25, it is determined whether or not the content of the synchronization detection counter 34 is "7". In addition, the above step B
At 23, if the content of the coincidence counter 32 has not reached "2", the process immediately proceeds to step B25 to determine whether or not the content of the synchronization detection counter 34 has become "7". If the content of the synchronization detection counter 34 has not reached "7", the process returns to step B21 and the same processing is repeated. When the content of the synchronization detection counter 34 becomes "7", whether or not the flip-flop 57 is set as shown in step B26, that is, the count value of the synchronization detection counter 34 is "7".
It is determined whether or not the count value of the coincidence counter 32 has become "2" until it becomes. When the count value of the synchronization detection counter 34 becomes "7", a "1" signal is output from the output terminal O ₁ and is inverted to "0" by the inverter 55 and input to the NOR circuit 56. At this time, if the flip-flop 57 is set, its output signal "1" is the AND circuit 58.
Since it is input to the NOR circuit 56 via the reset signal, the reset signal output from the NOR circuit 56 is held in the “0” state.
At this time, the synchronous output of the AND circuit 58 is sent to the audio circuit as the mute signal MU as shown in step B27. The audio circuit prohibits audio output when the mute signal MU is "0", and resumes the audio output operation when the mute signal MU becomes "1". After that, when the count value of the synchronization detection counter 34 becomes "8", the output terminal O
_The "1" signal is output from ₂ and input to the NOR circuit 38,
The clock input of the synchronization detection counter 34 is prohibited. The above is the case where it is determined that the vertical synchronizing signal φv is normally received. At this time, the digital tuning control circuit 273
Stops the tuning voltage counter 275 clock, fixes the count value, and ends the tuning operation.

If the normal reception state does not occur and the count value of the coincidence counter 32 does not reach "2" until the count value of the synchronization detection counter 34 reaches "7", the flip-flop
Since 57 is not set, the output of AND circuit 58 is "0".
Held in a state. In this state, when the count value of the synchronization detection counter 34 becomes "7" and the "1" signal is output from the output terminal O ₁ , the inverter 55 inverts it to "0" and inputs it to the NOR circuit 56. At this time, since the "0" signal is input from the AND circuit 58 to the NOR circuit 56 as described above, the reset signal R output from the NOR circuit 56 is "1".
Therefore, 4 in the digital tuning control circuit 273
The decimal counter 67 is reset. Therefore, the digital tuning control circuit 273 returns to step B5 to restart the above tuning operation.

Although the case where the up key 16a is operated has been described above, when the down key 16b is operated, the operation of the down key 16b is detected in step B2, and the down processing is performed in the same manner as the case of the above-mentioned up processing.

At this time, the relationship between H and L output from the frequency detection circuit 26 and the relationship between up and down of the tuning voltage counter 275 are just the reverse of the up processing.

Next, regarding the tuning operation in manual mode,
Description will be made with reference to the digital tuning control circuit 273 shown in FIG. 9 and the flowchart of FIG. To select the desired channel in manual mode, use the up key 16a or down key for tuning.
Keep pressing 16b until the desired channel is received.
When the manual mode is designated, the digital tuning control circuit 273 constantly checks whether or not the tuning key is operated as shown in step C1 of FIG. 13, and if there is a key input, the step C2 It is determined whether or not it is the up key 16a as shown in. If the key is the up key 16a, as shown in step C3, the tuning voltage counter 27 is fed from the digital tuning control circuit 273.
Send a count-up signal to 5 and set the content to "+8".
After that, the process proceeds to step C4 and it is determined whether or not the up key 16a is continuously pressed. If the up key 16a is not pressed continuously, the process returns to step C1. If it is pressed, the process proceeds to step C5 to count 0.5 seconds. That is, in the digital tuning control circuit 273 shown in FIG. 9, in the manual mode, the "1" signal is the NOR circuit as the manual mode signal MANU.
It is input to 83, and the input from the decoder 79 to the AND circuit 69 is prohibited. When the up key 16a is operated in this state, the key control circuit 272a outputs a one-shot up key signal UP (high level), and the flip-flop 61
Is set. The set of this flip-flop 61 is E
It is sent from the X-OR circuit 62 to the tuning voltage counter 275 as an up-count command. In addition, the up key signal UP
Is input to the flip-flop 65 via the NOR circuit 63 and the NAND circuit 64. The flip-flop 65 reads the input signal in synchronization with the vertical synchronizing signal φv, holds it for one cycle (about 16 ms) of the vertical synchronizing signal φv, and holds the AND circuit 69.
Open the gate of and hold the quaternary counter 67 in the reset state. When the quaternary counter 67 is reset, the output from the output terminal "3" of the decoder 79 becomes "0",
The reset state of the 64-base counter 84 is released. At this time, the clock pulse φ3 is input to the 64-ary counter 84 via the clocked inverter 91. Therefore, the 64-ary counter 84 counts up at high speed by the clock pulse φ3, and outputs eight pulse signals while the output of the counter 65 is “1”, that is, in one cycle of the vertical synchronizing signal φv. Output. The output of the 64-ary counter 84 is sent to the tuning voltage counter 275 via the AND circuit 69 as the timing signal φB. As a result, the content of the tuning voltage counter 275 is "+8", and the count value is sent to the modulated wave creating circuit 277. This modulated wave creation circuit 277
Modulates the count value of the tuning voltage counter 275 into a pulse width and outputs it to the tuner tuning voltage control circuit 29 shown in FIG. Then, as described above, the key control circuit 272a determines whether or not the key is continuously pressed. If the key is not pressed continuously, the process returns to step C1. If the key is pressed continuously, the key control circuit 272a counts 0.5 seconds as shown in step C5, and then,
The key control circuit 272a outputs a manual key presence signal. This manual key presence signal is output while the key is pressed, and the flip-flop 65 is output via the NAND circuit 64.
Read by. The output of the flip-flop 65 opens the gate of the AND circuit 69, and the output of the 64-bit counter 84 is sent to the tuning voltage counter 275 as a clock pulse φB. As a result, the tuning voltage counter 275 is incremented as shown in step C6. Next, as shown in step C7, it is judged whether or not the key operation is continued. If the key operation is continued, the procedure returns to step C6 and the output of the 64-base counter 84 counts up the tuning voltage counter 275. Continue operation. Therefore, the AND circuit 88 is supplied with the signal M indicating the presence / absence of the synchronizing signal from the latch circuit 41 of FIG. This signal M has a high level when there is synchronization, and has a low level when there is no synchronization. When the synchronizing signal M is sent as the tuning voltage counter 275 counts up, the AND circuit 88 Becomes "1", the gate of the clocked inverter 90 opens, and the low-frequency clock pulse φ4 is input to the 64-bit counter 84. As a result, the 64-base counter 84 and the count-up operation are delayed, and the sweep speed of the tuner tuning voltage is switched to a low speed. That is, since the sync signal is detected when there is a channel, the signal M becomes a high level and the sweep speed of the tuner tuning voltage becomes slow, and when the channel leaves the channel, the sync signal cannot be detected. Becomes low level and the tuner tuning voltage sweep speed increases. Then, when the up key 16a is released when the desired channel is selected by the tuner tuning voltage sweep, the tuning voltage counter 275 is displayed as shown in step C8.
Stop counting operation. That is, the up key 16a
When is released, the key signal becomes "0" and "0" is read into the flip-flop 65. As a result, the output of the flip-flop 65 becomes "0", the gate of the AND circuit 69 is closed, and the output of the clock pulse φB to the tuning voltage counter 275 is prohibited. As a result, the tuning voltage counter
The 275 count-up operation stops and the tuning operation ends.

If the down key 16b is operated, step C2
In step C, the operation of the down key 16b is detected.
Go to 9. In this step C9, a down count command is output from the EX OR circuit 62 to set the tuning voltage counter 275 to "-8". Then, as shown in step C10, it is judged whether or not the down key 16b is continuously pressed, and if the key is not continuously pressed, the process returns to step C1. If the down key 16b is continuously pressed, the key control circuit 272a counts 0.5 seconds as shown in step C11.
Then, as shown in step C12, the tuning voltage counter 27
Count down 5. Next, as shown in step C13, it is determined whether or not the key operation is completed. If the key is still pressed, the process returns to step C12 and the tuning voltage counter 27
Continue the countdown operation of 5. When the end of the key operation is detected in step C13, the tuning operation of the tuning voltage counter 275 is stopped and the tuning operation is ended, as shown in step C8.

The set values of the counters in the control circuit 27 are not limited to those in the above embodiment, and may of course be set to other values.

Further, the present invention can be applied not only to television but also to radio and the like.

[Effects of the Invention] As described in detail above, according to the present invention, an electronic tuning tuner, an auto / manual tuning mode selecting means,
In a tuning device having an up key, a down key, and a sweep means for changing the tuning voltage of an electronic tuning tuner step by step, when the manual tuning mode is selected by the auto / manual tuning mode selecting means, the up key or the down key When operated, the sweeping means is operated, and the first step amount is set to the number of steps sufficient to get out of synchronization from the synchronized channel, and the sweeping means is stopped on the receiving channel. In mode, you can operate the up key and down key only once, and you can surely get out of the currently synchronized channel, so you do not need to operate the up key and down key again, and you can get comfortable operability, In manual mode,
The effect is that fine adjustment is possible and the sweep can be performed at high speed.

[Brief description of drawings]

The drawings show an embodiment of the present invention. FIG. 1 is an external configuration diagram, FIG. 2 is a block diagram showing an overall configuration of an electronic circuit, and FIG. 3 is a block diagram showing details of an electronic tuning tuner. 4 is a block diagram showing details of a television linear circuit, FIG. 5 is a block diagram showing details of a frequency detection circuit,
6 is a timing chart for explaining the operation of the frequency detection circuit of FIG. 5, FIG. 7 is a block diagram showing the details of the control circuit, and FIG. 8 shows the details of the synchronization detection circuit portion in FIG. Block diagram, FIG. 9 is a block diagram showing details of the digital tuning control circuit portion in FIG. 7, FIG. 10 is a flow chart showing a synchronization detection operation, and FIG. 11 is a timing chart for explaining the synchronization detection operation. FIG. 12 is a flow chart showing the auto tuning operation in the auto mode, and FIG. 13 is a flow chart showing the auto tuning operation in the manual mode. 11 …… Case, 12 …… Video display, 13 …… Channel display, 14 …… Volume display, 15 …… Display panel, 16a ……
Tuning up key, 16b ... Down key, 17
a: Up key for volume adjustment, 17b: Down key,
18 …… Auto / manual switch, 19 …… VHF
/ UHF selector switch, 20 ... power switch, 21 ... antenna, 22 ... electronic tuning tuner, 23 ... TV linear circuit, 24 ... A / D conversion circuit, 25 ... liquid crystal drive circuit, 26
...... Frequency detection circuit, 27 ...... Control circuit, 28 ...... Key input section, 29 ...... Tuner tuning voltage control circuit, 221 ...... Antenna coupling circuit, 222 …… High frequency coupling circuit, 223 …… Mixing circuit, 224 …… … Local oscillation circuit, 231 …… Intermediate frequency amplification circuit, 232 …… Detection circuit, 233 …… Video amplification circuit, 234…
… Synchronous separation circuit, 261 …… Frequency discriminator, 262,263…
… Comparator, 264, 265 …… Reference power supply, 271 …… Reference clock generation circuit, 272 …… Key control circuit, 273 ……
Digital tuning control circuit, 274 ... Synchronous detection circuit, 275 ... Tuning voltage counter, 276 ... Memory, 277
...... Modulation wave creation circuit, 278 ...... Volume display circuit / channel display circuit, 279 ...... Display control circuit, 2710 ...... 4-bit counter, 2711 …… D / A conversion circuit, 31 …… Mismatch counter, 32… … Match counter, 33 …… 525 hex counter,
34 …… Synchronous detection counter, 36, 41 …… Latch circuit, 67…
… Quaternary counter, 79 …… Decoder, 84 …… 64-base counter.

Front Page Continuation (72) Inventor Koji Yamagishi, 3-2-1 Sakaemachi, Hamura-cho, Nishitama-gun, Tokyo Casio Computer Co., Ltd., Hamura Technical Center (56) Reference JP-A-54-151316 (JP, A) Showa 57-136817 (JP, A) Actually opened Showa 57-64942 (JP, U)

Claims (1)

[Claims] 1. An electronic tuning tuner, an auto / manual tuning mode selection means, an up key, a down key,
In a tuning device having a sweep means for changing the tuning voltage of an electronic tuning tuner step by step, when the manual tuning mode is selected by the auto / manual tuning mode selecting means, while the up key or down key is operated. When the up key or the down key is operated while the auto tuning mode is selected by the means for operating the sweep means and the auto / manual tuning mode selection means, the sweep means is operated and the first step amount is increased. Is a sufficient number of steps to get out of synchronization from the tuned channel, means for stopping the sweeping means on the receiving channel, and means for determining whether or not the sweep position by the sweeping means is near the receiving channel, To the judgment means When it is judged to be near the receiving channel, the sweep speed of the sweeping means is switched to a low speed, and when it is judged not to be near the receiving channel, a means for switching the sweeping speed of the sweeping means to a high speed is provided. And tuning equipment.