JPS5915236B2 - Signal extraction pulse generator - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention is for extracting the information signal 5 inserted in a specific line after a certain part of the vertical synchronization pulse or equalization pulse within the vertical retrace period of a television signal. The present invention relates to a device for generating pulses.

The information signal includes a VIR (vertical interval reference) signal, a still image broadcast signal, a multiplexed audio signal, etc., and in the following, the VIR signal will be explained as a representative signal.

The hue, brightness, contrast, etc. of color video information tend to deteriorate while it is being delivered from the broadcasting station to the television receiver in a general home, but this is reflected in the reference signal (VIR signal) from the broadcasting station.
A ``5VIR system'' has been proposed in which the signal is corrected by 5VIR, and in the United States, a few broadcast stations are already transmitting this VIR signal by inserting it into the vertical retrace period. In the composite video signal shown in FIG.
This signal is inserted into the th line, and the VIR signal is made up of various reference signals such as a chroma reference, a luminance reference, and a black reference, as shown in FIG.

By the way, when using the VIR signal on the receiver side, it is necessary to extract this signal.One way to do this is to extract the vertical synchronization pulse from the television signal, and then extract the vertical synchronization pulse from the television signal. It is conceivable to generate a sampling pulse after a certain period of time using the time reference. ? 0 This type of device is used as a third
4, in the block diagram shown in FIG. 3, 1 is a circuit for extracting vertical periodic pulses from a television signal including a VIR signal.More specifically, this circuit is a sync separation circuit. output (composite synchronization signal) 1
Extract the vertical synchronization pulse from 5.

Note that in the synchronous separation circuit, the output pulse width increases in accordance with the amplitude of the input pulse. 2 is a means for supplying horizontal frequency pulses; 3 is a counter for counting the vertical synchronizing pulses and horizontal frequency pulses; and 4 is a means for applying horizontal frequency pulses to the counter after the counter has counted an even number of vertical synchronizing pulses. 5 means for controlling pulse supply to the counter such that the contents of the counter are VI
This circuit generates a pulse with a width of approximately 1H when the count number corresponding to the line in which the R signal is inserted is reached.

Each component of such a device, together with associated circuitry, may further include a fourth
This is embodied in the figure. This figure 4 shows the circuit configured for IC, and the capacitor C is connected to pin 1.
1 is attached externally. A composite sync pulse (see the beginning of Figure 1) obtained by passing the composite video signal in Figure 1 through a normal sync separation circuit of a television receiver is applied from pin 2 to the base of the switching transistor T. Then, the transistor T1 is turned off only during the period of the horizontal periodic pulse, the equivalent pulse, and the vertical periodic pulse (see FIG. 1A). On the other hand, a horizontal frequency pulse (for example, a flyback pulse, hereinafter referred to as ``flyback pulse'') [see Fig. 1E] is transmitted through the No. 3 pin 3 to the transistor T.
T2 is added to the base of T2 to turn on the transistor T2 only during the flyback pulse. Therefore, the differential pair T3 in which the transistors Tl and T2 operating in this manner are connected
, T4, and the base of T3 rises in potential only when both transistors T, , T2 are off, that is, during the equalization pulse and vertical synchronization pulse widths, as the capacitor C1 is charged by the power supply Cc, and during other periods, the base of T3 increases in potential. Due to the conduction of T1 or T2, the charge accumulated in the capacitor C1 is discharged through T1 or T2, so that the capacitor C1 becomes approximately at ground potential. Note that since the equalization pulse and the vertical synchronization pulse have different pulse width periods, the base potential rise of the transistor T3 also differs accordingly. Figure 1C shows this situation, with T,,T
Level E during the vertical synchronization pulse width period with a long off period of 2.
2, but only reaches level E1 during the short equalization pulse period of the off period. Here, set the base bias of the other T4 of the differential pair to R6El<? ×Vcc<E2
If R6+R7 is selected so that R6+R7 is selected, a pulse of positive polarity approximately in accordance with the vertical synchronizing pulse appears at the collector of the transistor T4.

This pulse turns off the next stage transistor T5 and produces a negative pulse at the voltage division point a on its collector side.

That is, the transistor T5 normally turns on when the base potential drops due to the conduction of T4, and the point a is at a constant high level potential, but as mentioned above, when a positive pulse appears at the collector of the transistor T4, it turns off. This is because point a becomes the ground potential. Six pulses are generated at point a according to the large sawtooth wave voltage shown in FIG. Therefore, only two are shown in FIG. 1-2. The transistors T, -T5 and their associated resistors and capacitor C1 constitute a vertical synchronizing pulse extraction circuit 1 in FIG. Incidentally, the Zener diode Dz connected to the second pin 2 was introduced as a noise countermeasure. Next, the counter 3 is constructed by connecting five T flip-flops, and in the figure, only one T flip-flop, F, is specifically shown, and the others are shown only as blocks F2, F3, F4, and F. However, they all have the same circuit configuration. T flip flop F
Initially, S, is controlled by a set pulse so that S, is at a low level, so T,l is off and Tl2 is on, and the emitter current of T,2 flows to ground through T7, but as mentioned above. When the negative pulse generated at point a of the vertical synchronization pulse extraction circuit 1 is applied to the transistors T7 and T8, these transistors T7 and T8 are turned off, and the emitter current of Tl2 cannot flow through the collector and emitter of T7. , flows into the base of T9. Therefore, T, turns on, and as the base-emitter bias of Tll increases, the T flip-flop reverses its state, and Tl, turns on.
Tl2 is turned off. In this way, the inversion operation of Tl, Tl2 is performed every time a negative polarity pulse is input to T7 and T8. When the counter 3 counts two input pulses, the emitter of the first decoder transistor Tl3 becomes a high and high level input signal, turning on the transistor Tl4 connected to its collector. For this reason,
In flip-flop F6, Tl5 is on and T,6 is off. Then, as Tl6 turns off, T6 turns on, so as mentioned earlier, the pulse generated at the collector of the transistor T4 forming the differential pair is invalidated and will not be added to the counter 3. . however,
The other transistor Tl5 of the flip-flop F6
As Tl7 turns off and Tl8 turns on, flyback pulses from pin 3 are successively applied to the counter 3 through Tl8. Thus, the first two T-flip-flops Fl9F29F39F49F5 of counter 3 are applied with vertical sync pulses, followed by flyback pulses.
The first output of is Sl, S2, S3, S4, S5 in Fig. 1.
become that way.

Although the flyback pulse is added to the counter after counting two vertical synchronization pulses, it is not necessary to limit the number of vertical synchronization pulses to be counted to two;
It may be 4 or 6, as long as it is an even number. However, if an odd number of counts is used, a malfunction will occur in either the even field or the odd field, which must be avoided. For example, as shown in Fig. 5, when counting only one vertical period pulse, in an even field, the flyback pulse H and the extracted vertical synchronization pulse N are approximately at the same position, so counter 3 is counted. The input pulse is as shown in Figure 2. However, in odd-numbered fields, the extracted vertical synchronization pulse is shifted from the repeating position of the flyback pulse, so the pulse input to counter 3 is 1 as shown in Figure 2. It becomes more and more. When a VIR signal extraction pulse is generated, it is generated by a fixed number of counters from the start pulse, so if it is done as shown in Fig. 5, there is a problem that the IR signal will not be extracted in one of the fields. result. In this point,
If the flyback pulse is added to the counter after counting an even number of extracted vertical synchronization pulses, the number of counts up to the line where the IR signal is inserted will be the same for both the even and odd fields, and as described above, either one There is no risk of malfunction occurring in the field.

However, if two of the even numbers are selected, there is an advantage that reliable operation can be expected even in a weak electric field. In other words, when the electric field is weak, the vertical synchronization pulse obtained from the synchronization separation circuit tends to collapse from the third pulse onwards, as shown in Figure 6, but the pulses are quite stable up to the first two pulses. It is. A circuit 5 that generates an IR signal extraction pulse when the counter 3 to which pulses are input in this manner counts a predetermined number of pulses includes a second decoder transistor T33, transistors T35 and T36 connected to the collector of the second decoder transistor T33, and transistors T35 and T36 connected to the collector of the second decoder transistor T33.
7, T38.

The emitter of the second decoder transistor T33 is connected to receive the outputs Sl, g2, g3, K4, and S5 of the counter 3, and therefore, as can be seen from the waveform shown in FIG. T at the count number
Since the inputs of 33 are all at high level, the second decoder transistor T33 is turned off, so the transistor T35 connected to its collector is turned on, and T36 is turned off, so that the voltage at point b corresponds to about 1H. A negative gate pulse (see FIG. 1) is generated. Since the transistor T37 is turned off at the same time, the transistor T38 becomes conductive and generates a positive gate pulse corresponding to approximately 1H at its emitter. It should be noted that whether to generate positive or negative gate pulses in this way should be decided based on the relationship with the subsequent circuit (not shown), and therefore it may be sufficient to use only one of the gate pulses. Needless to say. The second decoder transistor T33 is 2
At a point other than 17 counts out of one count pulse, at least one of the emitter inputs becomes low level and conducts, so that all the circuit states after the transistor T35 connected to the collector are reversed. , the aforementioned gate pulse does not appear. Further, the transistor T35 connected to the base is given a flyback pulse from pin 3 (FIG. 1(e)) and becomes conductive only during the period of the flyback pulse. Since the base is brought to ground potential, the duration of the flyback pulse corresponds to decoder T33 becoming substantially inactive. Therefore, the gate pulse generated at each emitter of transistors T36 and T38 by 17 counts has a period of 1H excluding the flyback pulse width. The reason why the decoder T33 is made inactive only during the flyback pulse period is as follows. Generally, a counter can be made into a synchronous counter by taking feedback using an AND circuit, etc.
The synchronous counter inevitably has a complicated configuration.
For this reason, it is advantageous to employ an asynchronous counter as shown in FIG. 4, but such an asynchronous counter causes a time delay for each bit. FIG. 7 shows as an example the first output waveform of each T flip-flop at the point where the counter 3 has counted 16 pulses, and the changes in S2 to S5 that change according to changes in S1 are shown by dotted lines. As shown in the figure, a time delay occurs, albeit slightly. There is a risk that the second decoder transistor T33 may malfunction within the signal delay time and generate a gate pulse at an unnecessary location. Therefore, a flyback pulse that includes such a delay time is used to make the second decoder transistor T33 inoperable only during the pulse period. This eliminates malfunctions caused by minute time delays that occur in asynchronous counters, and even if the flyback pulse period is inactive, the resulting gate pulse has a width sufficient to extract the VIR signal. No problem. Incidentally, in order to eliminate the influence of the time delay of such an asynchronous counter, a similar configuration is applied to the third decoder transistor T3l, which will be described later, and also to the first decoder transistors T, T3, which have already been described. It has been adopted as shown in . Third decoder transistor T3l and transistors T3O, T2, , T2 connected to its collector
8, T2, and T2 are provided to terminate the pulse input to the counter 3 at a certain number or more, and if there is no means to interrupt the pulse input to the counter in this way, the subsequent counter Due to the operation of 17
This is because the same count content as the count content of 1 is also exhibited during the scanning period, so that gate pulses are generated periodically at unnecessary times. The third decoder transistor T3 is the Sl of each T flip-flop of the counter.
, ,S3, g4, and S are connected to the counter so as to be input to the emitters, and therefore become non-conductive at the time of 21 counts. Accordingly, T3O is on, T2
, is off, T28, T2, , T2l are turned on, lowering the collector potential of Tl6 constituting flip-flop F6, and therefore the base potential of Tl5, and turning off Tl5.
6 is turned on to invert the state of the flip-flop. Therefore, switching transistor Tl7 is turned on.
T, 8 is turned off, and the flyback pulse from pin 3 is no longer supplied to counter 3. A transistor T related to the output of the third decoder transistor T3.
The emitter of 27 is a switching transistor T22~
T26 are connected in parallel as shown, and as T27 becomes conductive, these transistors T22 to T26 also become conductive, setting their respective collectors to a low level. This means that each of the flip-flops F2 to F5 constituting the counter 3 is reset and their first outputs S1 to S5 are brought to the initial state of low level. In FIG. 1, the symbol H indicates the reset pulse in this case. Considering that if the reset pulse is too short, the counter 3 will not be able to follow it, a small capacitor C2 is inserted at the bottom of the transistor T28. The charge in the capacitor C2 charged by the conduction of the transistor T28 flows through the base-emitter impedance of the next stage T27, so the discharge time constant is large. In other words, with this circuit configuration, only a small capacitance needs to be created within the IC.

As mentioned above, by using the apparatus shown in FIGS. 3 and 4,
Using the vertical synchronization signal as a time reference, a predetermined signal sampling pulse can be generated after a certain period of time.

However, what is important here is that only the vertical synchronizing pulse must be extracted correctly in the vertical synchronizing pulse extraction circuit, but when switching channels, etc., the composite video signal must be extracted in the synchronizing separation circuit of the television receiver. The vedestal level inside fluctuates greatly,
A pseudo pulse is generated, although it is slightly wider than the vertical synchronization pulse, and this becomes ringing and tails, so this pseudo pulse is extracted by the vertical synchronization pulse extraction circuit 1, and this pseudo pulse is used as a reference. In this case, the above-mentioned circuit will work and malfunction will occur. Furthermore, if noise exceeding the level of the vertical synchronizing pulse is input to the synchronization separation circuit during normal reception, the synchronization separation circuit outputs a wide pulse, and this pseudo pulse also causes the above-mentioned malfunction.

The present invention proposes a signal extraction device devised to prevent such malfunctions.

That is, as shown in FIG. 8, the present invention includes a circuit 6 for detecting noise exceeding a predetermined level in the video detection output, and uses the output of this circuit to reset the counter 3. be. FIG. 9 shows a specific embodiment of the detection circuit 6, which has a configuration using a VIR killer signal generation circuit. This is because the device shown in FIG. 4 described above (represented by 11 in FIG. 9) and the IR killer signal generation circuit 13, which occupies most of FIG. 9, are housed in the same IC chip. This is because it is advantageous to use this circuit 13, and as will be understood from the explanation below, changes in the composite video signal due to the pseudo pulses can be directly applied to this circuit 13. Thus, in the embodiment of FIG. 9, diode D is used to form the detection circuit.

and PNP transistor Q. It is only necessary to connect them to the VIR killer signal generation circuit 13 and the VIR signal extraction pulse generation circuit 11 as shown. Incidentally, before explaining this detection circuit 6, the VIR killer signal generation circuit 13 will be explained briefly.
I will explain about it. The VIR killer signal generation circuit 13 receives a video signal from a video detection circuit (not shown) through a capacitor CC externally connected to a terminal pin 14, which is connected to a transistor Q1.
The polarity shown in FIG. 1 is applied to the base of the circuit.

This video signal is inverted by the transistors Ql and Q2, and the chroma frequency component is removed through the capacitor C2 connected between the emitter of Q2 and the ground.
The video signal applied to the base of transistor Q4 is the first
It will look like Figure 0. First and second transistors Q4, Q
A constant current source transistor Q6 is connected to the commonly connected emitters of the transistors Q6, and the gate pulse of positive polarity (see FIG. 10C) is applied to the base of the constant current source transistor Q6. The base of the second transistor Q5 is connected to a constant potential point +EO
The collector is connected to one end of a capacitor C1 inserted into the video signal supply path as shown. On the other hand, the collector of the first transistor Q4 is connected to the power supply +Cc via a resistor Rt. Furthermore, the first transistor Q
4 is connected to the emitter of a PNP transistor Q7 that outputs different pulses depending on the level setting of the signal at the base.
The base of is connected to the base of the second transistor Q4.

Further, the collector of the PNP transistor Q7 is connected to the collector of a transistor Q8 as a combining means, although it is connected through a resistor R9. First, the operation of the circuit up to this point will be explained. Now, when the gate pulse [Fig. 10C] is applied to the base of the constant current source transistor Q6, Q5 is turned on, and current flows through the second transistor Q5 as shown by the arrow, and the capacitor C'1 is connected as shown in the figure. to charge. Here, the hot side of the capacitor C'1 is connected to the video detection circuit, and the current flows from the power source at that point. As the capacitor is charged, the video signal (VIR signal in this case) shown in FIG. 11 moves upward, and the DC level Ex of the chroma reference signal reaches E as shown in FIG.

is made to match. This is because as the capacitor CC is charged, the base potential of Q1 decreases and the conduction bias of Q1 becomes deeper, and the emitter currents of Q2 and Q3 increase, resulting in a back electromotive force generated in the resistor, that is, a back electromotive force of the first transistor Q4. This is because the base potential rises, and this rise causes the chroma DC level to rise to E as shown in FIG. Q4 in accordance with
, Q5 are carried out until the equilibrium state is maintained. The PNP transistor Q7, which receives the video signal (in this case the IR signal part) whose DC component has been reproduced from the base of the first transistor Q4, has its base set to EO as well as the base of the second transistor Q5. The DC level of the chroma reference signal (E due to the DC component regeneration mentioned above).

It is off during the period (at the same potential as EO), and is on during the luminance reference and black reference signal periods, which are higher in level than EO, and its collector becomes a high potential. Therefore, a signal as shown in FIG. 102 is generated at the collector of the PNP transistor.

This signal is combined with a gate pulse applied to the base of the transistor Q3 inserted between the collector of the PNP transistor Q7 and the reference potential point. That is, the base of the transistor Q8 is normally supplied with a constant conduction bias from the circuit 11 and is turned on, and its collector is held at a low potential, but the 19th line of each field is connected to the circuit shown in FIG. Since a gate pulse of negative polarity is applied to the base, Q8 is off during this period, and its collector is not grounded. Therefore, the PN
When combined with the pulse shown in FIG. 10 2 which is the output of the P transistor Q7, a pulse as shown in the same figure is obtained.

In response to this pulse, a state is created in which the transistor Q, in the subsequent circuit is turned on, QlO is turned off, and Ql, , Ql2 are turned on. The emitter current of the turned-on transistor Ql2 connects the capacitor C3 to one side of the differential pair Ql3 at the next stage.
Charge to a sufficient potential to turn on. Note that this charging stops after the pulse has elapsed, so the capacitor C'3
The charge flows through the resistor Rl5, but this discharge time constant is long, so the potential of the capacitor C'3 is maintained at a value sufficient to turn on Ql, until the next VIR signal.

Note that diodes D'1 and D'2 are connected in opposite directions between the bases of the differential pairs Ql3 and Ql4, as shown in the figure.
It is designed to efficiently charge the capacitor Ct and prevent overcharging. That is, in the state where the pulse (see FIG. 10) is not received, the transistors Q and 2 are off and the capacitor c'S. is not charged by the emitter current of Ql2, but in this case, since the capacitance of the capacitor C'3 is selected to be large, the potential of the capacitor is determined by the current during the pulse (see Figure 10). It is difficult to raise the potential. Therefore, before the charging current based on the pulse flows, the power supply (+Vc
c) → Resistor R120 → Diode Dt → Capacitor C'
The capacitor C'3 is charged through the path No.3. In this case, Q
l3 is never turned on. That is, diode D1 has Q
This is because the base potential of Ql3 is held lower than that of l4. In this way, the potential of the capacitor Ct, which is previously held at a lower potential close to the conduction potential of Ql3, can easily make Ql3 conductive by the emitter current of the transistor Ql2 flowing during the pulse period (see Fig. 10). It is raised to a potential level. The other diode D2, which is connected in the opposite direction to the diode Dt, becomes conductive when the capacitor C'3 is overcharged to a predetermined value or more, and passes the emitter current of the transistor Ql through the resistor to the reference potential point. It serves as a drain. As mentioned above, the arrival of the pulse (see FIG. 10) causes one of the differential pairs Q, 3, Ql4, Ql3, to remain conductive for at least one field period, thus preventing reception of the television signal comprising the VIR signal. In the case of , the pulses [see Fig. 10] are generated every field, so Ql3 of the differential pair is turned on one by one, and the transistors Q and Q1 connected to their collectors are turned on.
, , Ql6 is made conductive. Therefore, a positive voltage is obtained at point A. At this time, the differential pair Q and 4 are turned off, and the transistors Ql7 and Ql8 connected to their collectors are turned off. Therefore, the emitter current of Ql8 does not flow. By the way, when the potential at the point A becomes high level, the transistors Q, . conduct, lighting up the light emitting diode D'3 to indicate that the automatic adjustment circuit 12 using the VIR signal is in operation, but the collector of Ql9 is almost at the reference potential (earth potential), so the potential at point B is at a low level. In this way, when the potential applied to the automatic adjustment circuit 12 through the line 1 is high enough and the signal applied through the line 12 is low, the automatic adjustment circuit 12 is activated, and conversely, as will be described later, the automatic adjustment circuit 12 is activated. low, track 2
If side 2 is high, it is inactive. However, depending on the configuration of the automatic adjustment circuit 12, it goes without saying that it is sufficient to use only one of the lines. Next, we will explain the operation when a television signal without a VIR signal inserted is received. First, even in this case, the pulse generating circuit 11 generates a gate pulse as shown in the figure for the lines 13 and 14 on the 19th line of each field. Therefore, the differential amplifier 15 and the transistor Q8 as a pulse synthesizing means both operate, but the above-mentioned pulse (see FIG. 10) is not generated. That is, the 19th line in each field of the television signal to which the VIR signal is not inserted is at the pedestal level as shown in FIG.
For DC regeneration by L, the pedestal level is E as shown in Fig. 11 111. is set to Therefore, the video signal applied to the emitter of PNP transistor Q7 during the gate pulse period is E. and the PNP transistor Q
No bias is applied to turn on 7. Therefore, no pulse is generated at the collectors of transistors Q7 and Q8, and the states of the subsequent circuits are Q, off, QlO on, and Q
,,,Q,2 turns off, and the differential pair Ql3, Ql4 becomes Ql
3 is off, Ql4 is on, and the signal content given to the automatic adjustment circuit 2 through lines 1, 12 is the above-mentioned V.
The opposite is true when the IR signal is present, and the automatic adjustment circuit 2
becomes inactive.

At this time, the transistor Ql, is kept off, so the light emitting diode D! 3 does not light up. In the above description, the pulse generated at the collector of the PNP transistor Q7 is combined with the gate pulse during the gate pulse period (i.e., the 19th line period of each field).
This is to prevent the PNP transistor from being turned on and generating a pulse even by a video signal during a scanning period, for example, during a period other than that, causing a malfunction. As described above, in the television receiver which extracts the VIR signal from the television signal and performs various automatic adjustments, the circuit 13 disables the circuit that performs the automatic adjustment when the IR signal is not sent. , VIR signal is being sent, it is possible to suitably and reliably generate a signal for activating the VIR signal. A switching diode D is connected to the power supply (+Vcc) line of the VIR killer signal generating circuit 13.

Connect the anode side of the PNP transistor C to the emitter of the transistor Q1. Connect the base of the PNP
Transistor Q. emitter and the switching diode D. The operation of the detection circuit 6, which is connected to the cathode of , is as follows. Now, when the video detection output level drops significantly due to channel switching, etc., the degree of conductivity of Ql and Q2 increases, and the voltage drop of RZ increases, and the voltage drop becomes 2V.
When f exceeds f (f is the rising voltage of the diode), the switching diode D is activated.

and PNP transistor Q. turns on. That is, PNP transistor Q. Since the emitter-base voltage required for conduction is equal to f, the voltage across resistor R'2 [therefore, D.
anode and Q. D when the base-to-base voltage] becomes 2f or more. , QO is conductive. PNP transistor Q
. The collector current is applied to the VIR signal extraction pulse generation circuit 11 to reset the circuit 11. Specifically, it may be added to the emitter side of the transistor T27 shown in FIG. In this way, the base potential of each of T22 to T26 rises and T22 to T26 become conductive, their collectors are grounded, and the flip-flops F1 to F5 are brought into the reset state. At the same time, transistors T2 and T2 are turned on, and T15 is turned on. Off, Tl7 turns on and pin 3
The horizontal frequency pulse input from the transistor Tl7
This is because the voltage flows to the ground due to the voltage and is not substantially supplied to the counter 3. Therefore, even if the VIR sampling pulse generator 11 once starts counting by using the pseudo pulse, it will not be immediately reset and generate a sampling pulse.

Note that the detection circuit 6 does not operate unless an input that makes the voltage across the resistor R equal to or higher than 2Vf is applied to the terminal 14, so under normal conditions, the IR signal extraction pulse generator 11 and the VIR killer signal generator 13 are operated as normal. Perform the action.

However, even under normal conditions, the voltage across the resistor R2 is
If noise that increases the value above f comes in, the counter is reset in the same way, so even if a pseudo pulse due to the noise is given to the counter from the synchronization separation circuit, no malfunction will occur.

As described above, the present invention provides a means for detecting the arrival of an undesired pseudo pulse when an undesired pulse (including one whose width is considerably wider than the vertical synchronizing pulse) that imitates a vertical synchronizing pulse is input. Since the detection output is used to reset the means for generating the sampling pulse, malfunctions occur in the device that generates the sampling pulse after a certain period of time using the vertical synchronization pulse as a time reference. The present invention has the great effect of being able to prevent this, making it extremely useful.

[Brief explanation of the drawing]

Fig. 1 is a diagram of various signal waveforms of the signal sampling pulse generator, Fig. 2 is a waveform diagram showing details of the VIR signal, Fig. 3 is a block circuit diagram of the device, and Fig. 4 is the specific circuit of Fig. 3. figure. FIG. 5, FIG. 6, and FIG. 7 are explanatory waveform diagrams. FIG. 8 is a block circuit diagram of the signal extraction pulse generator of the present invention, FIG. 9 is a concrete implementation circuit diagram thereof, and FIG.
11 and 12 are explanatory diagrams of FIG. 9. 1
・・・・・・Vertical synchronization pulse extraction circuit, 2・・・・・・
horizontal frequency pulse supply means, 3...counter,
4... Circuit for controlling pulse supply, 5...
...Pulse generation circuit, 6...Detection circuit, 11.
...VIR signal extraction pulse generation circuit, 12.
・・・・Hakudo adjustment circuit, Ldan・・・・VIR killer signal generation circuit.

Claims (1)

[Claims] 1. A vertical sync pulse extraction circuit that extracts a vertical sync pulse from the output of a sync separation circuit whose output pulse width increases as the input pulse amplitude increases, and a horizontal pulse generator that generates a horizontal pulse synchronized with the horizontal sync pulse. , a counter, and a counter to which a vertical synchronizing pulse is first supplied to the counter, and after the counter has counted a predetermined even number of vertical synchronizing pulses, the horizontal pulse is applied to the counter instead of the vertical synchronizing pulse. In a signal sampling pulse generation device having a pulse supply control means for controlling pulse supply and a pulse generation circuit for generating a sampling pulse when the counter has counted a predetermined number, the level of the signal sampling pulse is higher than the level of the vertical synchronization pulse among the video detection outputs. A detection means for detecting noise exceeding a predetermined level is provided, and the output of the detection means resets the counter and controls the pulse supply control means to cut off the supply of the horizontal pulse. A signal extraction pulse generator characterized by: