JPS58151650A - Information processing device - Google Patents

Abstract

PURPOSE:To reduce a manufacturing cost, to make a device small-sized, and to improve its reliability, by writing irrespective of firmware information and hardware information, and simultaneously, setting them into a logic part which requires hardware information. CONSTITUTION:When a control instruction is issued, a microprogram is read out to a register 201 from a main storage device, and control information is written in a memory 202. On the contrary, when a store control instruction is issued, the microprogram sets address information to a register by a path 215, reads out control information to the register 201 from the memory 202, and writes it in the main storage device through a path 213. At the point of time when hardware information to logic parts 300, 400 is written in the memory 202, a decoder 205 outputs a signal to only corresponding paths 216, 217, and its hardware information is simultaneously set in order to registers 301, 401 of the logic parts 300, 400, too.

Description

DETAILED DESCRIPTION OF THE INVENTION Object of the Invention The present invention relates to an information processing apparatus, and more particularly to an improvement in a hardware configuration related to setting and holding of control information for controlling the operation of an information processing apparatus.

The operation mode of a conventional information processing apparatus is controlled by a monitoring program setting various kinds of control information that defines the operation mode in the information processing apparatus and reading out the setting state. It is a common operation of an information processing device that a command word for this purpose is prepared, and that registers within the information processing device can be set and read by the command word.

Such control information can be roughly divided into two types. That is, there is information that is accessed only by a microprogram that controls the operation of the information processing device (formware information), and information that is used at an electrical level as a manual signal for logic gates (hardware information).

Now, in conventional information processing devices, registers consisting of flip-flops using logic gates are provided in a concentrated manner in a specific logic section, and both firmware information and hardware information are set in these registers. The hardware information is supplied from this logic section to other logic sections through an interface line. An example thereof will be explained with reference to FIG.

In the figure, it is one logical unit within the 1ll-i information processing device. Within this logic section, 12.13.14
is a register that stores secondary j information, and is accessible from the operation register 11 of the microprogram. Setting control information to registers 12.13.14 is as follows:
This can be done register by register sequentially via path 111, and only read from registers 12, 13, 14
12, the data can be sequentially read out to the data/meta 11. At the bladder removal path 110 from the main memory according to the command,
The storage of Q to the main memory according to an instruction is performed in a path 118.

All bytes of register 12 and some bytes of register [3 are hardware information. The output signal of each of these bytes is provided via paths 116, 118 to other logic (not shown) that requires it.

Such a conventional configuration has the following drawbacks. First, control information is stored in registers consisting of flip-flops without distinguishing between firmware information and node-ware information, but such flip-flops require many expensive logic gates with low integration. . Also,
The number of interface lines and connection pins for distributing hardware information to each logic section increases.

These impede improvements in the degree of integration and miniaturization of the logic section including the above-mentioned registers, as well as other logic sections, and as a result, impede improvements in the reliability, miniaturization, and miniaturization of the entire information processing device. It becomes. In particular, recent information processing devices contain a significant amount of control information.
7, and the impact of the above-mentioned drawbacks is increasing.

OBJECT OF THE INVENTION An object of the present invention is to eliminate the drawbacks of the prior art as described above.
The purpose of the present invention is to provide an information processing device.

Among the control information, the firmware information is referenced only by the microphone (3) Roboprogram, so there is no need to store it in flip-flops using logic gates like hardware information, and it is easy to use for highly integrated RA.
There is no problem even if M holds it.

In view of this point, in the present invention, R and AM that can be accessed from a microprogram are provided in a specific logic section within the information processing device, and the control information is firmware information...
- This information is stored centrally in AM without distinguishing it from hardware information. Also, seven lip-flops for holding hardware information are distributed and provided in individual logic units that require it. Then, the control information is converted into the above l(
When writing to AM, hardware information is simultaneously set to flip-flops in the logic unit that require it.

Embodiment of the Invention FIG. 2 is a block diagram showing an example of an information processing apparatus according to the invention, and parts other than the main parts related to holding control information settings are omitted.

200, 800, and 400 are (4) logical units within the information processing device, and are physically independent from each other.

Inside the logic unit 200, there is an RA for storing control information.
M202 is provided. This RAM 202 can be accessed by a microprogram that controls the operation of the information processing device. In the other logic section 800°400,
Registers 801, 401 are provided to hold its own necessary hardware information. These registers 801 and 401 are composed of flip-flops using logic gates, and in this embodiment, register 8
01 has a size of 8 bytes, and 7 stars 401U2 bytes.

When a load control instruction is issued, the microprogram passes the control configuration from main memory (not shown) to
10 to register 201 (8 bytes), and address information to register 201 (8 bytes) via path 215.
04 and write the control information to the I-tOM 202 via the path 211. 203, address register 2
Decode the address information set to 04 and store it in the RAM.
202. Conversely, when a store control instruction is issued, the microprogram passes pass 2.
At step 15, address information is set in the register 204, and the RA
Register 20 from M202 via all control information buses 212
1 and writes it to main memory via path 218.

In addition, when R, A M 202 is mixed, shi/meta 201
The control information within is also sequentially sent to the path 212 one byte at a time.

In the RAM 202, addresses for hardware 1 share information for the logic units 300 and 400 are allocated in advance. In order to detect the writing of control information () - hardware information) to this address (2. A decoder 205 that decodes the address information in the register 204 is provided in the logic unit 200. Hardware for the logic unit 800 At the point when the information is enriched in )t A M 202, the decoder 205 sends the corresponding path 216
Outputs a signal only to Similarly, when the hardware information for the logic unit 400 reaches l(0M202), the decoder 205 decodes the path 217 corresponding to the logic unit 400.
Outputs a signal only to

Registers 801 and 40 in logic units 2100 and 400
It is connected to the connection pin of the path 214 of the logic unit 200 through the information manpower paths 310 , 410 U of 1, connection pins, and interface paths 501 , 508 , respectively.

A control path 811 for the control registers 301 and 401,
411 is the path 50 for the connection pin and ink face.
2° 504, the output path 21 of the de=1-da 205
6,217 connection pins, respectively.

When the hardware information for the logic section 800 is written to the RAM 202, the hardware information is simultaneously set to the register 301 one byte at a time. Similarly, when hardware information 1 (A M 202) for the logic unit 400 is written, the hardware information is also sequentially set in the register 401 one byte at a time.

Note that although only two logic units to which hardware information should be supplied are shown, there are generally many similar logic units or more.

Effects of the Invention Since the present invention is as described above, it is possible to provide an excellent information processing device having the following advantages.

Conventionally, firmware information and software information were
This was previously held by flip-flops using logic gates that were concentrated in specific logic sections, but since this was replaced with RAM, which is easy to integrate, a high degree of integration was obtained for the firmware information. 〈The number of expensive logic gates is reduced. Moreover, the number of expensive logic gates is reduced.
Since the flip knobs are distributed and provided in individual logic sections that require them, concentration of logic gates for constructing the flip knobs can be avoided. Therefore, the degree of integration of a particular ethics department will not be significantly reduced, and the number of interface lines can also be reduced, making it possible to reduce manufacturing costs, downsize, and improve reliability of the information processing device.

In addition, the hardware information and firmware information are stored all at once in a RAM that is provided in a specific logic unit and can be accessed by a microprogram. Transfer to the department. Therefore, compared to the case where the hardware information is simply distributed and stored in each logic unit, reading and writing of the control information using the Urarashi language can be performed intensively at the quotient speed. Therefore, the information processing apparatus according to the present invention is also superior in terms of processing speed.

[Brief explanation of the drawing]

FIG. 1 is a block diagram for explaining a conventional news processing apparatus, and FIG. 2 is a block diagram showing only the essential parts of the information processing apparatus according to the invention. 200, 300.400...Logic section, 202...Side 1] RA for Goho Kakukasu~1.205...Decoder for detecting writing of hardware information, 301,401...
Registers for holding hardware information (flip knob group).

Claims (1)

[Claims] (]) In an information processing device (=, a random access memory (RAM) that can be accessed by a microprogram that controls the operation of the information processing device is provided in a specific cooking section of the information processing device, and the microprogram controls the operation of the information processing device). Control information that is only referenced and control information (hardware information) that is directly used by individual logic units in the information processing device are written to the FLAM without distinction, and a Seven lip-flops consisting of logic gates are distributed within each logic section,
) At the same time as writing the hardware information to tAM,
An information processing device characterized in that the hardware information is set in the flip-flop in the logic unit that requires it.