JPS5730019A - Information processing device - Google Patents

Information processing device

Info

Publication number
JPS5730019A
JPS5730019A JP10481980A JP10481980A JPS5730019A JP S5730019 A JPS5730019 A JP S5730019A JP 10481980 A JP10481980 A JP 10481980A JP 10481980 A JP10481980 A JP 10481980A JP S5730019 A JPS5730019 A JP S5730019A
Authority
JP
Japan
Prior art keywords
address
high speed
signal
written
information
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP10481980A
Other languages
Japanese (ja)
Inventor
Takao Tanaka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Fujitsu Ltd
Original Assignee
Fujitsu Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Fujitsu Ltd filed Critical Fujitsu Ltd
Priority to JP10481980A priority Critical patent/JPS5730019A/en
Publication of JPS5730019A publication Critical patent/JPS5730019A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/20—Handling requests for interconnection or transfer for access to input/output bus
    • G06F13/28—Handling requests for interconnection or transfer for access to input/output bus using burst mode transfer, e.g. direct memory access DMA, cycle steal

Abstract

PURPOSE:To increase average processing speed, by using memories which are possible for high speed operation in the relation with an input and output device. CONSTITUTION:A decoder DEC decodes an address given from a controller which controls DMA, and when the high-speed mode is selected, clocks CLs 1, 2 are made to high speed and written in a high speed side memory with a read/write switching signal R/W and a memory data register MDR. When the accessing is finished once, a signal is outputted to an information MS to produce the next address and the next information is written in an F-RAM. When a readout is made with DMA system and display is made on e.g. a cathode ray tube CRT, the signal R/W is switched and a memory MEM is selected through the provision of an address and operation is made to provided the next address.
JP10481980A 1980-07-30 1980-07-30 Information processing device Pending JPS5730019A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP10481980A JPS5730019A (en) 1980-07-30 1980-07-30 Information processing device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP10481980A JPS5730019A (en) 1980-07-30 1980-07-30 Information processing device

Publications (1)

Publication Number Publication Date
JPS5730019A true JPS5730019A (en) 1982-02-18

Family

ID=14391004

Family Applications (1)

Application Number Title Priority Date Filing Date
JP10481980A Pending JPS5730019A (en) 1980-07-30 1980-07-30 Information processing device

Country Status (1)

Country Link
JP (1) JPS5730019A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59157734A (en) * 1983-02-25 1984-09-07 Canon Inc Data transfer system

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59157734A (en) * 1983-02-25 1984-09-07 Canon Inc Data transfer system

Similar Documents

Publication Publication Date Title
JPS6462743A (en) Memory access controller
JPS57196677A (en) Storage device for character graphic information
JPS5730019A (en) Information processing device
TW226468B (en)
JPS56156978A (en) Memory control system
JPS5616980A (en) Write-in system of one-bit of memory
JPS54145444A (en) Control system of buffer memory
SU765878A1 (en) Long-time memory
JPS5737795A (en) Read-only memory element
JPS57109177A (en) List processing system
JPS5533282A (en) Buffer control system
KR940001160A (en) Signal processing structure to preselect memory address data
JPS6413621A (en) Register selecting circuit
JPS56137447A (en) Information processor
JPS58151650A (en) Information processing device
JPS54104246A (en) Memory system
JPS5658114A (en) Data delaying device
JPS5654678A (en) Memory control system
JPS5771044A (en) Data buffer control system
JPS5555495A (en) Dynamic mis memory circuit
JPS5764389A (en) Data output reversing circuit of semiconductor memory device
JPS56137424A (en) Buffer memory device
JPS5611535A (en) Data input and output control system
JPS5614773A (en) Decoding circuit for compressed picture
JPS56114055A (en) Bulk transfer speed converter