JPH0444148A - Address assigning device - Google Patents

Abstract

PURPOSE:To attain the assignment of addresses to the peripheral devices from a central controller by writing successively the addresses into the storage means of the peripheral devices of plural stages connected to the central controller via a bus. CONSTITUTION:A central controller 14 outputs a write signal and a write enable signal to its own write output terminal and enable output terminal respectively and at the same time outputs a data signal to a bus 13. Each of peripheral devices 16 - 22 receives a write signal through a write input terminal in a valid period of the write enable signal received through an enable input terminal and then writes the data signal received from the bus 13 into each of storage means 16a - 22a respectively. At the same time, the write enable signal received through the enable input terminal is transmitted through the enable output terminal. Therefore the write enable signal passes successively through the enable input terminal and the enable output terminal of each of devices 16 - 22. Thus the contents of the data signals written into the means 16a - 22a of the devices 16 - 22 are used as the addresses of these devices 16 - 22.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention relates to an address assignment device in which an address is assigned by a central controller to each of a plurality of stages of peripheral devices connected to the central controller via a bus.

[Prior Art] FIG. 4 is a block diagram showing the configuration of a conventional address assignment device. A plurality of peripheral devices 4 to 10 are connected to the central control device 2 via a bus 12. In addition, bus 12
includes address bus, data bus as well as
Other signals 2 For example, it is assumed that all buses for transmitting decode signals and control signals are included.

In such a configuration, in order to individually control each of the peripheral devices 4 to 10 from the central control device 2 via the bus 12, addresses are assigned from the central control device 2 to each of the peripheral devices 4 to 10. There must be.

For example, the following method is used to allocate addresses to the peripheral devices 4 to 10. That is, each peripheral device 4
~10, dip switch (DSW) 4a~
10a, and set different values to these. The peripheral devices 4-10 compare the values set in the DSWs 4a-10a with the address decode signal from the central controller 2.

Only when the setting value of the DSW 4aNIOa corresponds to the address decode signal, the central control unit 2 is allowed to access the corresponding peripheral device. In other words, addresses are assigned according to the setting values of the DSWs 4a to 10a of the peripheral device 4axlOa.

[Problems to be Solved by the Invention] However, the conventional address allocation method described above has the following problems. That is, since the operator must set the dip switch one by one, the setting operation is complicated, and therefore, setting errors are inevitable.

Note that, apart from the above-mentioned method, the following method of allocating addresses to peripheral devices has been proposed. For example, this is a method using a multipath such as a VME bus, and is defined as a standard for each bus.

In such a method, the above-mentioned drawbacks are eliminated because addresses are automatically assigned to peripheral devices. However, in order to implement this method, it is naturally necessary to use a bus specified by the standard. Moreover, in order for the central control unit to identify the peripheral devices, complicated hardware must be installed on each peripheral device.

SUMMARY OF THE INVENTION Accordingly, one object of the present invention is to provide an address assignment device that allows addresses to be assigned from a central controller to peripheral devices without requiring manual operations such as setting dip switches. Another object of the present invention is to provide an address assignment device that requires simple hardware and control procedures for address assignment operations.

[Means for Solving the Problems] In the address assignment device of the present invention, the central control unit has a write output terminal and an enable output terminal. Each of the peripheral devices has a write input terminal, an enable input terminal, an enable output terminal, and a storage means, respectively, commonly connected to the write output terminal of the central controller. The enable input terminal of the first stage peripheral device is connected to the enable output terminal of the central controller, and the enable input terminal of each subsequent stage peripheral device is connected to the enable output terminal of the previous stage peripheral device.

[Operation] According to the address assignment device of the present invention, the central control unit outputs a write signal and a write enable signal to the write output terminal and enable output terminal of the central control unit, respectively, and outputs a data signal to the bus. . When each of the peripheral devices receives a write signal from the write input terminal during a valid period of the write enable signal from the enable input terminal, each of the peripheral devices writes the data signal from the bus to the storage means;
A write enable signal from the enable input terminal is passed to the enable output terminal. Accordingly, the write enable signal passes sequentially through the enable input and enable output terminals of each peripheral device. As a result, the content of the data signal written in each of the storage means of each peripheral device becomes the address of that peripheral device.

[Embodiment] Next, an embodiment related to the address assignment device of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of an address assignment device according to the present invention. This address assignment device comprises a plurality of stages of peripheral devices 16 . connected to a central control device 14 via a bus 13 . 18. 20. 22 is assigned an address by the central controller 14. Bus 13 is for transmitting address signals, data signals, address decode signals, and other control signals. In addition,
In this specification, the "/" prefix to each signal name indicates that the signal is an active low signal. The central controller 14 has a write output terminal 30 and an enable output terminal 40. The central controller 14 outputs a write signal /A write enable signal /El to a write output terminal 30 and an enable output terminal 40, respectively. At the same time, a data signal representing an address to be assigned to each peripheral device 16 to 22 is output to the bus 13. Each of the peripheral devices 16 to 22 has the following terminals.

That is, a write input terminal 32 .commonly connected to a write output terminal 30 of the central controller 14 . 34. 36.38
, enable input terminal 42. 44. 46°48, and enable output terminal 50. 52. It is 54°56. Further, the peripheral devices 16-22 have storage means 16a-22a for storing addresses assigned to the peripheral devices 16-22 by the central control device 14. The enable input terminal 42 of the first-stage peripheral device 16 is connected to the central controller 1.
It is connected to the enable output terminal 40 of No. 4. Also,
The enable input terminals 44, 46.48 of the peripheral devices 18, 20.22 in the subsequent stages are respectively connected to the enable output terminals 50, 52.54 of the peripheral devices in the previous stage.

Next, the operation of the address assignment device configured in this manner will be explained.

First, when the peripheral device 16 receives the write signal /A from the write input terminal 32 during the valid period of the write enable signal /El from the enable input terminal 42, the peripheral device 16 receives the write signal /A from the central controller 14 via the bus 13. The data signal is written into the storage means 16a. The content of this data signal becomes the address of the peripheral device 16. Further, the peripheral device 16 writes the address and also writes the enable input terminal 4.
The write enable signal /El from 2 is passed to the enable output terminal 50. The signal that has passed is defined as a write enable signal /E2. This write enable signal /E2
is applied to the enable input terminal 44 of the peripheral device 18 at the next stage. Peripheral device 18 then performs a write operation similar to that described above. That is, the peripheral device 18 is connected to the enable input terminal 4.
When the write signal /A from the write input terminal 34 is received during the valid period of the write enable signal /E2 from the central controller 14, the data signal outputted from the central controller 14 via the bus 13 is written into the storage means 18a. The content of this data signal becomes the address of the peripheral device 18. Further, the peripheral device 18 passes the write enable signal /E2 from the enable input terminal 44 to the enable output terminal 52 while writing the address. The passed signal is designated as a write enable signal /E3. This write enable signal /E3 is applied to the enable input terminal 46 of the peripheral device 20 at the next stage. Thereafter, by performing similar address allocation operations, enable signals /E4 and /E5 are output from peripheral devices 20 and 22, respectively, and enable signals /E4 and /E5 are output from peripheral devices 20 and 22, respectively.
Addresses are sequentially assigned up to 2.

Next, the operations of the central control device 14 and the peripheral devices 16 to 22 will be described in detail with reference to the circuit diagram shown in FIG. 2 and the corresponding time chart shown in FIG. 3.

FIG. 2 is a circuit diagram showing a portion of a peripheral device in an embodiment of the present invention. In FIG. 12, parts corresponding to those in FIG. 1 are given the same reference numerals. Buffer 60 is enabled when write enable signal /El is valid and provides write signal /A to AND gate 66 . Signals are exchanged between the bus 13 and the data bus BD inside the peripheral device 16 via the bus buffer 62. The bus buffer 62 is enabled when an output signal from an output terminal Q of a multiplexer 74, which will be described later, becomes valid, and data can be exchanged. Four bits of data of the data on the bus 13 is input to the buffer 64 . When the buffer 64 is enabled by the write enable signal /El, the buffer 64
The 4-bit data passed through is applied to input terminals D1 to D4 of register 68. These data are taken into the 4-bit register 68 at the rising edge of the write signal /A which has passed through the AND gate 66, and are output as active low to its output terminals 01-4. Note that this register 68 is similar to the storage means 16a in FIG.
This corresponds to

The address of the peripheral device 16 is expressed as 3-bit data.
It is stored in register 68. The remaining 1-bit data written to register 68 is used as a write completion signal indicating whether an address has been written to register 68 or not. This write completion signal will be explained later. Furthermore, the 4-bit data output from the register 68 passes through the buffer 76 and is stored as data in the peripheral device 16.
It is output to bus BD. Further, each of the 3-bit address data output from the register 68 is applied to the control input terminal C1-03 of the multiplexer 74. According to this address data, multiplexer 74 selects one of the four decode signals DSI-DS4 applied to its input terminals D3-D6 and outputs it to output terminal Q.

When the signal output to the output terminal Q becomes valid (rLJ), it means that the peripheral device 16 has been selected by the central controller 14. The signal output from the output terminal Q of the multiplexer 74 enables the bus buffer 62 described above. Therefore, data is exchanged between the internal data bus BD of the peripheral device 16 and the bus 13, that is, the peripheral device 16 is selected. A decoder 78, enabled by the output signal of multiplexer 74, receives address signals provided from central controller 14 via bus 13 and address bus BA in peripheral device 16. The decoder 78 decodes the received address signal to each element 2 in the peripheral device 16, such as a buffer or a memory.

It outputs enable signals that enable other elements, etc., and outputs other control signals. That is,
Each of the elements within the peripheral device is assigned an address. Note that the data bus BD in the peripheral device 16
Similarly, address bus BA in peripheral device 16 is connected to bus 13 via a bus buffer (not shown). Furthermore, since these bus buffers are three-state buffers, they require control signals in addition to enable signals. However, in this embodiment, the above-mentioned control signal is omitted because it has no operational relevance.

Next, the operation of the circuit shown in FIG. 2 will be explained with reference to the time chart shown in FIG.

First, the central controller 14 enables the write enable signal /El to the enable input terminal 42 ("LJ") (FIG. 3(A)).As a result, the buffers 60 and 64 are enabled, and and gate 72
One of the input terminals becomes "L". Next, the peripheral device 16
A data signal indicating an address to be assigned to the bus 13 is output to the bus 13. Therefore, the data signal passes through buffer 64 and is applied to the input terminal of register 68.

After the address signal is determined (FIG. 3(C)), the central controller 14 outputs the write signal /A (FIG. 3(C)).
B)). This write signal /A passes through enabled buffer 60 and AND gate 66 and is applied to the clock input terminal of register 68. As a result, at the rising edge of the write signal /A, the data being applied to the input terminals D1 to D4 of the register 68 is
8 is written. Note that the register 68 has been reset by the initial settings performed before this write operation.
The output terminals Ql-Q4 of the register 68 are all rH in advance.
It is in J state. Therefore, as a result of the write operation, a data signal indicating the address as described above is output to the data input terminals D1 to D3 of the register 68. Note that in order to cause the output terminal Q4 of the register 68 to output a write completion signal /B indicating that the write operation has been completed, a signal rHJ is applied to the data input terminal D4. Therefore, before and after the write operation, the state of the output terminal Q4 of the register 68 changes from rHJ to rLJ. That is, the state of the write completion signal /B is "1".
1'' indicates before writing, and rLJ indicates after writing. This write completion signal /B reaches the input terminal of AND gate 72. Therefore, the output signal of AND gate 72, i.e., the write enable signal /E
2 becomes valid (``L'') at the same time that the write completion signal /B becomes valid (``L'') (FIG. 3(D)). This write enable signal /E2 is applied to the enable output terminal 50.
, and is applied to the enable input terminal 44 of the peripheral device 18 at the next stage. In addition, the write completion signal /B is
It reaches AND gate 66 via inverter 70 . That is, when the write completion signal /B becomes valid (rLJ), the AND gate 66 is closed, so that the write signal /A inputted through the buffer 60 is prohibited from passing through from then on. Therefore, rewriting to register 68 is prohibited.

As a result of such operations, an address is assigned to the peripheral device 16. Furthermore, the same operation as above is performed sequentially.
This is done in the peripheral devices 18, 20.22. As a result, the third
As shown in Figures (E), (F), and (G), the write enable signal /E3°/E4. /E5 is the enable output terminal 52, 54.5 of the peripheral device 18, 20.22.
It is output from 6. Since these operations will be repeated, their explanation will be omitted.

As mentioned above, by performing the address assignment operation,
Each of the peripheral devices 16-22 can be assigned on an address map viewed from the central controller 14. Therefore, from the central control unit 14 via the bus 13 the peripheral device 1
From 6 to 22, enter the address corresponding to the assigned address.
By applying decode signals DSI to DS4, a desired peripheral device can be selected and the selected peripheral device can be individually controlled.

Furthermore, whether the above address allocation operation was performed correctly,
If you want to check whether this is the case, you can do the following. That is,
In FIG. 1, from the central control device 14 to each peripheral device 16
The addresses +5- assigned to 22 are stored in the storage means 16a to 22a of each peripheral device 16 to 22.
By confirming that the address has been stored in , it is possible to confirm whether or not the address assignment operation was performed correctly. This is the second
This will be explained with reference to the figures. That is, the address decode signal DSL-DS4 corresponding to the address of the peripheral device to be selected
For example, by outputting , the peripheral device 16 is selected. As a result, the output signal at the output terminal Q of the multiplexer 74 becomes "L", enabling the decoder 78. An address signal from the bus 13 is input to this decoder 78 . The address signal is set so that the signal that enables the buffer 76 that receives the output signal of the register 68 is rLJ.

As a result, the data stored in the register 68, that is, the address assigned to the peripheral device 16, is sequentially transferred to the bus 13 via the buffer 76, the data bus BD in the peripheral device 16, and the bus buffer 62. Output.

As a result, the central control unit W14 can read the address assigned to the peripheral device 16. By comparing the address read from the peripheral device 16 in this way with the address initially assigned to the peripheral device 16,
It is possible to confirm whether or not the address assignment operation was performed correctly. Therefore, by sequentially performing a similar operation to each of the peripheral devices 18 to 22, the address assignment operation can be confirmed.

As described above, by confirming address assignment, it is easy to count how many peripheral devices have read addresses.

If this fact is utilized, the following advantages will arise. That is, in the case of FIG. 1, among the four peripheral devices 16 to 22,
For example, consider a case where the peripheral device 20 is not connected. In this case, the write enable signal is
It reaches up to 8. However, the write enable signal is not input to the peripheral device 22 because the enable input terminal 46 and the enable output terminal 54 that should be present in the next stage do not exist.

As a result, no address is assigned to the peripheral device 22. Next, when the above-mentioned address assignment is confirmed, the addresses up to the peripheral device 18 can be read, but the addresses from the next stage onward cannot be read. Therefore, it is recognized by the central control unit 14 that only two peripheral devices 16, 18 have been assigned addresses. Therefore, by comparing the number of peripheral devices to be connected and the number of peripheral devices to which addresses have been assigned in the central control unit 14, it can be automatically determined whether a predetermined number of peripheral devices are correctly connected. It has the advantage that it can be determined.

As described above, according to the address assignment device of the present invention, addresses are sequentially written into each of the storage means 16a to 22a of the plurality of peripheral devices 16 to 22 connected to the central controller 14 via a bus. It will be done. Therefore, deep
Addresses can be assigned from the central controller to the peripheral devices without requiring manual operations such as setting switches. Therefore, unlike the conventional method, there is no need for complicated setting operations of dip switches. Another advantage is that malfunctions due to incorrect settings of the dip switch can be prevented.

Further, the hardware necessary to realize these address assignment operations can be realized by a simple configuration as shown in the circuit diagram of FIG. Further, the hardware control procedure is simple, as shown in the time chart of FIG.

In the embodiment shown in FIG. 2, a 4-bit register 68 is used. Three of the four bits were used to store addresses assigned to peripheral devices. The reason for this will be explained. If there are 2 bits, 4
Since different types of addresses can be expressed, it should be possible to store addresses to be assigned to the four peripheral devices 16-22. However, due to initial settings, it is necessary to separately indicate the state in which the register 68 is reset. Therefore, the number of bits used in register 68 is increased by one, and three bits are used for address storage.

Although preferred embodiments of the present invention have been described above, the present invention is not limited to the embodiments described herein.
It will be apparent to those skilled in the art that various modifications and changes can be made as necessary without departing from the spirit of the invention.

[Effects of the Invention] As explained below, according to the address assignment device of the present invention, addresses are sequentially assigned to each of the storage means of a plurality of stages of peripheral devices connected to a central control unit via a bus. written. Therefore, unlike the conventional art, addresses can be assigned from the central controller to the peripheral devices without requiring manual operations such as setting dip switches. This not only improves operability, but also improves the depth and depth.
This has the advantage of preventing malfunctions due to incorrect switch settings. Another advantage is that the hardware and control procedures needed to implement the address assignment operation can be simple. Furthermore, by reading out the addresses assigned to peripheral devices and counting the number of peripheral devices to which addresses have been assigned, it is possible to determine whether a predetermined number of peripheral devices are connected.

[Brief explanation of drawings]

FIG. 1 is a block diagram showing the configuration of an address assignment device of the present invention, FIG. 2 is a circuit diagram showing a part of a peripheral device in an embodiment of the present invention, and FIG. 3 is an address allocation device in the same embodiment. FIG. 4, a time chart corresponding to the allocation operation, is a block diagram showing the configuration of a conventional address allocation device. 13: 14= 16-22: 16a-22 a: 68: Bus central controller peripheral device storage means register (storage means)

Claims (1)

[Scope of Claims] An address assignment device in which the central controller allocates an address to each of a plurality of stages of peripheral devices connected to the central controller via a bus, wherein the central controller has a write output terminal and an enable terminal. each of the peripheral devices outputs a write signal and a write enable signal to the write output terminal and the enable output terminal, respectively, and outputs a data signal to the bus, and each of the peripheral devices outputs a write output of the central controller. A write input terminal, an enable input terminal, an enable output terminal, and a storage means are respectively connected to the terminals in common, and the enable input terminal of the peripheral device in the first stage is connected to the enable output terminal of the central controller, and the enable input terminal of the peripheral device in the first stage is connected to the enable output terminal of the central controller, and The enable input terminal of each of the peripheral devices in the subsequent stage is connected to the enable output terminal of the peripheral device in the previous stage, and each of the peripheral devices receives the write enable signal from the enable input terminal during the validity period of the write enable signal from the enable input terminal. Upon receiving said write signal from said write input terminal, said data signal from said bus is written to said storage means, said write enable signal from said enable input terminal is passed to said enable output terminal, and each of said peripheral devices An address assignment device characterized in that the content of said data signal written in said storage means of said device becomes an address of said peripheral device.