JPS63197251A - Information processor - Google Patents

Abstract

PURPOSE:To eliminate a mounting position error by comparing the address outputted from a processor with an ID when the processor ends its resetting action and is set under its working state and providing an access on a ROM when the coincidence is obtained from said comparison via a circuit provided to each ROM. CONSTITUTION:The titled processor is provided with a gate circuit 5 which outputs the addresses of the ID written in ROMs 8, 10 and 12 in response to a chip selection signal 25 when a mode signal 24 shows the reset mode of a processor 4, outputs an address signal received from the processor 4 to an address bus 13 when the signal 24 shows the working mode to the processor 4 and a gate circuit 6 which outputs an output enable signal 28 to those ROMs 8, 10 and 12 by the signal 24 in the reset mode of the processor 4 and by a memory read signal 27 received from the processor 4 in a processor working mode respectively. When the processor 4 gives accesses to the ROMs 8, 10 and 12, it is just required for the processor 4 to output the ID of the ROM as an address signal. Thus the accesses are possible to the ROMs 8-12 regardless of the mounting positions in terms of hardware.

Description

DETAILED DESCRIPTION OF THE INVENTION [Field of Industrial Application] The present invention provides a processor and a 1.1l
The present invention relates to an information processing device having a plurality of ROMs that are tlled.

[Conventional technology]

Conventionally, in this type of information processing apparatus, each ROM has been mounted with each address fixed, such as corresponding to an address from one address to another.

(Problem that is intended to be solved) In the conventional method described above, the hardware implementation position order and the software program addressing order may differ, and in this case, implementation errors or implementation errors may occur. In order to clarify the location, it is necessary to put a label on the ROM and create a corresponding diagram, and if you try to match the hardware mounting position order with the address of the software program, the ROM mounting The disadvantage is that it causes till reduction.

[Means for resolving the same period]

The information processing device of the present invention has an ID indicating where the content written in the ROM km is located in terms of addressing of the software program.
It is written to a predetermined address in OM, and resets the processor to the reset state for a predetermined period of time.
~ A reset signal generation circuit that generates a signal, and a dip select 1 signal that latches the ID output from the ROM to the data bus 2 during processor reset, and latches the address on the address bus when the processor is operating. an ID discrimination circuit provided for each ROM that outputs a signal, and the chip select signal that selects each ID discrimination circuit during processor reset; and a timing generation circuit that outputs a mode signal indicating whether the processor is resetting or operating; and an RO corresponding to the chip select signal when the mode signal indicates that the processor is resetting.
A gate circuit that outputs the address of the ID written in M and outputs the address signal output from the processor to the address bus when the mode signal indicates that the processor is operating, and a gate circuit that outputs the address signal output from the processor to the address bus when the mode signal indicates that the processor is operating. It has a gate circuit that outputs an output enable signal to the ROM in response to a signal or, during processor operation, in response to a memory read signal from the processor.

[Effect]

Therefore, when the processor accesses the ROM, the processor only needs to output the IQ of the ROM as an address signal, and can access the ROM regardless of the hardware mounting position.

〔Example〕

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram of an embodiment of an information processing apparatus according to the present invention, and FIG. 12 is an address/data correspondence diagram, FIG. 3 is a block diagram of the ID discrimination circuit 7.9.11, and FIG. 4 is a timing generation circuit for the operation of this embodiment.

In this embodiment, three ROM8. ID. 12 has been implemented,
Each ROM8, ID. 12, an IQ indicating where the content written in the ROM is located in terms of addressing in the software program is written at the final address FFFF, as shown in FIG. And each ROM8, ID
．． 12 is provided with a ■D discrimination circuit 7.9.11. The ID discrimination circuits 7, 9.11, as shown in FIG.
The ID output from the corresponding ROM onto the data bus 14 during the reset of the processor 4 is sent to the chip select signal 25.
The ID latch circuit 71 wraps the address signal output to the address bus 13 during the first processor operation.
-m is compared with the ID latched in the latch circuit 71.
The ID comparison circuit 72 outputs the chip select signal 26 when the mode signal 24 indicates that the processor is being reset, and outputs the chip select signal 25 when the mode signal 24 indicates that the processor is being reset. Selector 73 that outputs the signal 26 to the corresponding ROM
It is made up of. Basic clock signal generation circuit 2. The reset signal generation circuits 1 each receive a basic clock signal 21.
A reset signal 22 is generated. When the ID read timing generation circuit 3 receives the reset signal 22, the processor 4
A processor reset signal 23 that resets each ROM 8, ID. A chip select signal 25 for selecting 12 and a mode signal 24 are output. The gate circuit 5 is provided between the processor 4 and the address bus 13, and the mode signal 24 indicates that the processor is operating].
When the mode signal 24 indicates that the processor is in operation, the address signal FFFF is output to the address bus 13, and when the mode signal 24 indicates that the processor is operating, the address signal output from the processor 4 is output to the address bus 13. The OR gate 6 uses the mode signal 24 indicating that the processor is being reset or the memory read signal 27 outputted from the processor 4 as an output enable signal 28 for the ROM 8. ID. Output to 12.

Next, the operation of this embodiment will be explained with reference to the time chart of FIG.

When the reset signal 22 is sent from the reset signal generation circuit 1 at time 1'1, the ID read timing generation circuit 3
A processor reset signal 23 is output from the processor 4, and the processor 4 enters a reset state. At the next time t2, the mode signal 24 output from the ID read timing generation circuit 3 becomes low level.

Due to this change in the mode signal 24, the address signal FFFF is outputted from the gate circuit 5 to the address bus 13, and the mode signal 24 is inputted to the OR gate 6, and the ROM 8. ID. 12 is output. Then, at time t3, the chip select signal 25 is output to the D discrimination circuit 7. This chip select signal 25 is output to the ROM 8 via the selector 73. As a result, the final address FFFF of ROM8 is accessed,
The stored ID is output to the data bus 14 and latched by the ID latch circuit 71 at time t4 when the chip select signal 25 becomes high level. After that, in the same way, the chip select signal 2 is sequentially sent to the ID discrimination circuit 9-11.
5 is output and ROMID. 12 ID latch circuits 71
The ID is stored in the . In this way j) all ROM8
゜ID. When the 12 IDs are stored in the respective ID latch circuits 71, the mode signal @24 becomes high level at time t6. The gate circuit 5 opens when the mode signal 24 becomes high level. Then, when the processor reset signal 23 becomes high level at time t6, the processor 4 is released from the reset state and enters the operating state. The processor 4 uses the IO of the ROM 8 as an address signal and also outputs a memory read signal 27. This ID is output onto the address bus 13 through the gate circuit 5. Then, the ID comparison circuit 72 of the ID discrimination circuit 7 outputs a chip select signal @26 indicating a match, which is selected by the selector 73 and stored in the ROM8.
Enter. As a result, the ROM 8 is chip-selected, and thereafter, the processor 4 outputs an address signal to the address bus 13, and the data at the specified address in the ROM 8 is read out and output onto the data bus 14.
input to processor 4;

〔Effect of the invention〕

As explained above, the present invention stores an ID in the ROM, reads the ID while resetting the processor that accesses the ROM, stores it, and outputs the ID when the processor finishes resetting and enters the operating state. By providing each ROM with a circuit that compares the address and ID of the ROM and accesses the ROM when they match, it is no longer necessary to mount each ROM in a fixed position when multiple ROMs exist, and the mounting position can be changed to each ROM. This eliminates the work of pasting a label indicating the information and creating a corresponding diagram, and also has the effect of eliminating mounting position errors.

[Brief explanation of the drawing]

FIG. 1 is a block diagram of an embodiment of the information processing apparatus of the present invention, and FIG. ID. 12 is an address/data correspondence diagram, FIG. 3 is a block diagram of the ID discriminating circuit 7.9.11, and FIG. 4 is a timing chart of the operation of this embodiment. DESCRIPTION OF SYMBOLS 1... Reset signal generation circuit, 2... Basic clock signal circuit, 3... ID read timing generation circuit, 4... Processor, 5... Gate circuit, 6... OR gate, 7.9 .11...-ID discrimination circuit, 8. ID. 12...ROM. 13...address bus, 14...data bus,
21...4 clock signals, 22...Reset signal, 23...Processor reset signal, 24...Mode signal, 25.26...Chip select signal, 27...Memory read signal 28. ...Output enable signal, 71...ID latch circuit, 72...ID comparison circuit, 73...Selector.

Claims (1)

[Scope of Claims] In an information processing device having a processor and a plurality of ROMs controlled by the processor, each ROM has an ID indicating where the content written in the ROM is located in terms of addressing of a software program. A reset signal generation circuit that generates a reset signal that puts the processor in a reset state for a predetermined period of time, and an I/O signal that is output from the ROM onto the data bus during processor reset.
D is latched by the chip select signal, and when the processor is operating, the address on the address bus is latched I.
an ID discriminating circuit provided for each ROM, which outputs a chip select signal to the ROM when the ROM matches D, and outputs the chip select signal which selects each ID discriminating circuit during processor reset; It also includes a timing generation circuit that generates a mode signal indicating whether the processor is being reset or in operation, and an address of an ID written in the ROM that corresponds to the chip select signal when the mode signal indicates that the processor is being reset. and a gate circuit that outputs the address signal output from the processor to the address bus when the mode signal indicates that the processor is operating; An information processing device comprising a gate circuit that outputs an output enable signal to a ROM in response to a memory read signal.