JPS5679353A - Memory bus data transfer method of multiprocessor - Google Patents
Memory bus data transfer method of multiprocessorInfo
- Publication number
- JPS5679353A JPS5679353A JP15427079A JP15427079A JPS5679353A JP S5679353 A JPS5679353 A JP S5679353A JP 15427079 A JP15427079 A JP 15427079A JP 15427079 A JP15427079 A JP 15427079A JP S5679353 A JPS5679353 A JP S5679353A
- Authority
- JP
- Japan
- Prior art keywords
- memory
- information
- bus
- data
- read
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Abstract
PURPOSE: To remarkably improve the throughput of the time sharing control memory bus, by varying the timing for defining timing of each information depending on a quality of the information.
CONSTITUTION: The information transferred on the memory bus 13 is classified into the address information to the memory 12, the read-out data information from the memory 12, and the write data information to the memory 12. Among these data the address information is set to the address register 42 of the processing unit 11 before a request to the memory 12 is output, and therefore the on-bus can be performed on the bus 13 from the beginning of the machine cycle. On the other hand, as for the read-out data from the memory 12, only if the data is defined before the end of the machine cycle, that will do. Also, as for the write data to the memory 12, the time for outputting from the register file 44 in the unit 11 becomes necessary. Accordingly, the throughput of the bus 13 is remarkably improved by transferring the address information, the memory read-out data, and the write data to the first part of the machine cycle, the middle part, and the last part, respectively.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15427079A JPS5679353A (en) | 1979-11-30 | 1979-11-30 | Memory bus data transfer method of multiprocessor |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP15427079A JPS5679353A (en) | 1979-11-30 | 1979-11-30 | Memory bus data transfer method of multiprocessor |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPS5679353A true JPS5679353A (en) | 1981-06-29 |
| JPS6153753B2 JPS6153753B2 (en) | 1986-11-19 |
Family
ID=15580488
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP15427079A Granted JPS5679353A (en) | 1979-11-30 | 1979-11-30 | Memory bus data transfer method of multiprocessor |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JPS5679353A (en) |
Cited By (3)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58119066A (en) * | 1981-12-30 | 1983-07-15 | ウルリツチ・フインジヤ− | Method and apparatus for exchanging data between more than one common memories and processing modules for data processing system |
| JPS5977566A (en) * | 1982-09-27 | 1984-05-04 | ニツクスドルフ・コンピユ−タ・アクチエンゲゼルシヤフト | One connection preparation method of multiple data processor for central clock control multiple system |
| JPS60245063A (en) * | 1984-05-21 | 1985-12-04 | Fujitsu Ltd | Access system for shared memory |
-
1979
- 1979-11-30 JP JP15427079A patent/JPS5679353A/en active Granted
Cited By (5)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPS58119066A (en) * | 1981-12-30 | 1983-07-15 | ウルリツチ・フインジヤ− | Method and apparatus for exchanging data between more than one common memories and processing modules for data processing system |
| JPS5977566A (en) * | 1982-09-27 | 1984-05-04 | ニツクスドルフ・コンピユ−タ・アクチエンゲゼルシヤフト | One connection preparation method of multiple data processor for central clock control multiple system |
| JPS6478362A (en) * | 1982-09-27 | 1989-03-23 | Nixdorf Computer Ag | One connection preparation of several data processors for central clock control multi-line system |
| JPH0472262B2 (en) * | 1982-09-27 | 1992-11-17 | Jiimensu Nitsukusudorufu Infuomeeshon Shisutemu Ag | |
| JPS60245063A (en) * | 1984-05-21 | 1985-12-04 | Fujitsu Ltd | Access system for shared memory |
Also Published As
| Publication number | Publication date |
|---|---|
| JPS6153753B2 (en) | 1986-11-19 |
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