JPS569826A - Channel controller - Google Patents
Channel controllerInfo
- Publication number
- JPS569826A JPS569826A JP8493979A JP8493979A JPS569826A JP S569826 A JPS569826 A JP S569826A JP 8493979 A JP8493979 A JP 8493979A JP 8493979 A JP8493979 A JP 8493979A JP S569826 A JPS569826 A JP S569826A
- Authority
- JP
- Japan
- Prior art keywords
- circuit
- command
- input
- read
- ffs
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Pending
Links
Landscapes
- Bus Control (AREA)
- Memory System Of A Hierarchy Structure (AREA)
Abstract
PURPOSE: To improve data transfer performance remarkably by enabling access from some input-output channels to a buffer memory circuit even in data transfer between a main memory unit and the buffer memory circuit by providing a group of command discrimination FFs.
CONSTITUTION: A group of command discrimination FFs401 is provided; input-output channels that correspond to set FFs are in process of the execution of a READ type command, i.e. a command for writing to buffer memory circuit 434 and those that corresponds to unset FFs are in process of the execution of a command for reading to circuit 434. Then, circuit 434 uses a circuit element that is executable for addresses 430 and 431 differing in read operation and write operation and the READ type command while data are stored in main memory unit MM at STORE402 or WRITE type command while data from MM are fetched at FETCH403 is executed by the input-output channel and access to circuit 434 of the input-output channel is accepted at 425, enabling simultaneous multiple access (simultaneous execution of read and write operations) to circuit 434.
COPYRIGHT: (C)1981,JPO&Japio
Priority Applications (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8493979A JPS569826A (en) | 1979-07-06 | 1979-07-06 | Channel controller |
Applications Claiming Priority (1)
Application Number | Priority Date | Filing Date | Title |
---|---|---|---|
JP8493979A JPS569826A (en) | 1979-07-06 | 1979-07-06 | Channel controller |
Publications (1)
Publication Number | Publication Date |
---|---|
JPS569826A true JPS569826A (en) | 1981-01-31 |
Family
ID=13844619
Family Applications (1)
Application Number | Title | Priority Date | Filing Date |
---|---|---|---|
JP8493979A Pending JPS569826A (en) | 1979-07-06 | 1979-07-06 | Channel controller |
Country Status (1)
Country | Link |
---|---|
JP (1) | JPS569826A (en) |
Cited By (2)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5621221A (en) * | 1979-07-30 | 1981-02-27 | Ibm | Input*output control unit |
JPS59100964A (en) * | 1982-12-01 | 1984-06-11 | Hitachi Ltd | Parallel transfer type director device |
-
1979
- 1979-07-06 JP JP8493979A patent/JPS569826A/en active Pending
Cited By (4)
Publication number | Priority date | Publication date | Assignee | Title |
---|---|---|---|---|
JPS5621221A (en) * | 1979-07-30 | 1981-02-27 | Ibm | Input*output control unit |
JPS5820060B2 (en) * | 1979-07-30 | 1983-04-21 | インタ−ナショナル ビジネス マシ−ンズ コ−ポレ−ション | input/output control device |
JPS59100964A (en) * | 1982-12-01 | 1984-06-11 | Hitachi Ltd | Parallel transfer type director device |
JPH0459653B2 (en) * | 1982-12-01 | 1992-09-22 | Hitachi Ltd |
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