JPS5712470A - Information processor having buffer memory - Google Patents

Information processor having buffer memory

Info

Publication number
JPS5712470A
JPS5712470A JP8629580A JP8629580A JPS5712470A JP S5712470 A JPS5712470 A JP S5712470A JP 8629580 A JP8629580 A JP 8629580A JP 8629580 A JP8629580 A JP 8629580A JP S5712470 A JPS5712470 A JP S5712470A
Authority
JP
Japan
Prior art keywords
memory
write
address
register
information processor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP8629580A
Other languages
Japanese (ja)
Inventor
Yuzo Omori
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Nippon Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp, Nippon Electric Co Ltd filed Critical NEC Corp
Priority to JP8629580A priority Critical patent/JPS5712470A/en
Publication of JPS5712470A publication Critical patent/JPS5712470A/en
Pending legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F5/00—Methods or arrangements for data conversion without changing the order or content of the data handled
    • G06F5/06—Methods or arrangements for data conversion without changing the order or content of the data handled for changing the speed of data flow, i.e. speed regularising or timing, e.g. delay lines, FIFO buffers; over- or underrun control therefor
    • G06F5/16—Multiplexed systems, i.e. using two or more similar devices which are alternately accessed for enqueue and dequeue operations, e.g. ping-pong buffers

Landscapes

  • Engineering & Computer Science (AREA)
  • Theoretical Computer Science (AREA)
  • Physics & Mathematics (AREA)
  • General Engineering & Computer Science (AREA)
  • General Physics & Mathematics (AREA)
  • Memory System Of A Hierarchy Structure (AREA)

Abstract

PURPOSE:To increase the performance of an information processor, by carrying out simultaneously both the read and write processes to the divided different buffer memories and reducing the queuing time of one process due to the other process. CONSTITUTION:A buffer memory 106 is divided into memories A106a and B106b. The data given from a write data register 105 is written into the side of memory B106b in the write W0 and W2, and an address switch circuit B108b provided for selection of address at the side of memory B106b selects and delivers the side of address register B102. On the other hand, the data given from the register 105 is written in the side of memory A106a in the write W1 and W3, and an address switch circuit A108a provided for selection of address at the side of the memory A106a selects and delivers the register B102 side. Thus the memory A106a is read in the write W0 and W2, and the memory B106b is read in the write W1 and W3 respectively.
JP8629580A 1980-06-25 1980-06-25 Information processor having buffer memory Pending JPS5712470A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8629580A JPS5712470A (en) 1980-06-25 1980-06-25 Information processor having buffer memory

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8629580A JPS5712470A (en) 1980-06-25 1980-06-25 Information processor having buffer memory

Publications (1)

Publication Number Publication Date
JPS5712470A true JPS5712470A (en) 1982-01-22

Family

ID=13882838

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8629580A Pending JPS5712470A (en) 1980-06-25 1980-06-25 Information processor having buffer memory

Country Status (1)

Country Link
JP (1) JPS5712470A (en)

Cited By (7)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59100964A (en) * 1982-12-01 1984-06-11 Hitachi Ltd Parallel transfer type director device
JPS60136842A (en) * 1983-12-26 1985-07-20 Hitachi Ltd Buffer storage control system
JPS6249438A (en) * 1985-08-28 1987-03-04 Hitachi Ltd Data buffering method for shared memory device retrieving system
JPS6314572A (en) * 1986-07-07 1988-01-21 Matsushita Graphic Commun Syst Inc Registering method for electronic filing system
EP0262468A2 (en) * 1986-09-18 1988-04-06 Advanced Micro Devices, Inc. Reconfigurable fifo memory device
FR2636448A1 (en) * 1988-09-15 1990-03-16 Finger Ulrich Data acquisition device for a processor
CN106604088A (en) * 2016-12-15 2017-04-26 北京小米移动软件有限公司 Buffer area data processing method and device, and equipment

Cited By (10)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS59100964A (en) * 1982-12-01 1984-06-11 Hitachi Ltd Parallel transfer type director device
JPH0459653B2 (en) * 1982-12-01 1992-09-22 Hitachi Ltd
JPS60136842A (en) * 1983-12-26 1985-07-20 Hitachi Ltd Buffer storage control system
JPH0131219B2 (en) * 1983-12-26 1989-06-23 Hitachi Ltd
JPS6249438A (en) * 1985-08-28 1987-03-04 Hitachi Ltd Data buffering method for shared memory device retrieving system
JPH0523459B2 (en) * 1985-08-28 1993-04-02 Hitachi Ltd
JPS6314572A (en) * 1986-07-07 1988-01-21 Matsushita Graphic Commun Syst Inc Registering method for electronic filing system
EP0262468A2 (en) * 1986-09-18 1988-04-06 Advanced Micro Devices, Inc. Reconfigurable fifo memory device
FR2636448A1 (en) * 1988-09-15 1990-03-16 Finger Ulrich Data acquisition device for a processor
CN106604088A (en) * 2016-12-15 2017-04-26 北京小米移动软件有限公司 Buffer area data processing method and device, and equipment

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