JPS56152384A - Television receiver for simultaneous display on plural colored screens - Google Patents

Abstract

PURPOSE:To simplify the chrominance signal processing circuit, by sampling the chrominance signal and writing this sampled signal into the memory by the clock signal synchronized with the chrominance subcarrier. CONSTITUTION:The chrominance signal amplified to a prescribed level by band amplifying circuit 51 is sent to sampling circuits 112 and 113. Sampling circuits 112 and 113 sample the chrominance signal at the timing of the write clock signal, which is generated by write clock signal generating circuit 42', to write the chrominance signal into B-Y signal memory 412 and R-Y signal memory 413. The burst signal extracted by band amplifying circuit 51 is supplied to the APC circuit consisting of phase detecting circuit 52 and voltage control oscillator 53, and the APC circuit generates the chrominance subcarrier. Write clock generating circuit 42' generates the write clock signal synchronized with the signal, which is obtained by dividing the chrominance subcarrier by frequency dividing circuit 111, as well as the synchronizing signal of the slave screen signal.