JPS56145444A - Bus system of multisystem computer - Google Patents

Bus system of multisystem computer

Info

Publication number
JPS56145444A
JPS56145444A JP4754480A JP4754480A JPS56145444A JP S56145444 A JPS56145444 A JP S56145444A JP 4754480 A JP4754480 A JP 4754480A JP 4754480 A JP4754480 A JP 4754480A JP S56145444 A JPS56145444 A JP S56145444A
Authority
JP
Japan
Prior art keywords
bus
request address
hold line
computer
acquition
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP4754480A
Other languages
Japanese (ja)
Other versions
JPS5836374B2 (en
Inventor
Shinji Ogawa
Akio Kinoshita
Makoto Kano
Yasuo Shimizu
Kenichi Naka
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Panafacom Ltd
Original Assignee
Panafacom Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Panafacom Ltd filed Critical Panafacom Ltd
Priority to JP55047544A priority Critical patent/JPS5836374B2/en
Publication of JPS56145444A publication Critical patent/JPS56145444A/en
Publication of JPS5836374B2 publication Critical patent/JPS5836374B2/en
Expired legal-status Critical Current

Links

Classifications

    • G—PHYSICS
    • G06—COMPUTING; CALCULATING OR COUNTING
    • G06F—ELECTRIC DIGITAL DATA PROCESSING
    • G06F13/00—Interconnection of, or transfer of information or other signals between, memories, input/output devices or central processing units
    • G06F13/14—Handling requests for interconnection or transfer
    • G06F13/36—Handling requests for interconnection or transfer for access to common bus or bus system
    • G06F13/368—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control
    • G06F13/374—Handling requests for interconnection or transfer for access to common bus or bus system with decentralised access control using a self-select method with individual priority code comparator

Abstract

PURPOSE:To continue the normal operation of a bus even if any computer is troubled, by providing a bus-acquition-signal transmitting circuit to each subsystem and by wiring a shared hold line and request address lines, which correspond to respective subsystems, to respective subsystems. CONSTITUTION:Subsystems 3-0-3-n of the multisystem computer system are provided with bus acquition control circuits 7-0-7-n, and bus-acquition-signal transmitting and receiving circuits 5-0-5-n, and 6-0-6-n. To those circuits 5-0- 5-n, shared hold line 8hd and request address lines 8-0 are connected and to circuits 6-0-6-n, hold line 8hd and request address lines 8-1-8-n are also connected. Then, systems 3-0-3-n are provided with the function of checking a signal on hold line 8hd is active or not, that of sending a request address when it is not active, etc., and even if any computer is troubled, the normal operation of the bus is maintained. Further, the active maintenance of the computers is facilitated.
JP55047544A 1980-04-11 1980-04-11 Bus method in multi-system computer system Expired JPS5836374B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP55047544A JPS5836374B2 (en) 1980-04-11 1980-04-11 Bus method in multi-system computer system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP55047544A JPS5836374B2 (en) 1980-04-11 1980-04-11 Bus method in multi-system computer system

Publications (2)

Publication Number Publication Date
JPS56145444A true JPS56145444A (en) 1981-11-12
JPS5836374B2 JPS5836374B2 (en) 1983-08-09

Family

ID=12778082

Family Applications (1)

Application Number Title Priority Date Filing Date
JP55047544A Expired JPS5836374B2 (en) 1980-04-11 1980-04-11 Bus method in multi-system computer system

Country Status (1)

Country Link
JP (1) JPS5836374B2 (en)

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60258671A (en) * 1984-06-05 1985-12-20 Nec Corp Processor
JPS6358567A (en) * 1986-08-28 1988-03-14 Nec Corp Serial interface bus system

Cited By (3)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS60258671A (en) * 1984-06-05 1985-12-20 Nec Corp Processor
JPS6358567A (en) * 1986-08-28 1988-03-14 Nec Corp Serial interface bus system
JPH0564384B2 (en) * 1986-08-28 1993-09-14 Nippon Electric Co

Also Published As

Publication number Publication date
JPS5836374B2 (en) 1983-08-09

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