JPS5460532A - Bus checking system - Google Patents

Bus checking system

Info

Publication number
JPS5460532A
JPS5460532A JP12691877A JP12691877A JPS5460532A JP S5460532 A JPS5460532 A JP S5460532A JP 12691877 A JP12691877 A JP 12691877A JP 12691877 A JP12691877 A JP 12691877A JP S5460532 A JPS5460532 A JP S5460532A
Authority
JP
Japan
Prior art keywords
ioc
channel
circuit
akit
given
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Pending
Application number
JP12691877A
Other languages
Japanese (ja)
Inventor
Masaru Hamada
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Mitsubishi Electric Corp
Original Assignee
Mitsubishi Electric Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Mitsubishi Electric Corp filed Critical Mitsubishi Electric Corp
Priority to JP12691877A priority Critical patent/JPS5460532A/en
Publication of JPS5460532A publication Critical patent/JPS5460532A/en
Pending legal-status Critical Current

Links

Abstract

PURPOSE: To secure easy investigation for the factors of errors caus by both the software and the hardware by providing the bus check means on the bus line which is common to the input and putput control units.
CONSTITUTION: When the interruption signal is delivered to channel 1 from input/ outpout device IOC, COU gives the AKIT order to control line 4 to know which IOC the interruption is given from. Bus check circuit 8 consists of AKIT detecting circuit 10 and device and address detecting circuit 11. Circuit 10 checks whether some interruption signal has arrived from IOC when the AKIT command is given from channel 1. And the soft error signal 9 is emitted to channel 1 in case no interruption signal exists. Circuit 11 memorizes device adress DA of IOC and compares IOC with DA which is given when the data is transferred. And error signal 9 is emitted to channel 1 when no coincidence is obtained
COPYRIGHT: (C)1979,JPO&Japio
JP12691877A 1977-10-21 1977-10-21 Bus checking system Pending JPS5460532A (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP12691877A JPS5460532A (en) 1977-10-21 1977-10-21 Bus checking system

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP12691877A JPS5460532A (en) 1977-10-21 1977-10-21 Bus checking system

Publications (1)

Publication Number Publication Date
JPS5460532A true JPS5460532A (en) 1979-05-16

Family

ID=14947114

Family Applications (1)

Application Number Title Priority Date Filing Date
JP12691877A Pending JPS5460532A (en) 1977-10-21 1977-10-21 Bus checking system

Country Status (1)

Country Link
JP (1) JPS5460532A (en)

Cited By (1)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6020655U (en) * 1983-07-18 1985-02-13 株式会社明電舎 Abnormality monitoring device for asynchronous bus-coupled computer system

Cited By (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPS6020655U (en) * 1983-07-18 1985-02-13 株式会社明電舎 Abnormality monitoring device for asynchronous bus-coupled computer system
JPH0313798Y2 (en) * 1983-07-18 1991-03-28

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