JPS55121769A - Demodulator circuit for self-clocking information signal - Google Patents

Demodulator circuit for self-clocking information signal

Info

Publication number
JPS55121769A
JPS55121769A JP2966179A JP2966179A JPS55121769A JP S55121769 A JPS55121769 A JP S55121769A JP 2966179 A JP2966179 A JP 2966179A JP 2966179 A JP2966179 A JP 2966179A JP S55121769 A JPS55121769 A JP S55121769A
Authority
JP
Japan
Prior art keywords
output
signal
pulse
self
case
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP2966179A
Other languages
Japanese (ja)
Other versions
JPS6348107B2 (en
Inventor
Yoji Sugiura
Masaru Nishimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP2966179A priority Critical patent/JPS55121769A/en
Priority to US06/127,432 priority patent/US4344039A/en
Priority to DE3009713A priority patent/DE3009713C2/en
Publication of JPS55121769A publication Critical patent/JPS55121769A/en
Publication of JPS6348107B2 publication Critical patent/JPS6348107B2/ja
Granted legal-status Critical Current

Links

Classifications

    • H—ELECTRICITY
    • H04—ELECTRIC COMMUNICATION TECHNIQUE
    • H04L—TRANSMISSION OF DIGITAL INFORMATION, e.g. TELEGRAPHIC COMMUNICATION
    • H04L25/00—Baseband systems
    • H04L25/38—Synchronous or start-stop systems, e.g. for Baudot code
    • H04L25/40—Transmitting circuits; Receiving circuits
    • H04L25/49—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems
    • H04L25/4904—Transmitting circuits; Receiving circuits using code conversion at the transmitter; using predistortion; using insertion of idle bits for obtaining a desired frequency spectrum; using three or more amplitude levels ; Baseband coding techniques specific to data transmission systems using self-synchronising codes, e.g. split-phase codes

Landscapes

  • Physics & Mathematics (AREA)
  • Spectroscopy & Molecular Physics (AREA)
  • Engineering & Computer Science (AREA)
  • Computer Networks & Wireless Communication (AREA)
  • Signal Processing (AREA)
  • Dc Digital Transmission (AREA)
  • Signal Processing For Digital Recording And Reproducing (AREA)
  • Digital Transmission Methods That Use Modulated Carrier Waves (AREA)

Abstract

PURPOSE:To secure the demodulation for the data signal based on the clocks which are generated in the unit number corresponding to the measurement result of the inverting intervals of the self-clocking information (SCI) signal. CONSTITUTION:In case the FM-modulated SCI signal is demodulated, the signal inverting interval is either T0 or 2T0. And one unit of pulse/NC is generated based on latch signal output L1 in case the quantization is given to T0; while two units of pulse/NC are generated based on latch signal output L2 in case the quantization is given to 2T0 respectively. When the FM modulation is carried out, JKFF92 is reset by means of the output of NAND91 to which pulse X3 and latch signal output L2 are supplied. And the pulse/NC is divided into two parts by JKFF92, and the /Q output turns to clock RCL'. When output L1 is used for the data and clock RCL' is used for the clock which operates on the rise of RCL', the original digital data signal is demodulated.
JP2966179A 1979-03-13 1979-03-13 Demodulator circuit for self-clocking information signal Granted JPS55121769A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP2966179A JPS55121769A (en) 1979-03-13 1979-03-13 Demodulator circuit for self-clocking information signal
US06/127,432 US4344039A (en) 1979-03-13 1980-03-05 Demodulating circuit for self-clocking-information
DE3009713A DE3009713C2 (en) 1979-03-13 1980-03-13 Circuit arrangement for decoding a self-clocking information signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP2966179A JPS55121769A (en) 1979-03-13 1979-03-13 Demodulator circuit for self-clocking information signal

Related Child Applications (2)

Application Number Title Priority Date Filing Date
JP4941580A Division JPS55146623A (en) 1980-04-14 1980-04-14 Demodulating circuit for self-clocking information signal
JP6513680A Division JPS5623065A (en) 1980-05-15 1980-05-15 Demodulation circuit for self clocking information signal

Publications (2)

Publication Number Publication Date
JPS55121769A true JPS55121769A (en) 1980-09-19
JPS6348107B2 JPS6348107B2 (en) 1988-09-27

Family

ID=12282293

Family Applications (1)

Application Number Title Priority Date Filing Date
JP2966179A Granted JPS55121769A (en) 1979-03-13 1979-03-13 Demodulator circuit for self-clocking information signal

Country Status (1)

Country Link
JP (1) JPS55121769A (en)

Also Published As

Publication number Publication date
JPS6348107B2 (en) 1988-09-27

Similar Documents

Publication Publication Date Title
JPS563421A (en) Signal converting device
JPS52101910A (en) Signal converting ic circuit dependent on writing state
DE3888313D1 (en) DC - recovery circuit for the recovery and compensation of lost low frequency components in a digital signal transmission system.
NO881209L (en) DIGITAL LOCKED DATA ENTRY CIRCUIT.
HK27282A (en) Improvements in or relating to digital electronic alarm timepieces
JPS55121769A (en) Demodulator circuit for self-clocking information signal
DE68919437D1 (en) Circuit arrangement for the detection of code violations in AMI signal transmission.
EG13287A (en) Improvements in or relating to frequency-modulated data communications receivers
JPS543543A (en) Image recorder
DE3669348D1 (en) SYSTEM FOR MEASURING THE KEY RATIO OF IMPULSES VARIABLE FREQUENCY.
JPS5799062A (en) Reception circuit for data transmission
HK19882A (en) Improvements in or relating to digital electronic alarm timepieces
AU523034B2 (en) Encoding and decoding digital data
JPS5765945A (en) Demodulating circuit
JPS56163512A (en) Digital signal demodulating system
JPS5687211A (en) Digital demodulating circuit
JPS5387713A (en) Demodulation circuit
JPS5433060A (en) Printing recorder
JPS5687213A (en) Data demodulating circuit
JPS5382154A (en) Digital fm demodulating system
DE3060712D1 (en) Phase-locked oscillator circuit and system for generating a clock signal using this circuit
JPS556976A (en) Demodulating device
JPS5637814A (en) Demodulating circuit for self-clocking information signal
GB2167596B (en) Data reproducing device with clock signal generating circuit
JPS6467036A (en) Demodulation circuit