JPS5637814A - Demodulating circuit for self-clocking information signal - Google Patents

Demodulating circuit for self-clocking information signal

Info

Publication number
JPS5637814A
JPS5637814A JP11192079A JP11192079A JPS5637814A JP S5637814 A JPS5637814 A JP S5637814A JP 11192079 A JP11192079 A JP 11192079A JP 11192079 A JP11192079 A JP 11192079A JP S5637814 A JPS5637814 A JP S5637814A
Authority
JP
Japan
Prior art keywords
circuit
pulse
signal
output
digital data
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Granted
Application number
JP11192079A
Other languages
Japanese (ja)
Other versions
JPS6348108B2 (en
Inventor
Yoji Sugiura
Masaru Nishimura
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
Sanyo Electric Co Ltd
Original Assignee
Sanyo Electric Co Ltd
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by Sanyo Electric Co Ltd filed Critical Sanyo Electric Co Ltd
Priority to JP11192079A priority Critical patent/JPS5637814A/en
Priority to US06/127,432 priority patent/US4344039A/en
Priority to DE3009713A priority patent/DE3009713C2/en
Publication of JPS5637814A publication Critical patent/JPS5637814A/en
Publication of JPS6348108B2 publication Critical patent/JPS6348108B2/ja
Granted legal-status Critical Current

Links

Abstract

PURPOSE: To prevent an erroneous digital data signal from being demodulated by demodulating an original digital data signal from a clock signal and data generated on the basis of inversion intervals of a quantized signal.
CONSTITUTION: 2W4 pulses NC are inputted to circuit 60 for generating data and a clock signal from pulse generating circuit 50 corresponding to inversion intervals 2T0W4T0 of a quantized signal. Circuit 60 consists of three FF circuits 61W63 and NAND gate 64 and pulse X3 and latch output L4 are inputted to gate 64; since output L4 shows "1" only when the pattern of the digital data signal is 101, pulse M3 is generated by making use of this specific pattern to reset circuit 61 with the above-mentioned pulse and then the polarity of clock RCL is initialized to stop the synchronization between the clock and data. In addition, circuit 62 is set with pulse M1 to generate Q output "1" and circuit 63 has its data input grounded, so that the Q output will be reset to "0" in response to the rise of pulse NC. Consequently, the demodulation of erroneous digital data will be prevented.
COPYRIGHT: (C)1981,JPO&Japio
JP11192079A 1979-03-13 1979-08-31 Demodulating circuit for self-clocking information signal Granted JPS5637814A (en)

Priority Applications (3)

Application Number Priority Date Filing Date Title
JP11192079A JPS5637814A (en) 1979-08-31 1979-08-31 Demodulating circuit for self-clocking information signal
US06/127,432 US4344039A (en) 1979-03-13 1980-03-05 Demodulating circuit for self-clocking-information
DE3009713A DE3009713C2 (en) 1979-03-13 1980-03-13 Circuit arrangement for decoding a self-clocking information signal

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP11192079A JPS5637814A (en) 1979-08-31 1979-08-31 Demodulating circuit for self-clocking information signal

Publications (2)

Publication Number Publication Date
JPS5637814A true JPS5637814A (en) 1981-04-11
JPS6348108B2 JPS6348108B2 (en) 1988-09-27

Family

ID=14573420

Family Applications (1)

Application Number Title Priority Date Filing Date
JP11192079A Granted JPS5637814A (en) 1979-03-13 1979-08-31 Demodulating circuit for self-clocking information signal

Country Status (1)

Country Link
JP (1) JPS5637814A (en)

Also Published As

Publication number Publication date
JPS6348108B2 (en) 1988-09-27

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