JPH11306130A - Dma controller and data processing method thereof, and print controller and data processing method thereof - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently process two-way access between a CPU and a DMA avoiding an overrun in data transfer. SOLUTION: According to the analyzed state of inputted data, the access ratio of access to a RAM 2 from a CPU 1 and a direct memory access is varied by allowing a selector 102 to select one of signals generated by a counter 101 and the access to the memory from the CPU 1 and direct memory access are attributed at the varying access ratio. Consequently, the access ratio of the CPU access to the memory and direct memory access can dynamically be varied according to the inputted data and the access time of the continuous DMA can freely be adjusted according to the input data.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a D which collectively arbitrates direct memory access (DMA), CPU access and access to other memories from a plurality of sources.
The present invention relates to a data processing method of an MA control device and a DMA control device, a print control device, a data processing method of a print control device, and a storage medium storing a computer-readable program.

[0002]

2. Description of the Related Art Conventionally, a DMA controller which arbitrates direct memory access (DMA) from a plurality of sources, CPU access, and access to other memories collectively has to perform arbitration between DMAs from a plurality of sources. so,
It is configured to re-arbitrate the DMA request and the CPU and other requests for the source that has acquired the right to occupy the bus, or to arrange all the DMA, CPU and other requests in a flat manner and collectively unify them. ing.

[0003]

However, in each of the above-mentioned conventional examples, when arbitrating a DMA request and a CPU request in the highest hierarchy, only a fixed sequence based on a rule determined by hardware is used. Since it does not operate, complex data is transferred in a compressed form from an external device such as a host computer, and when the data is expanded, expanded, and video output, a frequent DMA request occurs and normal print data is generated. If a phenomenon (overrun) occurs that cannot be guaranteed, it cannot be avoided, and there is a problem that the resolution must be reduced and retransmitted, or retransmitted in the form of uncompressed data.

The present invention has been made to solve the above problems, and an object of the present invention is to provide a CPU for a memory.
Arbitration at the access ratio that fluctuates based on the analysis state of the input data between the access from the memory and the direct memory access, thereby expanding the data to the memory.
Even if a DMA request frequently occurs at the time of a data transfer request such as expansion or video output, the print data is normally transferred, and a transfer error, that is, a so-called overrun is avoided to prevent both the CPU and the DMA. Control device, a data processing method of the DMA control device, a print control device, a data processing method of the print control device, and a computer-readable program capable of freely preparing a memory access environment capable of efficiently processing access to the printer. It is an object of the present invention to provide a storage medium having stored therein.

[0005]

According to a first aspect of the present invention, there is provided a DMA control apparatus for controlling CPU access to a memory from a CPU and direct memory access from a plurality of sources. Counter means for counting a number of accesses and a number of direct memory accesses and generating a plurality of priority order switching signals for setting priorities so that an access ratio between CPU access and direct memory access to the memory is different; Analysis means for analyzing the stored data; and selection means for selecting one priority switching signal from a plurality of priority switching signals generated by the counter based on a result of the analysis of the data by the analysis means. Switching of one priority selected by the selection means Those having an arbitration unit as either the valid state of the CPU access and direct memory access, arbitrates the CPU access and direct memory access to the memory and the other as an invalid state based on the item.

According to a second aspect of the present invention, the analysis means analyzes the capacity of data stored in the memory.

In a third aspect according to the present invention, the analysis means analyzes a time required for developing data stored in the memory.

According to a fourth aspect of the present invention, the data is stored in the memory based on a predetermined page unit or band unit.

According to a fifth aspect of the present invention, the data is image data or text data.

According to a sixth aspect of the present invention, there is provided a print control apparatus for developing print data printable by a printing unit on a memory based on data input through a predetermined communication medium, The first memory access and the second memory access are performed such that a first memory access generated from a different source and a second memory access generated from a CPU have a different priority with respect to the memory based on a print data analysis result. It has arbitration means for arbitrating the second memory access.

According to a seventh aspect of the present invention, the arbitration means arbitrates the access time between the CPU access to the memory and the direct memory access from a plurality of sources at different ratios.

In an eighth invention according to the present invention, the arbitration means counts the number of CPU accesses to the memory and the number of direct memory accesses so that an access ratio between the CPU access and the direct memory access to the memory is different. Counter means for generating a plurality of priority order switching signals for setting priorities; analysis means for analyzing data stored in the memory; and generation means for the counter means based on an analysis result of the data by the analysis means. Selecting means for selecting one priority switching signal from a plurality of priority switching signals to be executed, and performing a CPU access and a direct memory access based on the one priority switching signal selected by the selecting means. One of the memos is set to the valid state and the other to the invalid state. It is intended to arbitrate the CPU access and direct memory access to.

In a ninth aspect according to the present invention, the analysis means analyzes the capacity of data stored in the memory.

[0014] In a tenth aspect according to the present invention, the analysis means analyzes a time required for developing data stored in the memory.

In an eleventh aspect according to the present invention, the data is stored in the memory based on a predetermined page unit or band unit.

According to a twelfth aspect of the present invention, the data is image data or text data.

According to a thirteenth aspect of the present invention, there is provided a data processing method of a DMA control device for controlling CPU access to a memory from a CPU and direct memory access from a plurality of sources.
A counter step of counting the number of accesses and the number of direct memory accesses and generating a plurality of priority switching signals for setting priorities so that the access ratio between CPU access and direct memory access to the memory is different; An analyzing step of analyzing the stored data; and a selecting step of selecting one priority switching signal from a plurality of priority switching signals generated by the counter means based on the analysis result of the data in the analysis step. , 1 selected in the selection step
An arbitration step of arbitrating the CPU access and the direct memory access to the memory with one of the CPU access and the direct memory access being enabled and the other being disabled based on the two priority switching signals. .

According to a fourteenth aspect of the present invention, in the analyzing step, the capacity of data stored in the memory is analyzed.

According to a fifteenth aspect of the present invention, in the analyzing step, the time required for developing the data stored in the memory is analyzed.

According to a sixteenth aspect of the present invention, the data is stored in the memory based on a predetermined page unit or band unit.

According to a seventeenth aspect of the present invention, the data is image data or text data.

According to an eighteenth aspect of the present invention, there is provided a data processing method of a print control apparatus for developing print data printable by a printing unit on a memory based on data input via a predetermined communication medium. The first memory access generated from a different source to the memory and the second memory access generated from the CPU based on the analysis result of the print data are prioritized at different ratios. An arbitration step for arbitrating between the memory access and the second memory access is provided.

According to a nineteenth aspect of the present invention, in the arbitration step, arbitration is performed at different ratios between the access time of the CPU access to the memory and the direct memory access from a plurality of sources.

According to a twentieth aspect of the present invention, in the arbitration step, the number of CPU accesses to the memory and the number of direct memory accesses are counted so that an access ratio between the CPU access and the direct memory access to the memory is different. A counter process for generating a plurality of priority switching signals for setting priorities; an analysis process for analyzing data stored in the memory; and a counter process for generating data based on an analysis result of the data by the analysis process. Selecting one priority switching signal from a plurality of priority switching signals to be executed, and performing a CPU access and a direct memory access based on the one priority switching signal selected in the selecting step. One of the menus is set to the valid state and the other to the invalid state. It is intended to arbitrate the CPU access and direct memory access to Li.

According to a twenty-first aspect of the present invention, in the analyzing step, the amount of data stored in the memory is analyzed.

According to a twenty-second aspect of the present invention, in the analyzing step, a time required for developing data stored in the memory is analyzed.

According to a twenty-third aspect of the present invention, the data is stored in the memory based on a predetermined page unit or band unit.

According to a twenty-fourth aspect of the present invention, the data is image data or text data.

[0029]

DESCRIPTION OF THE PREFERRED EMBODIMENTS [First Embodiment] FIG. 1 is a circuit block diagram illustrating the configuration of a DMA control device according to a first embodiment of the present invention. The DMA control device can be applied to a memory control circuit in the print control device according to the present invention.

In the drawing, reference numeral 101 denotes a counter for measuring the number of accesses, which measures the number of accesses for determining how many DMA accesses can be processed after one CPU access. Reference numeral 102 denotes a selector which selects an optimum signal for processing the corresponding page and band from a plurality of priority signals.

Reference numeral 103 denotes a JK flip-flop (JKF /
F), the default priority (CPU and DMA)
Can be processed alternately in an equivalent relationship). 1
Reference numeral 04 denotes an OR gate, which inputs a signal obtained by performing an OR process on CPU and DMA access last signals output from a sequencer (not shown) to a select terminal for switching the load / count-up of the counter 101.

Numeral 105 denotes an inverter gate (INV gate) which is simultaneously input by the NAND gates 106 and 107 in response to a CPU / DMA priority switching signal (DCPRI) output from the selector 102.
One of the PU and DMA request signals is set to be processable and the other is set to a non-processable state.

Reference numerals 108 and 109 denote AND gates.
After arbitration for activating the U and DMA accesses, a pulse is generated. 110 and 111 are DF
At / F, a synchronization pulse is sent from the outputs of the NAND gates 106 and 107 to a sequencer (not shown).

A CPU 1 executes a control program stored in the ROM 4 or an external memory (not shown) to control each device connected to the system bus 5 as a whole. Reference numeral 2 denotes a RAM, which functions as a work memory of the CPU 1, and has a page memory area, a band memory area, or the like, and is configured to be able to store compressed print data. The RAM 2 is configured so that its capacity can be expanded by an optional memory (not shown).

Reference numeral 3 denotes an external interface which can communicate with a host computer or the like via a communication medium (not shown) by a predetermined protocol. Reference numeral 6 denotes an engine controller which serially transfers image data (bitmap data) developed on the RAM 2 to the engine 7. The engine 7 includes a laser beam printer engine, an LED printer engine, an inkjet printer engine, and the like. Reference numeral 10 denotes a DMA controller (DMAC) that controls DMA for the RAM 2.

FIG. 2 is a circuit block diagram illustrating a detailed configuration of the counter 101 shown in FIG.

In the figure, reference numeral 201 denotes a selectable DF / F.
The output from the OR gate 104 is commonly input to the select input S, and the inverter gate 208 is input to the input a.
, The inverted output of the output Q is input. The output Q is input to the input b.

Reference numeral 202 denotes a selectable DF / F. The select input S receives the output of the OR gate 104 in common, and the input a has the output of the EXOR gate 211 and the output Q.
And the output Q is also input to the input b.

Reference numeral 203 denotes a selectable DF / F. The select input S receives the output of the OR gate 104 in common, and the input a receives the output of the AND gate 209 and the output Q via the EXOR gate 212. The exclusive ORed output is input, and the output Q is also input to input b.

Reference numeral 204 denotes a selectable DF / F. An output from the OR gate 104 is commonly input to the select input S, and the output a of the output of the AND gate 210 and the output Q is input to the input a via the EXOR gate 213. The exclusive ORed output is input, and the output Q is also input to input b.

Reference numeral 207 denotes a NAND gate.
/ F 201-204 with the inverted output Qn, that is, the DM output of one of the sources
In the state where the A request is generated, the signal PRI15 / 1 for processing with higher priority than the CPU request is output to the selector 102 up to 15 times in a row.

Reference numeral 206 denotes a NAND gate which is a selectable DF.
/ F 201-204 with the inverted output Qn, that is, the DM output of one of the sources
In the state where the A request has occurred, up to seven consecutive times,
A signal PRI7 / 1 for processing higher priority than the CPU request is output to the selector 102.

Reference numeral 205 denotes a NAND gate which is a selectable DF.
/ F 201-204 with the inverted output Qn, that is, the DM output of one of the sources
In the state where A request has occurred, up to three times
A signal PRI3 / 1 for processing higher priority than the CPU request is output to the selector 102.

Based on the above configuration, the first chart will be described with reference to the timing chart shown in FIG. 3 and the flowchart shown in FIG.
The operation of the embodiment will be described.

FIG. 3 is a timing chart for explaining the operation of the DMA control device according to the present invention.
This corresponds to the case where the CPRI becomes the signal PRI7 / 1.

In this embodiment, for the sake of simplicity, the switching signal DCPRI selected by the selector 102 is used.
Are processed seven times each time a DMA request is simultaneously input (signal P in FIG. 2).
RI7 / 1).

First, in a situation where no print request has been issued from an external interface such as a host computer, the selector 102 of the present DMA controller selects the output (signal PRI1 / 1) of the JKF / F 103 and the switching signal DCP
When the CPU last signal is input in the immediately preceding access from the sequence, the RI goes into the “H” state. At the time of arbitration of the next access, if the CPU and DMA requests are input simultaneously, the NAND gate 107 switches the switching signal DCPRI by the INV gate 105. Is inverted to the "H" state, while the NAND gate 106 switches the switching signals DCPRI, DMPRI.
Since both the A request signals are in the “H” state, the state changes to the “L” state.

Therefore, when there is no request from a source other than the CPU and DMA, D
MA request is processed with priority, that is, NAN
The CPU request is suspended by the D gate 106,
The ND gate 107 passes the DMA request.

Conversely, when a DMA last signal is input from a sequencer (not shown) in the immediately preceding access, DCPRI goes to the “L” state, and the arbitration of the next access causes the CPU and DM to be arbitrated.
When the requests of A are input simultaneously, the NAND gate 1
06 is in the “H” state, and the NAND gate 107 is in the “L” state, so that the CPU request is processed with priority.

At the time of the above default setting, the CP
It can be said that the U request and the DMA request can be processed alternately and have an equal relationship.

When a print request is generated from an external interface (not shown), print data is analyzed in the print control device including the DMA control device. At this time, external devices such as a host computer and the like analyze the print data in the form of compressed data. When one page of data or one band of data is transferred, the compressed data is expanded and expanded in a page memory such as a RAM, and the image data (bitmap data) is converted into serial data in the form of an engine. Is performed by DMA, so that DMA requests from a plurality of sources are ORed in the default setting.
In this way, the DMA request shown in FIG. 1 is obtained, and the frequency of occurrence of the DMA request per unit time is expected to be considerably high depending on the capacity of the transferred compressed data.

As a result, when high-resolution image data is transferred to the engine, development to the page memory cannot be performed in time,
A phenomenon (overrun) occurs in which output of normal video data cannot be guaranteed.

Therefore, for CPU and DMA requests input simultaneously, one CPU request process is performed for a plurality of DMA request processes, and the number of times can be specified by the capacity of the transferred compressed data. I do.

Further, information corresponding to the boundary value of the compressed data and the number of DMA request processing that can be inserted between the CPU request processing is stored in the ROM 4 or another memory resource (for example, a nonvolatile storage medium such as NVRAM) in the print control apparatus. Keep it.

Thus, when a print request is issued from the external interface, the amount of transfer data is analyzed in units of pages or bands, and the number of DMA request processes corresponding thereto is derived from the information in the ROM 4 described above.
Then, the priority switching register is accessed, and a value matching the previous number is set as the register signal 102A for the input S of the selector 102.

In this embodiment, if the signal PRI7 / 1 is selected as the output of the counter 101,
As shown in FIG. 2, the CPU last signal or the DMA
Is in the “H” state while the DF / F20 with select
Inputs b of 1 to 204 are selected and counted up by “1”.

The signal PRI7 / 1 becomes "L" after the reset value.
State (DMA priority), but DMA from multiple sources
In a situation where requests occur simultaneously and CPU requests occur simultaneously, the CPU request is processed first, and then the signal PRI7 / 1 changes from the "L" state to the "H" state.
State (DMA priority), and even if CPU requests are continuously input to the DMA controller,
The request is made when the signal PRI7 / 1 goes to the "H" state and the NAND gate 20 of the counter 101 shown in FIG.
6 is in the "L" state, that is, the state does not change to the "L" state until the counter value becomes "7 (h)". Therefore, in a state where a DMA request is always generated even in one of the plurality of sources, Up to seven consecutive requests can be processed with higher priority than CPU requests, and the default setting (CPU
In the case where the signal PRI1 / 1 having the same relationship as the DMA is set), the overrun data can be processed normally because the priority of the DMA is increased.

By repeating the above operation for each page or each band, even for complicated data in which a DMA request is frequently made, the priority of the DMA can be changed within a range in which the CPU does not run away, and the overrun is performed. Since the run can be prevented and the access processing of both the CPU and the DMA can be efficiently performed, the printer control device to which the DMA control device can be applied may overrun the printer engine even if the amount of analyzed data increases. Is suppressed, and normal printing can be performed.

Hereinafter, a characteristic configuration of the present embodiment will be described with reference to FIG.

C for the memory configured as described above
DMA controller (D) for controlling CPU access from PU1 and direct memory access from a plurality of sources
MAC 10), a plurality of priority switching signals for counting the number of CPU accesses to the memory and the number of direct memory accesses, and setting the priority so that the access ratio between the CPU access and the direct memory access to the memory is different. And a means for analyzing data stored in the memory (the CPU 1 executes a control program stored in the ROM 4 and outputs data (P
DL data) or dedicated hardware) and one of a plurality of priority switching signals generated by the counter means based on the result of the data analysis by the analysis means. Selection means (selector 102) for selecting a priority switching signal; one of CPU access and direct memory access being enabled based on one priority switching signal selected by the selection means, and the other being disabled Since there is arbitration means for arbitrating between the CPU access to the memory and the direct memory access as the state, the access ratio between the CPU access and the direct memory access to the memory can be dynamically varied according to input data. And the continuous DMA access freely according to the input data Between you can increase or decrease the.

Since the analysis means analyzes the capacity of the data stored in the memory, the access ratio between CPU access and direct memory access to the memory can be dynamically varied according to the capacity of the input data. The access time of the continuous DMA can be freely adjusted according to the capacity of the input data.

Further, since the analyzing means analyzes the time required for developing the data stored in the memory, the analysis means can determine whether the CP for the memory can be used in accordance with the time required for developing the input data.
The access ratio between the U access and the direct memory access can be dynamically changed, and the continuous DMA access time and the CPU access time can be freely adjusted according to the input data expansion processing time.

Since the data is stored in the memory based on a predetermined page unit or band unit, the access time of the continuous DMA can be freely set according to the data input in the predetermined page unit or band unit. CPU
You can adjust the access time.

Further, since the data is image data or text data, the continuous DMA access time and the CPU access time can be freely adjusted according to the image data or text data.

A printing control device (printer controller) for developing print data printable by a printing unit on a memory based on data input via a predetermined communication medium, wherein the print controller The first memory access and the second memory access are performed such that a first memory access generated from a different source and a second memory access generated from a CPU are given priority to the memory at different ratios based on the analysis result. Since the arbitration means (DMAC10) for arbitrating the memory access is provided, arbitration can be performed such that the first memory access has a higher priority than the second memory access at a different ratio according to the input print data. Even if the contents of the print data fluctuate, the optimal memory Seth becomes possible, thereby preventing the specific overrun occurs that depends on the print data.

Further, the arbitration means arbitrates the access time between the CPU access to the memory from the CPU and the direct memory access from a plurality of sources at different ratios, so that the first memory access and the second memory access can be arbitrated. The access time with the access can be freely changed.

The arbitration means counts the number of CPU accesses to the memory and the number of direct memory accesses, and sets a plurality of priorities so that the access ratio between the CPU access and the direct memory access to the memory is different. Counter means (counter 101) for generating a priority switching signal and analysis means (not shown) for analyzing data stored in the memory
And a selecting means (selector 102) for selecting one priority switching signal from a plurality of priority switching signals generated by the counter based on a result of analysis of the data by the analysis means, CP based on one priority switching signal selected by the selection means
One of the U access and the direct memory access is set to the valid state, and the other is set to the invalid state to arbitrate the CPU access to the memory and the direct memory access. The access ratio with access can be dynamically varied, and the access time of continuous DMA can be freely adjusted according to input data.

Further, since the analyzing means analyzes the capacity of the data stored in the memory, the access ratio between the CPU access and the direct memory access to the memory can be dynamically varied according to the capacity of the input data. The access time of the continuous DMA can be freely adjusted according to the capacity of the input data.

Further, the analyzing means analyzes the time required for developing the data stored in the memory.
It is possible to dynamically change the access ratio between the access and the direct memory access, and the continuous DMA access time and C
PU access time can be adjusted.

Further, since the data is stored in the memory on the basis of a predetermined page or band unit, the access time of the continuous DMA can be freely set according to the data inputted in the predetermined page unit or band unit. CPU
You can adjust the access time.

Since the data is image data or text data, the access time of the continuous DMA and the CPU access time can be freely adjusted according to the image data or the text data.

FIG. 4 is a flowchart showing an example of a data processing procedure in the DMA control device according to the present invention. Note that (1) to (6) indicate each step.

First, in step (1), the data analysis unit provided in the printer controller selects the selector 102.
Are set as default so that the priorities of the CPU and the DMA are equal.

Next, in step (2), the CPU 1 monitors the status of the print request and determines whether or not a print request has been issued. If it is determined that the print request has not been issued, the process is terminated. finish.

On the other hand, if it is determined in step (2) that the print request has occurred, in step (3), the original data for printing is analyzed for each page and each band. , Compression data capacity, and expansion time prediction.

Next, in step (4), the number of times of the DMA request processing corresponding to the information in the ROM 4 is derived based on the analyzed compressed data capacity, the expansion time prediction and the like. Then, the priority switching register is accessed, and a value matching the previous number is registered in the register signal 102.
A is set for the input S of the selector 102 as A.

Next, in step (5), the selector 102
Are based on the register signal 102A, the signals PRI3 / 1,
PRI7 / 1, PRI15 / 1 (signal PRIN / 1 (N
Is an integer of 3 or more)))
The print data is processed by successively accessing the DMA a predetermined number of times and retaining the CPU access. Thereby, the DMA
On the other hand, the priority (priority) of the CPU is reduced by the amount set in the register, and the frequent DMA can be pre-processed without overrun.

Next, it is determined whether or not the print request has been completed (6). If it is determined that the print request has been completed, the process returns to step (1).

On the other hand, if it is determined in step (6) that the print request has not been completed, the process returns to step (3), and the processing of steps (3) to (6) is repeated in the same manner.

Hereinafter, the characteristic configuration of this embodiment will be described with reference to FIG.

The memory (RAM
DMA controlling CPU access from CP1 and direct memory access from multiple sources for 2)
A data processing method for a control device (DMAC 10),
A counter step of counting the number of CPU accesses and the number of direct memory accesses to the memory and generating a plurality of priority switching signals for setting priorities so that the access ratio between the CPU access and the direct memory access to the memory is different ( (Not shown)
An analysis step (step (3) in FIG. 4) for analyzing data stored in the memory; and a plurality of priority switching signals generated by the counter step based on the result of the analysis of the data by the analysis step. A selection step (step (5) in FIG. 4) for selecting one priority switching signal from among them, and one of CPU access and direct memory access based on the one priority switching signal selected in the selection step An arbitration step of arbitrating CPU access and direct memory access to the memory with one being in a valid state and the other being in an invalid state.
The access ratio between PU access and direct memory access can be dynamically varied, and the access time of continuous DMA can be freely adjusted according to input data.

In the analyzing step, the capacity of data stored in the memory is analyzed, so that the access ratio between CPU access and direct memory access to the memory is dynamically varied according to the capacity of input data. The access time of the continuous DMA can be freely adjusted according to the capacity of the input data.

Further, the analyzing step analyzes the time required for developing the data stored in the memory.
The access ratio between the U access and the direct memory access can be dynamically changed, and the continuous DMA access time and the CPU access time can be freely adjusted according to the input data expansion processing time.

Since the data is stored in the memory on a predetermined page or band basis, the access time of the continuous DMA can be freely set in accordance with data input on a predetermined page or band basis. CPU
You can adjust the access time.

Further, since the data is image data or text data, the continuous DMA access time and the CPU access time can be freely adjusted according to the image data or text data.

A data processing method of a print control device for developing print data printable by a printing unit on a memory based on data input via a predetermined communication medium, comprising: The first memory access and the second memory are accessed such that a first memory access originating from a different source and a second memory access originating from the CPU have a different priority to the memory based on the result. Since there is an arbitration step (steps (3) to (5) in FIG. 4) for arbitrating access, the first memory access is different from the second memory access at a different ratio according to the input print data. Arbitration so that even if the contents of the print data fluctuate, the expansion processing can be completed within the allowable time set for the print data expansion to the memory. Mori access becomes possible, thereby preventing the specific overrun occurs that depends on the print data.

Further, the arbitration step arbitrates the access time between the CPU access to the memory from the CPU and the direct memory access from a plurality of sources at different ratios, so that the first memory access and the second memory access Access time can be freely changed.

The arbitration step counts the number of CPU accesses to the memory and the number of direct memory accesses, and sets a plurality of priorities so that the access ratio between the CPU access and the direct memory access to the memory is different. A counter step (not shown) for generating a priority switching signal, an analysis step for analyzing data stored in the memory (step (3) in FIG. 4), and a data analysis result based on the analysis step. A selecting step (step (5) in FIG. 4) of selecting one priority switching signal from a plurality of priority switching signals generated by the counter step, and the one priority selected by the selecting step Either CPU access or direct memory access based on the order switching signal Since the CPU access and the direct memory access to the memory are arbitrated while the valid state is set and the other is set to the invalid state, the access ratio between the CPU access and the direct memory access to the memory is dynamically varied according to input data. And the access time of the continuous DMA can be freely adjusted according to the input data.

Further, since the analyzing step analyzes the capacity of data stored in the memory, the access ratio between CPU access and direct memory access to the memory is dynamically varied according to the capacity of input data. The access time of the continuous DMA can be freely adjusted according to the capacity of the input data.

In the analyzing step, the processing time for expanding the data stored in the memory is analyzed.
It is possible to dynamically change the access ratio between the access and the direct memory access, and the continuous DMA access time and C
PU access time can be adjusted.

Further, since the data is stored in the memory based on a predetermined page or band unit, the access time of the continuous DMA can be freely set according to the data input in a predetermined page unit or band unit. CPU
You can adjust the access time.

Since the data is image data or text data, the continuous DMA access time and the CPU access time can be freely adjusted according to the image data or text data.

[Second Embodiment] In the first embodiment,
A case has been described in which the capacity of data to be transferred is made to correspond to the number of DMA accesses that can be performed up to one CPU access, and the priority of the DMA is made variable based on the information. Although the compression efficiency is low as in the case of repeated data of a pattern, depending on the processing method of the data, it is conceivable that the data may be quickly expanded in the page memory, and all the conditions for determining the parameters are not satisfied. Therefore, the compression format of the transferred data,
When compressing and transferring a font pattern using the pattern and text data as its constituent units, the number of times the same font is used is determined, and the data transferred from the external interface is transferred in units of one page or one band. The time it takes to analyze the data in units and expand it to the page memory is determined in advance by the RO in the print controller (not shown).
M is predicted from the information stored in M, and the priority of CPU access is lowered based on the estimated deployment time.
You may comprise so that the priority of A may be made variable.

As a result, more detailed analysis of the transfer data becomes possible, and the accesses of both the CPU and the DMA can be processed with high accuracy, and there is an effect that overrun is prevented.

Hereinafter, the configuration of a data processing program that can be read by a printing system to which the print control apparatus according to the present invention can be applied will be described with reference to a memory map shown in FIG.

FIG. 5 is a diagram for explaining a memory map of a storage medium for storing various data processing programs that can be read by a printing system to which the data processing apparatus according to the present invention can be applied.

Although not shown, information for managing a group of programs stored in the storage medium, for example, version information, a creator and the like are also stored, and information dependent on the OS or the like on the program reading side, for example, a program is stored. An icon or the like for identification display may also be stored.

Further, data subordinate to various programs is also managed in the directory. In addition, a program for installing various programs on a computer or a program for decompressing a program to be installed when the program to be installed is compressed may be stored.

The functions shown in FIG. 4 in this embodiment may be executed by a host computer by a program installed from the outside. In this case, the present invention is applied even when a group of information including a program is supplied to the output device from a storage medium such as a CD-ROM, a flash memory, or an FD, or from an external storage medium via a network. Things.

As described above, the storage medium storing the program codes of the software for realizing the functions of the above-described embodiment is supplied to the system or the apparatus, and the computer (or CPU or MP) of the system or the apparatus is supplied.
It goes without saying that the object of the present invention is also achieved when U) reads and executes the program code stored in the storage medium.

In this case, the program code itself read from the storage medium realizes the novel function of the present invention, and the storage medium storing the program code constitutes the present invention.

Examples of a storage medium for supplying the program code include a floppy disk, hard disk, optical disk, magneto-optical disk, CD-ROM, and C
DR, magnetic tape, nonvolatile memory card, RO
M, EEPROM and the like can be used.

When the computer executes the readout program code, not only the functions of the above-described embodiment are realized, but also the OS (Operating System) running on the computer based on the instruction of the program code. ) And the like perform part or all of the actual processing, and the processing realizes the functions of the above-described embodiments.

Further, after the program code read from the storage medium is written in a memory provided in a function expansion board inserted into the computer or a function expansion unit connected to the computer, based on the instruction of the program code, The CPU provided in the function expansion board or function expansion unit performs part or all of the actual processing,
It goes without saying that a case where the function of the above-described embodiment is realized by the processing is also included.

[0105]

As described above, the first embodiment according to the present invention is described.
According to the invention, there is provided a DMA control device for controlling CPU access to a memory from a CPU and direct memory access from a plurality of sources, wherein the DMA control device counts the number of CPU accesses and the number of direct memory accesses to the memory, Counter means for generating a plurality of priority switching signals for setting priorities so that the access ratio between CPU access and direct memory access to the memory is different; analysis means for analyzing data stored in the memory; Selecting means for selecting one priority switching signal from a plurality of priority switching signals generated by the counter means based on an analysis result of the data by the means; and one priority switching selected by the selecting means CPU access and direct based on signal An arbitration unit that arbitrates between CPU access to the memory and direct memory access by setting one of the memory accesses to a valid state and the other to an invalid state, so that the CPU access to the memory and the direct The access ratio with respect to memory access can be dynamically varied, and the access time of continuous DMA can be freely adjusted according to input data.

According to the second aspect, the analysis means analyzes the capacity of the data stored in the memory, so that the access between the CPU access and the direct memory access to the memory depends on the capacity of the input data. The ratio can be dynamically varied, and the access time of the continuous DMA can be freely adjusted according to the capacity of the input data.

According to the third aspect, the analyzing means analyzes the time required for developing the data stored in the memory, so that the CPU access to the memory and the direct memory The ratio of access to access can be dynamically varied, and the continuous DMA access time and CPU access time can be freely adjusted according to the input data expansion processing time.

According to the fourth aspect, the data is stored in the memory based on a predetermined page unit or a band unit. Therefore, the data can be freely set according to the data input in the predetermined page unit or the band unit. The continuous DMA access time and the CPU access time can be adjusted.

According to the fifth aspect, since the data is image data or text data, continuous DMA can be freely performed according to the image data or text data.
And the CPU access time can be adjusted.

According to the sixth aspect of the present invention, there is provided a print control apparatus for developing print data printable by a printing unit on a memory based on data input through a predetermined communication medium, The first memory access and the second memory access are performed in such a manner that a first memory access generated from a different source and a second memory access generated from the CPU are prioritized at different ratios with respect to the memory based on the analysis result. Arbitration means for arbitrating between the first memory access and the second memory access at different rates according to the input print data, and the content of the print data Even if the print data fluctuates, the optimal memory access that can complete the expansion processing within the allowable time set for the print data expansion to the memory becomes possible. A unique overrun occurs that depends on can be prevented.

According to the seventh aspect, the arbitration means arbitrates the access time between the CPU access to the memory from the CPU and the direct memory access from a plurality of sources at different ratios. The access time to the second memory access can be freely changed.

According to the eighth aspect, the arbitration means counts the number of CPU accesses to the memory and the number of direct memory accesses, and counts the number of accesses to the memory.
Counter means for generating a plurality of priority order switching signals for setting priorities so that the access ratio between PU access and direct memory access is different; analysis means for analyzing data stored in the memory; Selecting means for selecting one priority switching signal from among a plurality of priority switching signals generated by the counter means based on the analysis result of the data, wherein one priority selected by the selecting means is provided. Based on the switching signal, one of the CPU access and the direct memory access is set to the valid state, and the other is set to the invalid state to arbitrate the CPU access and the direct memory access to the memory. CPU access and direct memory access Ratio dynamically enables varying the can moderate the freely continuous DMA access time according to the input data.

According to the ninth aspect, the analyzing means analyzes the capacity of the data stored in the memory, so that the access between the CPU access and the direct memory access to the memory depends on the capacity of the input data. The ratio can be dynamically varied, and the access time of the continuous DMA can be freely adjusted according to the capacity of the input data.

According to the tenth aspect, the analyzing means includes:
Since the processing time for expanding the data stored in the memory is analyzed, it is possible to dynamically change the access ratio between CPU access and direct memory access to the memory according to the processing time for expanding the input data.
The continuous DMA access time and the CPU access time can be freely adjusted according to the input data expansion processing time.

According to the eleventh aspect, the data is stored in the memory based on a predetermined page unit or a band unit, so that the data can be freely set according to data input in a predetermined page unit or a band unit. The continuous DMA access time and the CPU access time can be adjusted.

According to the twelfth aspect, since the data is image data or text data, continuous DM can be freely performed according to the image data or text data.
The access time of A and the CPU access time can be adjusted.

According to the thirteenth aspect, C for the memory
A data processing method of a DMA control device for controlling CPU access from a PU and direct memory access from a plurality of sources, the method comprising counting the number of CPU accesses to the memory and the number of direct memory accesses to count the number of CPU accesses to the memory. A counter step of generating a plurality of priority switching signals for setting priorities so that the access ratio between the memory and the direct memory access is different; an analyzing step of analyzing data stored in the memory; and A selecting step of selecting one priority switching signal from a plurality of priority switching signals generated by the counter means based on the analysis result of the above, and based on one priority switching signal selected by the selecting step. CPU access and direct memory access Arbitration step of arbitrating CPU access and direct memory access to the memory with one of them as the valid state and the other as the invalid state, so that the CPU access and the direct memory access to the memory in accordance with the input data. Can be dynamically varied, and the continuous DMA access time can be freely adjusted according to the input data.

According to the fourteenth aspect, the analyzing step includes:
Since the capacity of data stored in the memory is analyzed,
CPU for memory according to the capacity of input data
The access ratio between the access and the direct memory access can be dynamically changed, and the access time of the continuous DMA can be freely adjusted according to the capacity of the input data.

According to the fifteenth aspect, the analyzing step includes:
Since the processing time for expanding the data stored in the memory is analyzed, it is possible to dynamically change the access ratio between CPU access and direct memory access to the memory according to the processing time for expanding the input data.
The continuous DMA access time and the CPU access time can be freely adjusted according to the input data expansion processing time.

According to the sixteenth aspect, the data is stored in the memory based on a predetermined page unit or a band unit. Therefore, the data can be freely set according to the data input in the predetermined page unit or the band unit. The continuous DMA access time and the CPU access time can be adjusted.

According to the seventeenth aspect, since the data is image data or text data, continuous DM can be freely performed according to the image data or text data.
The access time of A and the CPU access time can be adjusted.

According to the eighteenth aspect, there is provided a data processing method of a print control apparatus for developing print data printable by a printing unit on a memory based on data input via a predetermined communication medium. The first memory access is performed such that a first memory access generated from a different source and a second memory access generated from a CPU have a different priority to the memory based on an analysis result of the print data at a different ratio. And an arbitration step of arbitrating between the first memory access and the second memory access, so that the arbitration can be performed such that the first memory access takes precedence over the second memory access at a different ratio according to the input print data, Optimal memory access to complete the expansion processing within the allowable time set for print data expansion to memory even if the contents of print data fluctuates Next, a specific overrun occurs that depends on the print data can be prevented. According to the nineteenth aspect, the arbitration step includes the step of:
Since the access time between the U access and the direct memory access from a plurality of sources is arbitrated at different ratios, the access time between the first memory access and the second memory access can be freely changed.

According to the twentieth aspect, the arbitration step comprises:
A counter step of counting the number of CPU accesses to the memory and the number of direct memory accesses and generating a plurality of priority switching signals for setting priorities so that the access ratio between the CPU access and the direct memory access to the memory is different; An analyzing step of analyzing data stored in the memory; and one of a plurality of priority order switching signals generated by the counter step based on an analysis result of the data by the analyzing step.
Selecting one of the two priority switching signals,
Based on one priority switching signal selected in the selection step, one of the CPU access and the direct memory access is set to the valid state, and the other is set to the invalid state to arbitrate the CPU access and the direct memory access to the memory. Therefore, the access ratio between the CPU access and the direct memory access to the memory can be dynamically changed according to the input data, and the access time of the continuous DMA can be freely adjusted according to the input data.

According to the twenty-first aspect, the analyzing step includes:
Since the capacity of data stored in the memory is analyzed,
CPU for memory according to the capacity of input data
The access ratio between the access and the direct memory access can be dynamically changed, and the access time of the continuous DMA can be freely adjusted according to the capacity of the input data.

According to the twenty-second aspect, the analyzing step includes:
Since the processing time for expanding the data stored in the memory is analyzed, it is possible to dynamically change the access ratio between CPU access and direct memory access to the memory according to the processing time for expanding the input data.
The continuous DMA access time and the CPU access time can be freely adjusted according to the input data expansion processing time.

According to the twenty-third aspect, the data is stored in the memory based on a predetermined page unit or a band unit, so that the data can be freely set in accordance with the data input in the predetermined page unit or the band unit. The continuous DMA access time and the CPU access time can be adjusted.

According to the twenty-fourth aspect, since the data is image data or text data, continuous DM can be freely performed according to the image data or text data.
The access time of A and the CPU access time can be adjusted.

Therefore, even if a DMA request frequently occurs at the time of a data transfer request such as decompression, decompression, or video output to the memory, print data is transferred normally, and an overrun at the time of data transfer is prevented. It is possible to freely prepare a memory access environment which can avoid and efficiently process both accesses of the CPU and the DMA.

[Brief description of the drawings]

FIG. 1 is a circuit block diagram illustrating a configuration of a DMA control device according to a first embodiment of the present invention.

FIG. 2 is a circuit block diagram illustrating a detailed configuration of a counter shown in FIG.

FIG. 3 is a timing chart illustrating the operation of the DMA control device according to the present invention.

FIG. 4 is a flowchart illustrating an example of a data processing procedure in the DMA control device according to the present invention.

FIG. 5 is a diagram illustrating a memory map of a storage medium that stores various data processing programs that can be read by a printing system to which the data processing device according to the present invention can be applied.

[Explanation of symbols]

 1 CPU 2 RAM 3 External interface 4 ROM 5 System bus 101 Counter 102 Selector 103 JKF / F 104 OR gate 105 INV gate 106 NAND gate 107 NAND gate 108 AND gate 109 AND gate 110 DF / F 111 DF / F

Claims (24)

[Claims] 1. A DMA control device for controlling CPU access to a memory from a CPU and direct memory access from a plurality of sources, wherein the DMA controller counts the number of CPU accesses to the memory and the number of direct memory accesses to the memory. Counter means for generating a plurality of priority switching signals for setting priorities so that the access ratio between CPU access and direct memory access to the memory is different; analysis means for analyzing data stored in the memory; and analysis means Selecting means for selecting one priority switching signal from a plurality of priority switching signals generated by the counter means based on the analysis result of the data, and one priority switching signal selected by the selecting means Access and direct based on DMA controller, characterized in that it comprises an arbitration unit as either the valid state of the memory access, arbitrates the CPU access and direct memory access to the memory and the other as the invalid state, the. 2. The DMA control device according to claim 1, wherein said analysis means analyzes a capacity of data stored in said memory. 3. The DMA control device according to claim 1, wherein said analysis means analyzes a data development processing time of the data stored in said memory. 4. The DMA controller according to claim 1, wherein the data is stored in the memory based on a predetermined page unit or band unit. 5. The DMA control device according to claim 1, wherein said data is image data or text data. 6. A print control apparatus for developing print data printable by a printing unit on a memory based on data input via a predetermined communication medium, wherein the print control unit performs processing based on an analysis result of the print data. A first memory access originating from different sources to said memory and C
The first memory access and the second memory access so that the second memory access generated from the PU takes priority at a different ratio.
And a arbitration unit for arbitrating the memory access. 7. The arbitration means according to claim 1, wherein
7. The print control apparatus according to claim 6, wherein the access time between the CPU access from the PU and the direct memory access from a plurality of sources is adjusted at different ratios. 8. The arbitration means according to claim 5, wherein
Counter means for counting a number of PU accesses and a number of direct memory accesses, and generating a plurality of priority order switching signals for setting priorities so that an access ratio between CPU access and direct memory access to the memory is different; Analyzing means for analyzing data stored in the memory means, and selecting means for selecting one priority switching signal from a plurality of priority switching signals generated by the counter means based on the analysis result of the data by the analyzing means. CPU access to the memory and direct memory access to the memory with one of CPU access and direct memory access being enabled and the other being disabled based on one priority switching signal selected by the selection means. Features arbitration with access The print control apparatus according to claim 6. 9. The print control apparatus according to claim 8, wherein the analysis unit analyzes a capacity of data stored in the memory. 10. The print control apparatus according to claim 8, wherein said analysis means analyzes a time required for developing the data stored in said memory. 11. The print control device according to claim 8, wherein the data is stored in the memory based on a predetermined page unit or a band unit. 12. The data according to claim 8, wherein the data is image data or text data.
The print control device according to any one of the above. 13. A data processing method for a DMA controller which controls a CPU access to a memory from a CPU and a direct memory access from a plurality of sources, wherein the number of CPU accesses and the number of direct memory accesses to the memory are counted. A counter step of generating a plurality of priority switching signals for setting priorities so that an access ratio between CPU access and direct memory access to the memory is different; and an analyzing step of analyzing data stored in the memory. A selecting step of selecting one priority switching signal from a plurality of priority switching signals generated by the counter means based on a result of the analysis of the data by the analyzing step; CPU based on priority switching signal An arbitration step of arbitrating a CPU access and a direct memory access to the memory by setting one of the access and the direct memory access to an effective state and setting the other to an invalid state. Method. 14. The method according to claim 1, wherein the analyzing step analyzes an amount of data stored in the memory.
4. The data processing method of the DMA control device according to 3. 15. The data processing method for a DMA control device according to claim 13, wherein said analyzing step analyzes a data expansion processing time of data stored in said memory. 16. The DMA according to claim 13, wherein the data is stored in the memory based on a predetermined page unit or band unit.
A data processing method for the control device. 17. The data processing method according to claim 13, wherein the data is image data or text data.
6. The data processing method of the DMA control device according to any one of 6. 18. A data processing method of a print control device for developing print data printable by a printing unit on a memory based on data input via a predetermined communication medium, wherein the analysis of the print data is performed. A first memory access originating from a different source to the memory based on the result and C
The first memory access and the second memory access so that the second memory access generated from the PU takes priority at a different ratio.
A data processing method for a print control device, comprising an arbitration step of arbitrating between memory accesses. 19. The arbitration step includes the step of:
20. The data processing method for a print control device according to claim 18, wherein access times of CPU access from U and direct memory access from a plurality of sources are arbitrated at different ratios. 20. The arbitration step, wherein the number of CPU accesses to the memory and the number of direct memory accesses are counted, and a plurality of priorities are set so that an access ratio between the CPU access and the direct memory access to the memory is different. A counter step of generating a priority switching signal; an analyzing step of analyzing data stored in the memory; and a plurality of priority switching signals generated by the counter step based on an analysis result of the data by the analyzing step. A selecting step of selecting one of the priority switching signals from among the above, wherein one of the CPU access and the direct memory access is enabled based on the one priority switching signal selected in the selecting step, CPU access to the memory with the other disabled. 19. The method according to claim 18, wherein the arbitration is performed between the memory and the direct memory access.
The data processing method of the print control device according to the above. 21. The method according to claim 2, wherein the analyzing step analyzes an amount of data stored in the memory.
0. The data processing method of the print control device according to 0. 22. The data processing method for a print control device according to claim 20, wherein said analyzing step analyzes a time required for developing data stored in said memory. 23. The data processing method according to claim 18, wherein the data is stored in the memory based on a predetermined page unit or a band unit. 24. The data processing method according to claim 18, wherein the data is image data or text data.
3. The data processing method of the print control device according to any one of 3.