CN117422024A

CN117422024A - Data bit width conversion method, device, computer equipment and medium

Info

Publication number: CN117422024A
Application number: CN202311717821.2A
Authority: CN
Inventors: 刘伟; 卢圣才; 王洪良
Original assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Current assignee: Suzhou Metabrain Intelligent Technology Co Ltd
Priority date: 2023-12-14
Filing date: 2023-12-14
Publication date: 2024-01-19
Anticipated expiration: 2043-12-14
Also published as: CN117422024B

Abstract

The invention relates to the technical field of computers, and discloses a data bit width conversion method, a device, computer equipment and a medium, wherein the method comprises the following steps: acquiring a first indication state of a first indication signal and a second indication state of a second indication signal; controlling a write pointer to address in the annular cache register according to the first indication state to acquire first address information; controlling the read pointer to address in the annular cache register according to the second indication state to acquire second address information; determining a data bit width conversion state according to the first indication state, the second indication state, the first address information and the second address information; an operation corresponding to the data bit width transition state is performed on the input data and/or the output data. The mode is based on the FPGA internal state machine to control the read-write pointer to address in the annular buffer register, and compared with the traditional two-stage conversion, the design is simpler, more flexible and efficient, and the flexible and configurable bit widths of input data and output data can be realized.

Description

Data bit width conversion method, device, computer equipment and medium

Technical Field

The present invention relates to the field of computer technologies, and in particular, to a data bit width conversion method, a data bit width conversion device, a computer device, and a medium.

Background

In large digital circuit designs, a large project needs to be divided into several functional modules of unequal sizes. When data transmission is carried out between different modules, if the data bit widths are not matched, a bit width conversion function module is additionally added. The usual integer multiple of data bit width conversion can be accomplished by a simple shift control operation. However, when there is a non-integer bit width conversion like 2:3 or 3:2, the related methods may have drawbacks of being unable to migrate to other platforms; alternatively, although some methods are highly versatile and easy to migrate, the complexity may be too high while occupying more logic resources.

Disclosure of Invention

In view of this, the present invention provides a data bit width conversion method, apparatus, computer device and medium, so as to solve the problem that no relatively effective method in the related art can implement non-integer bit width conversion without being transplanted to other platforms, or implement non-integer bit width conversion with less occupied logic resources compared with the method that is relatively simple.

In a first aspect, the present invention provides a data bit width conversion method, which is applied to a data bit width conversion system, wherein a ring buffer register, a read pointer and a write pointer are configured in the data bit width conversion system, and the method includes:

Acquiring a first indication state of a first indication signal and a second indication state of a second indication signal;

controlling a write pointer to address in the annular cache register according to the first indication state to acquire first address information; controlling the read pointer to address in the annular cache register according to the second indication state to acquire second address information;

determining a data bit width conversion state according to the first indication state, the second indication state, the first address information and the second address information, wherein the data bit width conversion state is used for controlling input data to be input in a data input channel according to a first preset byte number, or feeding back a front end back pressure signal to control input data latch; and/or the data bit width conversion state is used for controlling output data to be output in a data output channel according to the second preset byte quantity, or feeding back a back end back pressure signal to control output data latch;

an operation corresponding to the data bit width transition state is performed on the input data and/or the output data.

The data bit width conversion method provided by the invention has the following advantages: the first indication state of the first indication signal is used for controlling the write pointer to address in the ring buffer register so as to acquire first address information indicated by the write pointer. And the second indication state of the second indication signal is used for controlling the read pointer to address in the annular buffer register and obtaining second address information indicated by the read pointer. And determining an address pointer difference value according to the first address information and the second address information. This pointer difference may then represent the number of positions in the ring buffer that are currently occupied. And further calculate the number of empty locations in the ring buffer register. The number of occupied locations may indicate a difference between the entered data and the outputted data. Further, it is possible to determine whether the data needs to be written or read continuously. Or writing and reading are performed simultaneously. Thus, the data bit width conversion state can be determined according to the first indication state, the second indication state and the address pointer difference value, wherein the data bit width conversion state is used for controlling input data to be input according to a first preset byte number in a data input channel, or feeding back a front end back pressure signal to control input data latch, and/or controlling output data to be output according to a second preset byte number in a data output channel, or feeding back a back end back pressure signal to control output data latch. In the mode, the read-write pointer is controlled to jump based on the internal state machine of the FPGA to address in the annular buffer register, and compared with the traditional two-stage conversion, the method has the advantages of simpler, more flexible and efficient design, and flexible and configurable bit widths of input data and output data can be realized. The method does not need to additionally introduce a third-party-width conversion IP, can be arbitrarily transplanted to any platform for execution, and does not need to occupy excessive logic resources. Furthermore, the method is not only applicable to non-integer multiple bit width conversion, but also applicable to integer multiple bit width conversion. More scenarios of user designs may be adapted.

In an alternative embodiment, determining the data bit width transition state based on the first indication state, the second indication state, the first address information, and the second address information includes:

determining an address pointer difference value according to the first address information and the second address information;

and determining the data bit width conversion state according to the first indication state, the second indication state and the address pointer difference value.

In an alternative embodiment, acquiring the first indication state of the first indication signal and the second indication state of the second indication signal specifically includes:

acquiring the current state of a preset data input effective indication signal, the current state of a data output effective indication signal and the current state of a preset output preparation signal;

identifying the current difference range of the pointer difference;

determining a first indication state according to the current state of the data input effective indication signal and the difference range of the data input effective indication signal and the address pointer;

and determining a second indication state according to the current state of the output preparation signal and the current state of the data output valid indication signal.

Specifically, the current state of the data input valid indication signal is used to indicate whether the input of the input is valid, the address pointer difference value is as described in the foregoing, and may indicate the difference between the input data and the output data, and if the difference between the input data and the output data is within the range of the difference value of the allowable input data and the current input data is valid data, it may be determined that the first indication state is valid, that is, the write pointer is controlled to address in the ring buffer register. Similarly, the current state of the output ready signal may indicate whether the output data is ready to be received. If the pointer is ready and the range of pointer differences is the range of differences that allows the output data, the second indication state is determined to be valid, thereby controlling the read pointer to address in the ring buffer.

In an alternative embodiment, the data bit width transition state includes: a first transition state, a second transition state, a third transition state, and a fourth transition state;

determining a data bit width transition state according to the first indication state, the second indication state, and the address pointer difference value, including:

when the first indication state and the second indication state are determined to be invalid at the same time, and the address pointer difference value is a preset value, determining that the data bit width conversion state is a first conversion state;

or when the first indication state and the second indication state are determined to be valid at the same time, and the address pointer difference value is any value in the intersection of the first difference value range and the second difference value range, determining that the data bit width conversion state is the second conversion state;

or when the first indication state is determined to be valid, the second indication state is determined to be invalid, and the address pointer difference value is any value in the first difference value range, determining that the data bit width conversion state is a third conversion state;

or when the first indication state is determined to be invalid, the second indication state is determined to be valid, and the address pointer difference value is any value in the first difference value range, determining that the data bit width conversion state is a fourth conversion state.

Specifically, when the first indication state and the second indication state are simultaneously invalid, it is indicated that the input data and the output data are simultaneously in the latch state, and it is determined that the data bit width transition state is the first transition state. Alternatively, the first address pointer difference value is in the intersection of the first difference range and the second difference range, which indicates that the address pointer difference value is within the difference range for indicating that the input data is allowed and within the difference range for indicating that the output data is allowed, and if the first indication state and the second indication state are simultaneously valid, the data bit width transition state may be determined to be the second transition state, that is, to indicate that the input and the output are simultaneously valid. Or if the first indication state is valid and the second indication state is invalid, the address pointer difference value is within the first difference value range, which indicates that only data is allowed to be input and data is not allowed to be output, and the data bit width conversion state can be determined to be a third conversion state; alternatively, if the second indication state is valid and the first indication state is invalid, the address pointer difference is within the second difference range, which indicates that only data is allowed to be output and data is not allowed to be input, and the data bit width transition state can be determined to be the fourth transition state.

In an alternative embodiment, performing an operation corresponding to a data bit width transition state on input data and/or output data specifically includes:

when the data bit width conversion state is the first conversion state, controlling the input data and the output data to be simultaneously latched;

or when the data bit width conversion state is the second conversion state, controlling input data to be input according to the first preset byte number in the data input channel, and controlling output data to be output according to the second preset byte number in the data output channel;

or when the data bit width conversion state is the third conversion state, controlling input data to be input in the data input channel according to the first preset byte number, and feeding back a back end back pressure signal for controlling output data to be latched;

or when the data bit width conversion state is the fourth conversion state, feeding back a front end back pressure signal for controlling the input data to be latched and controlling the output data to be output in the data output channel according to the second preset byte number.

In an alternative embodiment, the method further comprises:

when the data input channels comprise a plurality of data input channels, selecting a target data input channel from the plurality of data input channels in an arbitration mode to transmit input data; and/or when the data output channels comprise a plurality of data output channels, selecting a target data output channel from the plurality of data output channels in an arbitration mode to transmit output data.

Specifically, when the data input channel includes a plurality of data input channels, an optimal target data input channel may be selected from the plurality of data input channels in an arbitrating manner to transmit input data, and similarly, if the data output channel includes a plurality of data output channels, an optimal target data output channel may also be selected from the plurality of data output channels in an arbitrating manner to transmit output data.

In an alternative embodiment, the data input channel includes a plurality of data input channels, and selecting a target data input channel from the plurality of data input channels to transmit input data in an arbitrated manner includes:

acquiring a preconfigured priority of each data input channel;

selecting a data input channel with highest priority from the data input channels as a target data input channel, and transmitting input data by using the target data input channel;

and/or when the data output channel comprises a plurality of data output channels, selecting a target data output channel from the plurality of data output channels in an arbitration mode to transmit output data, wherein the method comprises the following steps of:

acquiring a preconfigured priority of each data output channel;

and selecting the data output channel with the highest priority in the data output channels as a target data output channel, and transmitting output data by using the target data output channel.

Specifically, when the target data input channel is selected in an arbitration manner, a preconfigured priority of each data input channel can be obtained in advance, then a data input channel with the highest priority in the data input channels is selected as the target data input channel, and input data is transmitted by using the target data input channel. Similarly, when the data output channels also include a plurality of data output channels, the target data output channel may be selected from the plurality of data output channels to transmit the output data in a similar manner.

polling each data input channel, and selecting any currently unoccupied data input channel as a target data input channel for transmitting input data;

and polling each data output channel, and selecting any currently unoccupied data output channel as a target data output channel for transmitting output data.

Specifically, in addition to the foregoing manner of implementing arbitration, a polling manner may also be employed to select a currently unoccupied data input channel from a plurality of data input channels as a target data input channel for transmitting input data. Similarly, a polling mode can be adopted to select a currently unoccupied data output channel from a plurality of data output channels as a target data output channel to transmit output data, so that load balancing is realized, and meanwhile, the data transmission efficiency is improved.

In an alternative embodiment, the data input channel comprises a plurality of data input channels, the method further comprising:

dividing input data into a plurality of input data fragments with the same number as the data input channel, and configuring identification information for each input data fragment;

and respectively distributing each input data segment to different data input channels for transmission, and combining a plurality of input data segments in a buffer queue according to the identification information of each input data segment to acquire input data.

Specifically, when the data input channel includes multiple data channels, besides the input data transmission and the output data transmission can be realized in the foregoing manner, it is also possible to consider that the input data is segmented into multiple input data segments, and identification information is configured for each input data segment and distributed to different data input channels for transmission, and the multiple input data segments are combined in the buffer queue according to the identification information of each input data segment, so as to obtain the input data.

In an alternative embodiment, the data output channel comprises a plurality of data output channels, the method further comprising:

dividing output data into a plurality of output data fragments with the same number as the data output channel, and configuring identification information for each output data fragment;

and respectively distributing each output data segment to different data output channels for transmission, and combining the plurality of output data segments in a buffer queue according to the identification information of each data segment to obtain output data.

Specifically, when the data output channel includes multiple data, besides the output data transmission and the output data transmission can be realized in the foregoing manner, it is also possible to consider that the output data is segmented into multiple output data segments, and identification information is configured for each output data segment and distributed to different data output channels for transmission, and the multiple output data segments are combined in the buffer queue according to the identification information of each output data segment, so as to obtain the output data.

In an alternative embodiment, the first indication state includes both an active and an inactive state;

when the current state of the data input valid indication signal is a valid state and the difference range of the address pointer difference value is a first difference range, determining that the first indication state is valid;

Or,

and when the current state of the data input valid indication signal is an invalid state and/or the difference range of the address pointer difference value is not in the first difference range, determining that the first indication state is invalid.

In an alternative embodiment, the boundary value of the first predetermined difference range is determined from the first predetermined number of bytes.

Specifically, since the input data is input according to the first preset number of bytes at a time, it is determined whether the input data can be input, and it is mainly seen whether there are at least the spare positions of the first preset number of bytes in the ring buffer register, and therefore, the boundary value of the first preset difference range is determined according to the first preset number of bytes.

In an alternative embodiment, the second indication state includes two types of valid state and invalid state, and the current state of the data output valid indication signal includes two types of valid and invalid;

when the difference range of the address pointer difference value is the second difference range, outputting the data to effectively indicate that the current state of the signal is an effective state; or when the difference range of the address pointer difference value does not belong to the second difference range, outputting the valid indication signal by the data, wherein the current state is an invalid state;

When the state of the output preparation signal is the effective state and the current state of the data output effective indication signal is the effective state, determining that the second indication state is effective;

or,

when the state of the output ready signal is an invalid state and/or when the current state of the data output valid indication signal is an invalid state, it is determined that the second indication state is invalid.

In an alternative embodiment, the boundary value of the second preset difference range is determined from the second preset number of bytes.

Specifically, since the output data is output according to the second preset number of bytes each time, it is determined whether the output data can be output, mainly whether at least the second preset number of bytes is not output in the ring buffer, that is, whether the occupied position in the ring buffer is greater than or equal to the second preset number of bytes, and therefore, the boundary value of the second preset difference range is determined according to the second preset number of bytes.

In an alternative embodiment, the input data is pre-stored in the input buffer queue for subsequent writing of the data from the input buffer queue to the ring buffer register;

and/or, the data read from the ring buffer is stored in the output buffer queue for subsequent reading of the data from the output buffer queue.

Specifically, input data may be first stored in the input buffer queue, and similarly, output data may be first stored in the output buffer queue, and data input and/or output may be controlled according to the data bit width conversion state.

In an alternative embodiment, the maximum data bit width of the ring buffer register is a preset integer multiple of the maximum of the first preset number of bytes and the second preset number of bytes.

Specifically, the ring buffer is used for storing input data and output data, and the input data and the output data need to be stored simultaneously in the conversion process. To ensure that input data and output data can be accommodated, the bit width of the register needs to be large enough. But in order to avoid taking up excessive memory resources, it may be set at least twice as large as the maximum of the input data bit width and the output data bit width, which may ensure that the ring buffer registers perform the shift operation of the data conveniently and that no data overflows during the shift process. The buffer, adjustment and synchronization of the data are realized, and the integrity and the correctness of the data are ensured.

In an alternative embodiment, when the first indication state is valid, controlling the write pointer to perform jump addressing in the ring buffer register according to a first preset byte number;

Alternatively, the pointer position of the write pointer in the ring buffer is unchanged when the first indication state is invalid.

In an alternative embodiment, when the second indication state is valid, controlling the read pointer to perform jump addressing in the ring buffer register according to a second preset byte number;

alternatively, the pointer position of the read pointer in the ring buffer is unchanged when the second indication state is invalid.

In an alternative embodiment, when performing an operation corresponding to a data bit width transition state on input data and/or output data, the method further comprises: the input data and the output data are asynchronously transmitted.

Specifically, by means of asynchronous transmission, in an ideal state, it can be ensured that the ring buffer register has no buffer data at a certain moment or in some cases, i.e. the input and output of the buffer data are all of them. Further improving the data bit width conversion efficiency.

In a second aspect, the present invention provides a data bit width conversion apparatus, the apparatus comprising:

the acquisition module is used for acquiring a first indication state of the first indication signal and a second indication state of the second indication signal;

the addressing module is used for controlling the write pointer to address in the annular cache register according to the first indication state to acquire first address information; controlling the read pointer to address in the annular cache register according to the second indication state to acquire second address information;

The processing module is used for determining a data bit width conversion state according to the first indication state, the second indication state, the first address information and the second address information, wherein the data bit width conversion state is used for controlling input data to be input in a data input channel according to a first preset byte number, or feeding back a front end back pressure signal to control input data latch; and/or the data bit width conversion state is used for controlling output data to be output in a data output channel according to the second preset byte quantity, or feeding back a back end back pressure signal to control output data latch;

and the execution module is used for executing the operation corresponding to the data bit width conversion state on the input data and/or the output data.

The data bit width conversion device provided by the invention has the following advantages:

the first indication state of the first indication signal is used for controlling the write pointer to address in the ring buffer register so as to acquire first address information indicated by the write pointer. And the second indication state of the second indication signal is used for controlling the read pointer to address in the annular buffer register and obtaining second address information indicated by the read pointer. And determining an address pointer difference value according to the first address information and the second address information. This pointer difference may then represent the number of positions in the ring buffer that are currently occupied. And further calculate the number of empty locations in the ring buffer register. The number of occupied locations may indicate a difference between the entered data and the outputted data. Further, it is possible to determine whether the data needs to be written or read continuously. Or writing and reading are performed simultaneously. Therefore, the data bit width conversion state can be determined according to the first indication state, the second indication state and the address pointer difference value, wherein the data bit width conversion state is used for controlling input data to be input according to a first preset byte number in a data input channel or feeding back a front end back pressure signal to control input data latch, and/or controlling output data to be output according to a second preset byte number in a data output channel or feeding back a back end back pressure signal to control output data latch. In the mode, the read-write pointer is controlled to jump based on the internal state machine of the FPGA to address in the annular buffer register, and compared with the traditional two-stage conversion, the method has the advantages of simpler, more flexible and efficient design, and flexible and configurable bit widths of input data and output data can be realized. The method does not need to additionally introduce a third-party-width conversion IP, can be arbitrarily transplanted to any platform for execution, and does not need to occupy excessive logic resources. Furthermore, the method is not only applicable to non-integer multiple bit width conversion, but also applicable to integer multiple bit width conversion. More scenarios of user designs may be adapted.

In a third aspect, the present invention provides a computer device comprising: the memory and the processor are in communication connection, computer instructions are stored in the memory, and the processor executes the computer instructions, so that the data bit width conversion method of the first aspect or any corresponding embodiment of the first aspect is executed.

In a fourth aspect, the present invention provides a computer readable storage medium having stored thereon computer instructions for causing a computer to perform the data bit width conversion method of the first aspect or any of its corresponding embodiments.

Drawings

In order to more clearly illustrate the embodiments of the present invention or the technical solutions in the prior art, the drawings that are needed in the description of the embodiments or the prior art will be briefly described, and it is obvious that the drawings in the description below are some embodiments of the present invention, and other drawings can be obtained according to the drawings without inventive effort for a person skilled in the art.

FIG. 1 is a flow chart of a data bit width conversion method according to an embodiment of the present invention;

FIG. 2 is a flow chart illustrating another method for converting data bit width according to an embodiment of the present invention;

FIG. 3 is a diagram of waveforms of signals in a handshake-based non-integer multiple data bit width conversion example provided by the present invention;

FIG. 4 is a master control diagram of a bit width conversion state machine provided by the present invention;

FIG. 5 is a block diagram of a non-integer multiple data bit width conversion processing method implementation based on handshaking;

FIG. 6 (1) is a schematic diagram of a read-write pointer jump status at a certain time according to the present invention;

FIG. 6 (2) is a schematic diagram of a read-write pointer jump status at another time point according to the present invention;

FIG. 6 (3) is a schematic diagram of a read-write pointer jump status at another time point according to the present invention;

FIG. 7 is a block diagram illustrating a data bit width conversion apparatus according to an embodiment of the present invention;

fig. 8 is a schematic diagram of a hardware structure of a computer device according to an embodiment of the present invention.

Detailed Description

For the purpose of making the objects, technical solutions and advantages of the embodiments of the present invention more apparent, the technical solutions of the embodiments of the present invention will be clearly and completely described below with reference to the accompanying drawings in the embodiments of the present invention, and it is apparent that the described embodiments are some embodiments of the present invention, but not all embodiments of the present invention. All other embodiments, which can be made by those skilled in the art based on the embodiments of the invention without making any inventive effort, are intended to be within the scope of the invention.

In the design of large-scale digital circuits, a large project is required to be divided into a plurality of functional modules with different sizes, and in order to ensure the reliable transmission of data, the related methods are mainly divided into two types: one type uses register latching, commonly used for single bit data transfers. Another type uses FIFO buffers or VALID-READY handshakes, commonly used for multi-bit data transfer.

If the data bit widths of the different modules are not matched, an additional bit width conversion function module is needed. The usual integer multiple of data bit width conversion can be accomplished by a simple shift control operation, and if there is a non-integer bit width conversion like 2:3 or 3:2, the related method can include: one is bit width conversion IP (e.g., AXI4-Stream DATA WIDTH Converter) integrated with a software development tool, and the other is to convert the input data bit width to the minimum of the two, and then amplify to the output data bit width. The first method has powerful IP integration function, can add a cutting part sideband signal at will, but cannot be transplanted to other platforms. The second method has strong universality and is convenient for transplanting, but each conversion can be completed by two steps, so that the complexity is improved and more logic resources are occupied.

To solve the above-described problems, embodiments of the present invention provide a data bit width conversion embodiment, and it should be noted that the steps illustrated in the flowcharts of the drawings may be performed in a computer system (computer device) including, for example, a set of computer executable instructions, and that although a logical order is illustrated in the flowcharts, in some cases, the steps illustrated or described may be performed in an order different from that herein.

In this embodiment, a data bit width conversion method is provided, which may be used in the above terminal device, such as a mobile phone, a tablet computer, etc., fig. 1 is a schematic flow diagram of a data bit width conversion method provided in an embodiment of the present invention, as shown in fig. 1, the method is applied to a data bit width conversion system, the data bit width conversion system is stored in an FPGA, a ring buffer register is configured in the data bit width conversion system, an FPGA internal state machine controls a read pointer and a write pointer, and addressing is performed in the ring buffer register, and a specific operation flow of the method is as follows:

step S101, acquiring a first indication state of the first indication signal and a second indication state of the second indication signal.

Step S102, the write pointer is controlled to address in the ring buffer register according to the first indication state, and first address information is obtained.

Step S103, the read pointer is controlled to address in the ring buffer according to the second indication state, and the second address information is obtained.

Specifically, the (first) indication state of the first indication signal is used to control the write pointer to address in the ring buffer register to obtain the first address information. The (second) indication state of the second indication signal is used for controlling the read pointer to address in the ring buffer register for obtaining the second address information. The first indication state and the second indication state herein refer to states of different signals, respectively, and do not refer to different state values of the same state.

The first indication state controls the write pointer to address in the ring buffer register for controlling whether the data is written or not, if the write pointer carries out jump addressing in the ring buffer register, the data is required to be written, and if the write pointer stops at a certain position, the data is not required to be written, and the data is latched. Similarly, if the read pointer performs jump addressing in the ring buffer register, it indicates that data needs to be read out, and if the read pointer is stationary at a certain position, it indicates that data does not need to be read out, and data latch is performed.

Step S104, determining the data bit width conversion state according to the first indication state, the second indication state, the first address information and the second address information.

Specifically, the first indication state is used for indicating whether the input is valid, i.e. whether the input is allowed, and the second indication state is used for indicating whether the output is valid, i.e. whether the output is allowed.

In an alternative embodiment, the address pointer difference value may be determined in advance from the first address information and the second address information. Then, determining the data bit width conversion state according to the first indication state, the second indication state and the address pointer difference value.

Wherein the address pointer difference value is used to indicate the currently occupied location in the ring buffer register. For example, a reservoir may include an inlet and an outlet, and the difference between the amount of water entering the inlet minus the amount of water exiting the outlet is the amount of water remaining in the reservoir. Similarly, the address pointer difference between the first address information and the second address information is used to indicate the number of data bytes currently still stored in the ring buffer register.

The data bit width conversion state can be used for controlling input data to be input in a data input channel according to a first preset byte number, or feeding back a front end back pressure signal to control input data latch;

And/or the data bit width conversion state can be used for controlling output data to be output in a data output channel according to the second preset byte number, or feeding back a back end back pressure signal to control output data latch.

Specifically, in a specific example, when the input data reaches a certain amount and the output speed of the output data does not catch up with the input speed of the input data, and the amount of data stored in the ring buffer register exceeds a certain threshold value, the input data latch needs to be controlled, and the output data is continuously output. Or when the amount of the input data stored in the buffer register is insufficient to output the output data according to the second preset byte number at a certain moment, the output latch needs to be controlled temporarily, the control input is valid, and the input data is continuously input. Or in some cases, it may be necessary to continuously input data and continuously output data to achieve a predetermined bit width conversion operation.

Therefore, in this embodiment, it is also necessary to include step S105 of performing an operation corresponding to the data bit width conversion state on the input data and/or the output data.

In the data bit width conversion method provided in this embodiment, the first indication state of the first indication signal is used to control the write pointer to address in the ring buffer register, so as to obtain the first address information indicated by the write pointer. And the second indication state of the second indication signal is used for controlling the read pointer to address in the annular buffer register and obtaining second address information indicated by the read pointer. And determining an address pointer difference value according to the first address information and the second address information. This pointer difference may then represent the number of positions in the ring buffer that are currently occupied. And further calculate the number of empty locations in the ring buffer register. The number of occupied locations may indicate a difference between the entered data and the outputted data. Further, it is possible to determine whether the data needs to be written or read continuously. Or writing and reading are performed simultaneously. Thus, the data bit width conversion state can be determined according to the first indication state, the second indication state and the address pointer difference value, wherein the data bit width conversion state is used for controlling input data to be input according to a first preset byte number in a data input channel, or feeding back a front end back pressure signal to control input data latch, and/or controlling output data to be output according to a second preset byte number in a data output channel, or feeding back a back end back pressure signal to control output data latch. In the mode, the read-write pointer is controlled to jump based on the internal state machine of the FPGA to address in the annular buffer register, and compared with the traditional two-stage conversion, the method has the advantages of simpler, more flexible and efficient design, and flexible and configurable bit widths of input data and output data can be realized. The method does not need to additionally introduce a third-party-width conversion IP, can be arbitrarily transplanted to any platform for execution, and does not need to occupy excessive logic resources. Furthermore, the method is not only applicable to non-integer multiple bit width conversion, but also applicable to integer multiple bit width conversion. More scenarios of user designs may be adapted.

In this embodiment, a data bit width conversion method is provided, which may be used in the above mobile terminal, such as a mobile phone, a tablet computer, etc., fig. 2 is a schematic flow chart of another data bit width conversion method provided in the embodiment of the present invention, as shown in fig. 2, and the flow chart includes the following steps:

step S201, a first indication state of the first indication signal and a second indication state of the second indication signal are obtained.

In an alternative embodiment, the acquisition of the first indication state and the second indication state may be achieved, in addition to being acquired by a preconfigured manner, by but not limited to:

in step S2011, a current state of the preconfigured data input valid indication signal, a current state of the data output valid indication signal, and a current state of the preconfigured output preparation signal are obtained.

Specifically, referring to fig. 3, a waveform diagram of each signal in a non-integer multiple data bit width conversion example of a handshake mechanism based on FPGA is illustrated in fig. 3, and fig. 3 is a 3:2 bit width conversion example. The data is inputted effectively when the data input effective indication signal in_valid and the reception preparation signal in_ready are simultaneously inputted effectively, and the data is outputted effectively when the data output effective indication signal out_valid and the transmission preparation signal out_ready are simultaneously inputted effectively. When the two are not satisfied at the same time, the data latch remains unchanged. Also included in fig. 3 are a clock signal CLK, an input data signal in_data, output valid data out_data, and the like. The data is hexadecimal data. The high level state of each signal is an active state, the low level state is an inactive state, and the exception is that the rising edge of the clock signal is an active state.

In this step, mainly, the current state of the data input valid indication signal and the current state of the output preparation signal are involved.

In step S2012, the difference range to which the pointer difference currently belongs is identified.

In particular, in an alternative embodiment, the setting of the difference range may also include one or more different ranges based on the difference in bit width conversion ratio between the input data and the output data. For example, taking the bit width conversion of the input data and the output data in fig. 3 as an example, the difference range may include two different ranges. For example, a first range of differences and a second range of differences may be included.

Step S2013, determining a first indication state according to the current state of the data input valid indication signal and the difference range to which the difference value from the address pointer belongs.

The method comprises the steps of,

step S2014, determining a second indication state according to the current state of the output preparation signal and the current state of the data output valid indication signal.

Specifically, the first indication state is mainly used for determining whether to allow data input, so that the specific state type can be determined according to the current state of the data input valid indication signal and the difference range of the address pointer difference value. The second indication state is mainly used for determining whether data output is allowed or not, so that the specific state type can be determined according to the current state of the output preparation signal and the difference range of the address pointer difference value.

Further, in an alternative embodiment, the first indication state includes an active state and an inactive state.

or,

The boundary value of the first preset difference range is determined according to the first preset byte number.

Further, in an alternative embodiment, the second indication state includes two types of valid state and invalid state; the current state of the data output valid indication signal comprises two types of valid and invalid;

or,

In an alternative embodiment, the boundary value of the second predetermined difference range is determined from the second predetermined number of bytes.

Step S202, the write pointer is controlled to address in the ring buffer register according to the first indication state, and first address information is obtained.

Step S203, and controlling the read pointer to address in the ring buffer according to the second indication state, so as to obtain the second address information.

Step S204, determining the data bit width conversion state according to the first indication state, the second indication state, the first address information and the second address information.

Step S205, an operation corresponding to the data bit width transition state is performed on the input data and/or the output data.

For the description of step S202 and step S205, please refer to step S102 and step S105 in the embodiment shown in fig. 1 in detail, and the detailed description is omitted herein.

In an optional implementation manner, on the basis of any of the foregoing embodiments, a data bit width conversion method flow is provided in this embodiment, and may be used in the foregoing mobile terminal, such as a mobile phone, a tablet computer, etc., where the following is mainly introduced in the method flow:

the data bit width transition state includes: a first transition state, a second transition state, a third transition state, and a fourth transition state. And determining a data bit width transition state according to the first indication state, the second indication state and the address pointer difference value, comprising the following method steps:

And step A1, when the first indication state and the second indication state are determined to be invalid at the same time and the address pointer difference value is a preset value, determining the data bit width conversion state as a first conversion state.

Or, in step A2, when it is determined that the first indication state and the second indication state are both valid, and the address pointer difference is any value in the intersection of the first difference range and the second difference range, it is determined that the data bit width transition state is the second transition state.

Or, in step A3, when the first indication state is determined to be valid, the second indication state is determined to be invalid, and the address pointer difference is any value in the first difference range, the data bit width transition state is determined to be the third transition state.

Or, in step A4, when the first indication state is determined to be invalid, the second indication state is determined to be valid, and the address pointer difference is any value in the first difference range, the data bit width transition state is determined to be the fourth transition state.

Specifically, when the first indication state and the second indication state are simultaneously invalid, it is indicated that the input data and the output data are simultaneously in the latch state, and it is determined that the data bit width transition state is the first transition state. Or, the first address pointer difference value is in the intersection of the first difference value range and the second difference value range, and the address pointer difference value is indicated to be in the difference value range for indicating the permission of input data and the difference value range for permitting output data, and if the first indication state and the second indication state are simultaneously valid, the data bit width conversion state can be determined to be the second conversion state, that is, the data bit width conversion state is used for indicating that the input and the output are simultaneously valid. Or if the first indication state is valid and the second indication state is invalid, the address pointer difference value is within the first difference value range, which indicates that only data is allowed to be input and data is not allowed to be output, and the data bit width conversion state can be determined to be a third conversion state; alternatively, if the second indication state is valid and the first indication state is invalid, the address pointer difference is within the second difference range, which indicates that only data is allowed to be output and data is not allowed to be input, and the data bit width transition state can be determined to be the fourth transition state.

Referring specifically to fig. 4, a master control diagram of a bit width transition state machine is illustrated in fig. 4, and fig. 4 includes four states S0, S1, S2, and S3, where S0 corresponds to the first transition state, S1 corresponds to the second transition state, S2 corresponds to the third transition state, and S3 corresponds to the fourth transition state.

The four transition states are jumped based on different jump conditions. The specific jump condition is the condition corresponding to each transition state described above, for example, jumping to the first transition state requires that the first indication state and the second indication state are simultaneously invalid, and the address pointer difference is a preset value, in a specific example, the preset value is 0. For another example, when the jump is to the second transition state, the first indication state and the second indication state are required to be valid at the same time, and the address pointer difference is any value in the intersection of the first difference range and the second difference range, only the first indication state and the second indication state are shown to be valid at the same time, and the limiting condition of the address pointer difference is not shown in the figure because of the limited display position, and other jump states are similar and are not repeated here.

In an alternative implementation manner, based on the foregoing method embodiment, according to the data bit width conversion state, input data is controlled to be input or latched in a data input channel according to a first preset byte number; and/or according to the data bit width conversion state, controlling output data to be output or latched in a data output channel according to a second preset byte number, wherein the method specifically comprises the following steps:

and B1, controlling the input data and the output data to be simultaneously latched when the data bit width conversion state is the first conversion state.

Or, in step B2, when the data bit width conversion state is the second conversion state, the input data is controlled to be input according to the first preset byte number in the data input channel, and the output data is controlled to be output according to the second preset byte number in the data output channel.

Or, in step B3, when the data bit width conversion state is the third conversion state, the input data is controlled to be input in the data input channel according to the first preset byte number, and the back end back pressure signal is fed back to control the output data to be latched.

Or,

and B4, when the data bit width conversion state is the fourth conversion state, feeding back a front end back pressure signal for controlling input data to latch and controlling output data to be output in a data output channel according to the second preset byte number.

Specifically, as described above, if the first transition state is the first transition state, it indicates that both the input and the output are invalid at present, and the data latch state is performed at this time. Then, when the data bit width conversion state is determined to be the second conversion state, the input data can be controlled to be input according to the first preset byte number, for example, 3 bytes. The output data is then controlled to be output in 2 bytes. When the data bit width transition state is the third transition state, the input data may be controlled to be input in 3 bytes and the output data may be latched. If the data bit width conversion state is the fourth conversion state, the front end back pressure signal is fed back to control the input data to latch and control the output data to output according to 2 bytes.

As an example, for example, at the beginning, both the input and output are 0, which is the first transition state. When the first transition state is changed into the second transition state, 3 bytes of data are input, and 2 bytes of data are output. Only one byte of data remains in the ring buffer at this time. The 2 byte output can no longer be guaranteed so the output latch at the next time only the input is valid. That is, the third transition state is skipped, the back pressure is output backward, the 3-byte data is controlled to be input, and the latch is output. At this time, 4 bytes of data are input, and at the next time, 2 bytes of data can be output. The remaining 2 bytes of data can be output with no data input for a while. Then a fourth transition state may be entered to output back-pressure onward, input latch, and output 2 bytes of data. At the next moment thereafter, the first transition state is entered because both the input and the output are 0.

Referring to fig. 5, a block diagram of a non-integer multiple data bit width conversion processing method based on handshake is illustrated in fig. 5.

Including a data input valid indication signal, an input data signal, a reception preparation signal, a data output valid indication signal, an output data signal, an output preparation signal, etc. In the schematic diagram, the data transmission device comprises an input buffer queue, a data transmission device and an output buffer queue, wherein the data transmission device comprises a specific transmission link and a ring buffer register. A specific transmission link comprises, for example, an input data transmission channel and an output data transmission channel.

In fig. 5, the input data (valid signal) is shown to be stored in the input buffer queue in advance, and in fact, the input data valid indication signal may be included and may also be added to the input queue. Then, output is performed in the input buffer queue, that is, the data output valid indication signal 0 and the output data signal 0 illustrated in fig. 5, after entering the data transmission device, after performing bit width conversion by the data transmission device, the generated output data (the input data signal 1 in fig. 5) with the second preset byte number is input into the output buffer queue in the form of an "input signal" for buffering, and then continuous output is performed in the buffer queue, such as the output data signal 1 shown in fig. 5. Similarly, the data input valid indication signal 0 is changed into the data output valid indication signal 0 after passing through the input buffer queue, and then is changed into the data input valid indication signal 1 (actually, the data output valid indication signal) after passing through the data transmission device, and then is continuously output after passing through the buffer queue. On the contrary, the output ready signal 1 needs to be changed to the reception ready signal 0 through the output buffer queue, the data transmission device and the output buffer queue, respectively.

Similarly, when the second indication state is valid, controlling the read pointer to carry out jump addressing in the ring buffer register according to the second preset byte quantity;

Referring specifically to fig. 6 (1) -6 (3), the read-write pointer jump status is schematically shown in fig. 6 (1) -6 (3), respectively. Taking the handshake-based 3:2 data bit width conversion control flow as an example, fig. 6 (1) shows that at a certain time, when the write pointer indicates position 3, the read pointer indicates position 0, and fig. 6 (2) shows that at another time, when the write pointer indicates position 4, the read pointer indicates position 2. Similarly, fig. 6 (3) shows that at another time, when the write pointer indicates a position of 1, the read pointer indicates a position of 4.

Hereinafter, the above method flow will be described by taking a handshake-based 3:2 data bit width conversion control flow and a handshake-based 2:3 data bit width conversion control flow as examples, respectively. See in particular below. First, a handshake-based 3:2 data bit width conversion control flow is introduced.

Input active in=in_valid & (buf_cnt < 4), output active: out_valid & & out ready. Wherein out_valid= (buf_cnt > 1) is output. Here buf_cnt represents the address pointer difference. In this example, buf_cnt <4 is set to be valid, considering that the maximum bit width in the ring buffer register is 6 (twice 3), and 3 bytes are required for each input of input data, so that at least 3 bytes of positions in the ring buffer register must be left free for data to be input. If at least 3 byte positions are said to be empty, then the current occupied position in the ring buffer register needs to be at most 3, i.e. buf_cnt is less than or equal to 3, i.e. buf_cnt <4, at which time the input is valid. Meanwhile, since the number of bytes output is 2 bytes, it is necessary to ensure that the output is valid only when there are at least 2 bytes of data in the ring buffer register, and thus, out_valid= (buf_cnt > 1) is output.

Hereinafter, the description is made based on four data bit width transition states, respectively.

S0 state, address pointer difference buf_cnt=0. That is, let us assume that we have a read pointer and a write pointer simultaneously of 0 as the starting instants. Then, when it is necessary to jump to the S1 state, the first indication state and the second indication state are required to be valid at the same time, and the address pointer difference value is any value in the intersection of the first difference range and the second difference range.

That is, in_active, out_valid & & out ready are valid simultaneously, and in_valid, out_valid, out ready are valid simultaneously at this time, and buf_cnt is only 2 and 3. Referring specifically to table 1, table 1 shows the skip situation of four states at different times after the read pointer and the write pointer are both 0 at time 0 and buf_cnt is 0. When buf_cnt is 2, buf_cnt is updated to 3, and if the state is still maintained at S1 at this time, buf_cnt is updated to 4.

TABLE 1

The method comprises the steps of setting a bit flip flag bit in the highest bit of a write pointer wptr and a read pointer rptr, and indicating whether current read-write operation is the same cycle operation or not, if the current operation is the same cycle operation, a current buffer counter buf_cnt is the difference between the write pointer and the read pointer, and if the current operation is not the same cycle, the writing operation is faster than the read operation by one cycle, and at the moment, the buffer counter buf_cnt is the write pointer plus the maximum buffer size of buf_reg and then the read pointer is subtracted.

It should be noted that, in any table in the embodiment of the present application, whether in_valid, out_valid, out ready, etc. are valid or not is set in advance, and the table is only used for explaining one skip condition of four transition states at different times and under different conditions.

Similar theory, S2 state: at this time, only the effective in_active is input, the back pressure is output, only the data can be cached, four conditions of 0, 1, 2 and 3 exist in the buf_cnt, and when the buf_cnt is 0, the buf_cnt is updated to 3; when buf_cnt is 1, updating buf_cnt to 4; when buf_cnt is 2, updating buf_cnt to 5; when buf_cnt is 3, buf_cnt is updated to 6.

The specific details are shown in tables 2 to 5:

TABLE 2

TABLE 3 Table 3

TABLE 4 Table 4

TABLE 5

S3 state: at this point the output is ready, but the input is invalid, only the buffered data can be output, with buf_cnt minus 2 for each output, see in particular table 6.

TABLE 6

The handshake-based 2:3 data bit width conversion control flow is described below:

input active in=in_valid & (buf_cnt < 5), output active: out_valid= (buf_cnt > 2) & outleady.

When the effective wptr=wptr+2 is input, when the effective rptr=rptr+3 is output, and also when wptr or rptr exceeds the maximum buffer size after self-addition, the jump is automatically made to the starting point and then the self-addition is performed.

S1 state: at the moment, the active in_active is input and ready is output at the same time, so that the active in_active can be buffered and output at the same time, the buf_cnt only has two conditions of 3 and 4, when the buf_cnt is 3, the buf_cnt is updated to 2, and when the buf_cnt is 4, the buf_cnt is updated to 3. See in particular table 7.

TABLE 7

S2 state: at this time, only the effective in_active is input, the back pressure is output, only the data can be cached, the buf_cnt has five conditions of 0, 1, 2, 3 and 4, and when the buf_cnt is 0, the buf_cnt is updated to 2; when buf_cnt is 1, updating buf_cnt to 3; when buf_cnt is 2, updating buf_cnt to 4; when buf_cnt is 3, updating buf_cnt to 5; when buf_cnt is 4, buf_cnt is updated to 6. See tables 8 and 9, respectively.

TABLE 8

TABLE 9

S3 state: at this point the output is ready, but the input is invalid, only the buffered data can be output, with buf_cnt decremented by 3 for each output. Specifically, the table 10 shows the results.

Table 10

In an alternative embodiment, the method may further comprise: when the data input channels comprise a plurality of data input channels, selecting a target data input channel from the plurality of data input channels in an arbitration mode to transmit input data; and/or when the data output channels comprise a plurality of data output channels, selecting a target data output channel from the plurality of data output channels in an arbitration mode to transmit output data.

step C1, obtaining a preconfigured priority of each data input channel;

step C2, selecting a data input channel with the highest priority in the data input channels as a target data input channel, and transmitting input data by using the target data input channel;

step D1, obtaining the preconfigured priority of each data output channel;

and D2, selecting the data output channel with the highest priority in the data output channels as a target data output channel, and transmitting output data by using the target data output channel.

Specifically, the priorities of the data input channel and the data output channel may be configured in advance according to actual needs, for example, according to the channel transmission rate. Then, when data is input or output subsequently, the channel with high priority is preferentially considered for transmission.

Specifically, besides the above-mentioned method, the data input channel with the highest priority can be selected, and the data input channel which is not occupied at present can be considered to be checked as the target data input channel, so that the data transmission efficiency is improved. Similarly, an unoccupied data output channel may be selected as the target data output channel for outputting data.

In an alternative embodiment, the data output channel includes a plurality of data output channels, the method further comprising:

In the two embodiments, the principle is similar, that is, the input data may be considered to be transmitted in slices, and/or the output data may be considered to be transmitted in distribution, and finally, the plurality of data segments may be integrated to obtain the input data, and/or the output data.

The embodiment also provides a data bit width conversion device, which is used for implementing the foregoing embodiments and preferred embodiments, and is not described in detail. As used below, the term "module" may be a combination of software and/or hardware that implements a predetermined function. While the means described in the following embodiments are preferably implemented in software, implementation in hardware, or a combination of software and hardware, is also possible and contemplated.

The present embodiment provides a data bit width conversion device, as shown in fig. 7, including: an acquisition module 701, an addressing module 702, a processing module 703, and an execution module 704.

An obtaining module 701, configured to obtain a first indication state of the first indication signal and a second indication state of the second indication signal;

The addressing module 702 is configured to control the write pointer to address in the ring buffer according to the first indication state, so as to obtain first address information; controlling the read pointer to address in the annular cache register according to the second indication state to acquire second address information;

the processing module 703 is configured to determine a data bit width conversion state according to the first indication state, the second indication state, the first address information, and the second address information, where the data bit width conversion state is used to control input data to be input in the data input channel according to the first preset byte number, or feedback a front end back pressure signal to control input data latch; and/or the data bit width conversion state is used for controlling output data to be output in a data output channel according to the second preset byte quantity, or feeding back a back end back pressure signal to control output data latch;

an execution module 704 is configured to perform an operation corresponding to the data bit width transition state on the input data and/or the output data.

In an alternative embodiment, the obtaining module 701 is specifically configured to:

Identifying the current difference range of the pointer difference;

In an alternative embodiment, the first indication state includes both an active and an inactive state; when the current state of the data input valid indication signal is a valid state and the difference range of the address pointer difference value is a first difference range, determining that the first indication state is valid;

or,

In an alternative embodiment, the second indication state includes two types of valid state and invalid state;

the current state of the data output valid indication signal comprises two types of valid and invalid;

or,

In an alternative embodiment, the data bit width transition state includes: a first transition state, a second transition state, a third transition state, and a fourth transition state; the processing module 703 is specifically configured to:

In an alternative embodiment, execution module 704 is specifically configured to: when the data bit width conversion state is the first conversion state, controlling the input data and the output data to be simultaneously latched;

In an alternative embodiment, execution module 704 is specifically configured to:

when the first indication state is valid, controlling the write pointer to carry out jump addressing in the ring buffer register according to the first preset byte quantity;

When the second indication state is valid, controlling the read pointer to carry out jump addressing in the annular cache register according to the second preset byte quantity;

In an alternative embodiment, the processing module 703 is further configured to select, in an arbitrated manner, a target data input channel from the plurality of data input channels to transmit the input data when the data input channel includes a plurality of data input channels; and/or when the data output channels comprise a plurality of data output channels, selecting a target data output channel from the plurality of data output channels in an arbitration mode to transmit output data.

In an alternative embodiment, the processing module 703 is specifically configured to:

acquiring a preconfigured priority of each data input channel;

Acquiring a preconfigured priority of each data output channel;

In an alternative embodiment, the data input channel includes a plurality of input data segments, and the processing module 703 is further configured to divide the input data into a number of input data segments equal to the number of the data input channels, and configure identification information for each of the input data segments;

In an alternative embodiment, the data output channel includes a plurality of output data segments, and the processing module 703 is further configured to divide the output data into a number of output data segments equal to the number of the data output channels, and configure identification information for each of the output data segments;

In an alternative embodiment, the input data and the output data are transmitted asynchronously.

The data bit width conversion device in this embodiment is presented in the form of a functional module, where the module refers to an application specific integrated circuit (Application Specific Integrated Circuit, abbreviated as ASIC), a processor and a memory that execute one or more software or firmware programs, and/or other devices that can provide the above-described functionality.

Further functional descriptions of the above respective modules and units are the same as those of the above corresponding embodiments, and are not repeated here.

The data bit width conversion device provided by the embodiment of the invention is characterized in that the first indication state of the first indication signal is used for controlling the write pointer to address in the annular cache register so as to acquire the first address information indicated by the write pointer. And the second indication state of the second indication signal is used for controlling the read pointer to address in the annular buffer register and obtaining second address information indicated by the read pointer. And determining an address pointer difference value according to the first address information and the second address information. This pointer difference may then represent the number of positions in the ring buffer that are currently occupied. And further calculate the number of empty locations in the ring buffer register. The number of occupied locations may indicate a difference between the entered data and the outputted data. Further, it is possible to determine whether the data needs to be written or read continuously. Or writing and reading are performed simultaneously. Therefore, the data bit width conversion state can be determined according to the first indication state, the second indication state and the address pointer difference value, wherein the data bit width conversion state is used for controlling input data to be input according to a first preset byte number in a data input channel or feeding back a front end back pressure signal to control input data latch, and/or controlling output data to be output according to a second preset byte number in a data output channel or feeding back a back end back pressure signal to control output data latch. In the mode, the read-write pointer is controlled to jump based on the internal state machine of the FPGA to address in the annular buffer register, and compared with the traditional two-stage conversion, the method has the advantages of simpler, more flexible and efficient design, and flexible and configurable bit widths of input data and output data can be realized. The method does not need to additionally introduce a third-party-width conversion IP, can be arbitrarily transplanted to any platform for execution, and does not need to occupy excessive logic resources. Furthermore, the method is not only applicable to non-integer multiple bit width conversion, but also applicable to integer multiple bit width conversion. More scenarios of user designs may be adapted.

The embodiment of the invention also provides computer equipment, which is provided with the data bit width conversion device shown in the figure 7.

Referring to fig. 8, fig. 8 is a schematic structural diagram of a computer device according to an alternative embodiment of the present invention, as shown in fig. 8, the computer device includes: one or more processors 10, memory 20, and interfaces for connecting the various components, including high-speed interfaces and low-speed interfaces. The various components are communicatively coupled to each other using different buses and may be mounted on a common motherboard or in other manners as desired. The processor may process instructions executing within the computer device, including instructions stored in or on memory to display graphical information of the GUI on an external input/output device, such as a display device coupled to the interface. In some alternative embodiments, multiple processors and/or multiple buses may be used, if desired, along with multiple memories and multiple memories. Also, multiple computer devices may be connected, each providing a portion of the necessary operations (e.g., as a server array, a set of blade servers, or a multiprocessor system). One processor 10 is illustrated in fig. 8.

The processor 10 may be a central processor, a network processor, or a combination thereof. The processor 10 may further include a hardware chip, among others. The hardware chip may be an application specific integrated circuit, a programmable logic device, or a combination thereof. The programmable logic device may be a complex programmable logic device, a field programmable gate array, a general-purpose array logic, or any combination thereof.

Wherein the memory 20 stores instructions executable by the at least one processor 10 to cause the at least one processor 10 to perform a method for implementing the embodiments described above.

The memory 20 may include a storage program area that may store an operating system, at least one application program required for functions, and a storage data area; the storage data area may store data created from the use of the computer device of the presentation of a sort of applet landing page, and the like. In addition, the memory 20 may include high-speed random access memory, and may also include non-transitory memory, such as at least one magnetic disk storage device, flash memory device, or other non-transitory solid-state storage device. In some alternative embodiments, memory 20 may optionally include memory located remotely from processor 10, which may be connected to the computer device via a network. Examples of such networks include, but are not limited to, the internet, intranets, local area networks, mobile communication networks, and combinations thereof.

Memory 20 may include volatile memory, such as random access memory; the memory may also include non-volatile memory, such as flash memory, hard disk, or solid state disk; the memory 20 may also comprise a combination of the above types of memories.

The computer device further comprises input means 30 and output means 40. The processor 10, memory 20, input device 30, and output device 40 may be connected by a bus or other means, for example in fig. 8.

The input device 30 may receive input numeric or character information and generate key signal inputs related to user settings and function control of the computer apparatus, such as a touch screen, a keypad, a mouse, a trackpad, a touchpad, a pointer stick, one or more mouse buttons, a trackball, a joystick, and the like. The output means 40 may include a display device, auxiliary lighting means (e.g., LEDs), tactile feedback means (e.g., vibration motors), and the like. Such display devices include, but are not limited to, liquid crystal displays, light emitting diodes, displays and plasma displays. In some alternative implementations, the display device may be a touch screen.

The embodiments of the present invention also provide a computer readable storage medium, and the method according to the embodiments of the present invention described above may be implemented in hardware, firmware, or as a computer code which may be recorded on a storage medium, or as original stored in a remote storage medium or a non-transitory machine readable storage medium downloaded through a network and to be stored in a local storage medium, so that the method described herein may be stored on such software process on a storage medium using a general purpose computer, a special purpose processor, or programmable or special purpose hardware. The storage medium can be a magnetic disk, an optical disk, a read-only memory, a random access memory, a flash memory, a hard disk, a solid state disk or the like; further, the storage medium may also comprise a combination of memories of the kind described above. It will be appreciated that a computer, processor, microprocessor controller or programmable hardware includes a storage element that can store or receive software or computer code that, when accessed and executed by the computer, processor or hardware, implements the methods illustrated by the above embodiments.

Although embodiments of the present invention have been described in connection with the accompanying drawings, various modifications and variations may be made by those skilled in the art without departing from the spirit and scope of the invention, and such modifications and variations fall within the scope of the invention as defined by the appended claims.

Claims

1. A data bit width conversion method, wherein the method is applied to a data bit width conversion system, and a ring buffer register, a read pointer and a write pointer are configured in the data bit width conversion system, and the method comprises:

controlling the write pointer to address in the annular cache register according to the first indication state to acquire first address information; controlling the read pointer to address in the annular cache register according to the second indication state to acquire second address information;

determining a data bit width conversion state according to the first indication state, the second indication state, the first address information and the second address information, wherein the data bit width conversion state is used for controlling input data to be input in a data input channel according to a first preset byte number, or feeding back a front end back pressure signal to control input data latch; and/or the data bit width conversion state is used for controlling output data to be output in a data output channel according to a second preset byte quantity, or feeding back a back end back pressure signal to control the output data latch;

And executing an operation corresponding to the data bit width conversion state on the input data and/or the output data.

2. The method of claim 1, wherein determining a data bit width transition state based on the first indication state, the second indication state, the first address information, and the second address information comprises:

3. The method according to claim 2, wherein obtaining the first indication state of the first indication signal and the second indication state of the second indication signal comprises:

acquiring the current state of a pre-configured data input effective indication signal, outputting the current state of the effective indication signal, and preparing the current state of the signal by the pre-configured output;

identifying the difference range of the address pointer difference value;

determining the first indication state according to the current state of the data input effective indication signal and the difference range of the difference value of the data input effective indication signal and the address pointer;

And determining the second indication state according to the current state of the output preparation signal and the current state of the data output valid indication signal.

4. A method according to claim 2 or 3, wherein the data bit width transition state comprises: a first transition state, a second transition state, a third transition state, and a fourth transition state;

the determining a data bit width conversion state according to the first indication state, the second indication state and the address pointer difference value comprises the following steps:

when the first indication state and the second indication state are determined to be invalid at the same time and the address pointer difference value is a preset value, determining that the data bit width conversion state is the first conversion state;

or when the first indication state and the second indication state are determined to be valid at the same time, and the address pointer difference value is any value in the intersection of a first difference value range and a second difference value range, determining that the data bit width conversion state is the second conversion state;

or when the first indication state is determined to be valid, the second indication state is determined to be invalid, and the address pointer difference value is any value in the first difference value range, determining that the data bit width conversion state is the third conversion state;

Or when the first indication state is determined to be invalid, the second indication state is determined to be valid, and the address pointer difference value is any value in the first difference value range, determining that the data bit width conversion state is the fourth conversion state.

5. The method according to claim 4, wherein said performing an operation corresponding to said data bit width transition state on said input data and/or said output data, in particular comprises:

or when the data bit width conversion state is the second conversion state, controlling the input data to be input according to a first preset byte number in the data input channel, and controlling the output data to be output according to a second preset byte number in the data output channel;

or when the data bit width conversion state is the third conversion state, controlling the input data to be input in the data input channel according to a first preset byte number, and feeding back the back end back pressure signal to control the output data to be latched;

Or when the data bit width conversion state is the fourth conversion state, feeding back the front end back pressure signal to control the input data to be latched and control the output data to be output according to a second preset byte number in the data output channel.

6. A method according to any one of claims 1-3, characterized in that the method further comprises:

when the data input channels comprise a plurality of data input channels, selecting a target data input channel from the plurality of data input channels in an arbitration mode to transmit the input data; and/or when the data output channels comprise a plurality of data output channels, selecting a target data output channel from the plurality of data output channels in an arbitration mode to transmit the output data.

7. The method of claim 6, wherein when the data input channels include a plurality of data input channels, selecting a target data input channel from the plurality of data input channels to transmit the input data using an arbitration scheme, comprises:

acquiring a preconfigured priority of each data input channel;

selecting a data input channel with highest priority from the data input channels as the target data input channel, and transmitting the input data by using the target data input channel;

And/or when the data output channel comprises a plurality of data output channels, selecting a target data output channel from the plurality of data output channels to transmit the output data in an arbitration mode, wherein the method comprises the following steps of:

acquiring a preconfigured priority of each data output channel;

and selecting the data output channel with the highest priority in the data output channels as the target data output channel, and transmitting the output data by using the target data output channel.

8. A method according to any one of claims 1-3, wherein when the data input channels comprise a plurality of data input channels, selecting a target data input channel from the plurality of data input channels for transmission of the input data using an arbitration scheme comprises:

polling each data input channel, and selecting any currently unoccupied data input channel as the target data input channel for transmitting the input data;

and polling each data output channel, and selecting any currently unoccupied data output channel as the target data output channel for transmitting the output data.

9. A method according to any one of claims 1 to 3, wherein the input data is pre-stored in an input cache queue for subsequent writing of data from the input cache queue to the ring cache register;

and/or storing the data read from the ring buffer into an output buffer queue for subsequent reading of the data from the output buffer queue.

10. The method of claim 9, wherein when the data input channel comprises a plurality of data input channels, the method further comprises:

dividing the input data into a plurality of input data fragments with the same number as the data input channel, and configuring identification information for each input data fragment;

and respectively distributing each input data segment to different data input channels for transmission, and combining a plurality of input data segments in the buffer queue according to the identification information of each input data segment so as to acquire the input data.

11. The method of claim 9, wherein when the data output channel comprises a plurality of data channels, the method further comprises:

dividing the output data into a plurality of output data fragments with the same number as the data output channel, and configuring identification information for each output data fragment;

And respectively distributing each output data segment to different data output channels for transmission, and combining a plurality of output data segments in the buffer queue according to the identification information of each data segment to acquire the output data.

12. A method according to claim 3, wherein the first indication state comprises both an active and an inactive state;

when the current state of the data input effective indication signal is an effective state and the difference range of the address pointer difference value is a first difference range, determining that the first indication state is effective;

or,

and when the current state of the data input valid indication signal is an invalid state and/or when the difference range of the address pointer difference value is not in the first difference range, determining that the first indication state is invalid.

13. A method according to claim 3, wherein the second indication state comprises two types of valid state and invalid state, and the current state of the data output valid indication signal comprises two types of valid and invalid state;

when the difference range of the address pointer difference value is a second difference range, the current state of the data output valid indication signal is a valid state; or when the difference range of the address pointer difference value does not belong to the second difference range, the current state of the data output valid indication signal is an invalid state;

When the state of the output preparation signal is a valid state and the current state of the data output valid indication signal is a valid state, determining that the second indication state is valid;

or,

and when the state of the output preparation signal is an invalid state and/or when the current state of the data output valid indication signal is an invalid state, determining that the second indication state is invalid.

14. A method according to any of claims 1-3, wherein the maximum data bit width of the ring buffer register is a preset integer multiple of the maximum of the first preset number of bytes and the second preset number of bytes.

15. A method according to any of claims 1-3, characterized by controlling the write pointer to jump address in the ring buffer register by the first preset number of bytes when the first indication state is valid;

16. A method according to any of claims 1-3, characterized by controlling the read pointer to jump address in the ring buffer register by the second preset number of bytes when the second indication state is valid;

17. A method according to any of claims 1-3, wherein when performing an operation corresponding to the data bit width transition state on the input data and/or the output data, the method further comprises:

and carrying out asynchronous transmission on the input data and the output data.

18. A data bit width conversion apparatus, the apparatus comprising:

the addressing module is used for controlling the write pointer to address in the annular cache register according to the first indication state to acquire first address information; controlling a read pointer to address in the annular cache register according to the second indication state to acquire second address information;

the processing module is used for determining a data bit width conversion state according to the first indication state, the second indication state, the first address information and the second address information, wherein the data bit width conversion state is used for controlling input data to be input in a data input channel according to a first preset byte number or feeding back a front end back pressure signal to control input data latch; and/or the data bit width conversion state is used for controlling output data to be output in a data output channel according to a second preset byte quantity, or feeding back a back end back pressure signal to control the output data latch;

19. A computer device, comprising:

a memory and a processor communicatively coupled to each other, the memory having stored therein computer instructions, the processor executing the computer instructions to perform the data bit width conversion method of any of claims 1 to 17.

20. A computer-readable storage medium having stored thereon computer instructions for causing a computer to perform the data bit width conversion method of any one of claims 1 to 17.