JPH10320351A - Buffer system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To efficiently perform data transfer by storing transfer data from an upper bus in a common bus through a common buffer controlling part and also making a buffer arbitrating part set transfer data from the common buffer to each sending buffer when the sending buffers have an empty area. SOLUTION: Sending buffers 32 to 52 are connected to lower buses 3 to 5, have capacity that is the same with an entry of a common buffer 21, receive transfer data that is sent to the lower buses by one entry each from the buffer 21 and store it. Bus processing parts 33 to 53 perform data sending control over the buses 3 to 5 of storage data of the buffers 32 to 52, also monitor designating buffers 31 to 51 and detect whether transfer data exists in the buffer 21 or not when the buffers 32 to 52 become empty states. When it exists, it shows an entry number and issues a data request to a buffer arbitrating part 23 and when it receives a set completion notification from the part 23, it sends storage data of the buffers 32 to 52 to the lower buses 3 to 5.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

The present invention relates to a buffer system, and more particularly to a buffer system for transferring data from an upper bus to a lower bus.

[0002]

2. Description of the Related Art When one upper bus is connected to a plurality of lower buses and data is exchanged between the upper bus and the lower bus, a difference in performance and a function between the two buses is absorbed and smooth operation is performed. A bus adapter is used to perform the transfer. A bus adapter generally employs a buffer for temporarily storing data and the like in order to absorb a difference in bus performance.
For this buffer, a flip-flop or a memory is used. The data and the like flowing through this buffer must be sent to the same lower bus in the order sent from the upper bus, but it is not necessary to guarantee the order between different lower buses. General.

A method of configuring a buffer when such a hierarchized bus structure is adopted is disclosed in Japanese Patent Application Laid-Open No. 57-6043.
The method described in Japanese Patent Publication No. 5 is basic.
That is, as shown in FIG. 2, data transfer from the system bus 6 having a large data capacity as an upper bus to the local bus 7 as a lower bus having a small data capacity is performed by a data buffer provided inside the bus adapter 1a. This is performed using 8 and 9 alternately. Data buffers 8 and 9
Each of the buffer units 8A and 8B can store one unit of data (transfer data of one bus clock) on the system bus 6 and correspond to one unit of data on the local bus 7.
And 9A and 9B.

The data stored in the data buffers 8 and 9 from the system bus 6 is transferred to buffer units 8A and 8
When the data is transmitted to the local bus 7 in the order of B, 9A, and 9B, and the data of the buffer unit 8B is transmitted and the data buffer 8 becomes empty, the next data is fetched from the system bus 6. Similarly, the buffer unit 9B
When the next data is transmitted, the next data is taken into the data buffer 9 so that the data can be continuously transmitted to the local bus 7 using the two data buffers alternately. However, fetching of data from the system bus 6 takes two
Since the number of data buffers is one, which is not efficient, the number of data buffers is usually increased so that data can be continuously taken from the system bus 6.

When considering a bus adapter that supports a plurality of lower buses using such a conventional buffer, a method of preparing the buffer and its control mechanism for each lower bus as described above, There is a method in which only one set of buffers shared by the bus is prepared and the control mechanism is configured to be compatible with a plurality of lower buses.

[0006]

However, in the above-described method of preparing a buffer for each of the lower buses, a buffer capable of absorbing the difference in performance and function between the two buses is provided for each of the lower buses. Given that commands and data from the higher-level device are generated randomly on the bus, and the lower-level bus to which it goes is also random, it has the disadvantage of having more hardware than necessary. is there.

On the other hand, when a buffer is shared by all lower buses, the buffer is used to transmit data to a lower bus among a plurality of lower buses due to a difference in operation state between the lower buses. If there is a state in which the lower bus is being used for some reason, there is a problem that data transmission to another subsequent lower bus is delayed until the buffer becomes empty. In other words, there is a drawback in that the behavior of one lower bus (bus busy or the like) affects the data transfer to the other lower bus, causing interference between buses.

An object of the present invention is to provide a buffer system capable of suppressing interference between buses due to the operation state of a lower bus when transferring data from one upper bus to a plurality of lower buses. It is in.

[0009]

According to a first aspect of the present invention, there is provided a buffer system used for transferring data from an upper bus to a plurality of lower buses by a bus adapter connected between buses having different performances. And a common buffer having a plurality of entries connected to the upper bus and storing transfer data to each lower bus, and identification information of an entry in the common buffer provided for each lower bus and storing transfer data. A first-in first-out instruction buffer, a transmission buffer connected to each lower bus for storing transfer data to be transmitted to the lower bus, and a common buffer for managing the common buffer and storing transfer data from the higher bus in the common buffer. A common destination for identifying a transfer destination and transmitting identification information of an entry storing transfer data in the corresponding instruction buffer; A buffer control unit, which is provided for each of the lower buses, controls transmission of data stored in the transmission buffer to the lower bus, monitors the instruction buffer, and indicates contents of the instruction buffer when there is free space in the transmission buffer. A bus processing unit for performing a data set request from the common buffer to the transmission buffer in accordance with, and arbitrating a data set request from each of the bus processing units to set corresponding data from the common buffer to the transmission buffer. A buffer arbitration unit for notifying the common buffer control unit of the completion of the setting, wherein the number of entries in the common buffer is set to be equal to or greater than the maximum number of entries in the instruction buffer.

The buffer system according to claim 2 is the buffer system according to claim 1, wherein each of the transmission buffers has the same storage capacity as one entry of the common buffer, and each of the bus processing units corresponds to the corresponding transmission buffer. Each time the transmission of the stored data to the lower bus is completed, the next data set request is made to the bus arbitration unit.

According to a third aspect of the present invention, in the buffer system according to the first aspect, the transmission buffer includes two entries each having the same storage capacity as one entry of the common buffer. The next data set request is made to the bus arbitration unit every time the transmission of the storage data of one entry of the corresponding transmission buffer to the lower bus is completed.

According to a fourth aspect of the present invention, in the buffer system according to the first, second or third aspect, the number of entries in each of the instruction buffers is set to be equal to the number of entries in the common buffer. It is characterized by.

According to a fifth aspect of the present invention, in the buffer system according to the second or third aspect, the number of entries in each of the instruction buffers is larger than the number of entries in each of the corresponding transmission buffers, and The number is set to be larger than the number of entries in each of the instruction buffers.

According to a sixth aspect of the present invention, in the buffer system according to the fifth aspect, the number of entries in the common buffer is a sum of the number of entries in two designated buffers having the largest number of entries among the designated buffers. It is characterized by being set large.

[0015]

Next, embodiments of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing the configuration of one embodiment of the present invention.

As shown in FIG. 1, the buffer system of this embodiment uses an upper bus 2 and a plurality of lower buses 3 to 3 having different performances.
5 is a buffer system used for data transfer from the upper bus 2 to the lower buses 3 to 5 in the bus adapter 1 connected to the bus adapter 5. The bus adapter 1 controls mutual data transfer between the upper bus 2 and the lower buses 3 to 5, and generally also controls data transfer from the lower bus to the upper bus. Shows only a portion related to data transfer from the upper bus to the lower bus.

In this buffer system, a common buffer 21 having a plurality of entries connected to the upper bus 2 and storing transfer data to the lower buses 3 to 5, and an entry provided for each lower bus and taking in the transfer data of the common buffer 21 are provided. Instruction buffers 31 to 51 in FIFO format for storing numbers, transmission buffers 32 to 52 for one entry for storing transmission data to lower buses 3 to 5, and transmission of data stored in transmission buffers 32 to 52 are controlled. Instruction buffers 31-5
1 is monitored, and from the common buffer 21 to the sending buffers 32 to 5
Bus processing units 33 to 53 for making a data set request to
And a common buffer control unit 2 that manages the common buffer 21 and controls fetching of transfer data from the upper bus 2 and transmission of the stored entry number to the instruction buffers 31 to 51.
2, and arbitrates for data transfer requests from the bus processing units 33 to 53, and sends data from the common buffer 21 to the transmission buffers 32 to 52.
And a buffer arbitration unit 23 for setting data to the buffer.

The common buffer 21 has a plurality of entries each having a capacity capable of storing one unit such as an instruction and data of the upper bus 2 as one entry. Common buffer control unit 22
Manages the use status of which of the plurality of entries in the common buffer 21 are being used and which are not used, controls the data storage to determine which entry receives the transfer data from the upper bus 2, and controls the lower bus. The instruction buffers 31 to 5 identify where in 3 to 5 the command or data should be sent.
The entry number is sent to the corresponding instruction buffer in 1 as identification information of the entry storing the transfer data. Upon receiving a data set request from the bus processing units 33 to 53, the buffer arbitration unit 23 performs arbitration between the bus processing units 33 to 53, and sends the selected buffer among the transmission buffers 32 to 52 to the common buffer 21. The storage data of the entry is set, and a data set completion notification is sent to the corresponding bus processing unit and common buffer control unit 22.

The instruction buffers 31 to 51 provided corresponding to the lower buses 3 to 5 have the same number of entries as the number of entries of the common buffer 21 in a FIFO structure.
When data is transmitted to the corresponding lower bus and stored in the common buffer 21, identification information (entry number) indicating which entry of the common buffer 21 stores data is stored in the instruction buffers 31 to 51. Is stored. The capacity of one entry of the instruction buffers 31 to 51 is slightly smaller than the capacity of one entry of the common buffer 21.
The sending buffers 32 to 52 are connected to the lower buses 3 to 5, respectively, have the same capacity as one entry of the common buffer 21, and receive and store transfer data to be sent to the lower bus one entry at a time from the common buffer 21. . The bus processing units 33 to 53 control the data transmission of the data stored in the transmission buffers 32 to 52 to the lower buses 3 to 5, and monitor the instruction buffers 31 to 51 when the transmission buffers 32 to 52 become empty, and perform common control. It detects whether or not transfer data exists in the buffer 21, and if so, issues a data set request to the buffer arbitration unit 23 by indicating the entry number, and sends a data set completion notification from the buffer arbitration unit 23. When received, the data stored in the transmission buffers 32-52 is transmitted to the lower buses 3-5.

Hereinafter, the operation of the buffer system of the present embodiment configured as described above will be described with reference to FIG.

An upper device such as a processor is connected to the upper bus 2, and transfer data including an instruction issued from the upper device and data accompanying the command flows on the upper bus 2. The common buffer control unit 22 constantly monitors the instruction of the transfer data flowing to the upper bus 2, and the instruction flowing to the upper bus 2 is an instruction to be transferred to any of the lower buses 3 to 5. In this case, the transfer data including the instruction is stored in a free entry of the common buffer 21. If there is no empty entry in the common buffer 21, the host device is notified to that effect.

The common buffer control unit 22 identifies which of the lower buses 3 to 5 the received instruction targets,
If the transfer data is to be sent to the lower bus 3,
An entry buffer 31 for designating an entry number for notifying in which entry of the common buffer 21 the transfer data is stored
Send to and store.

In the bus processing unit 33, when no data is stored in the transmission buffer 32 and the transmission buffer 32 is empty, the instruction buffer 31
When the entry number is stored in the instruction buffer 31 from the common buffer control unit 22, the first stored entry number is sent to the buffer arbitration unit 23.
A request is made to transfer the data stored in the entry in the common buffer 21 to the transmission buffer 32 and set it.

The buffer arbitration unit 23 monitors requests from the respective bus processing units 33 to 53, and arbitrates when there are a plurality of requests (arbitration is performed by a priority control method, a round robin method, or the like). Perform), and determine the processing order. When the request from the bus processing unit 33 is processed as a result of the arbitration, the output bus selection circuit of the common buffer 21 is switched to the transmission buffer 32, and the storage data stored in the entry of the designated entry number is changed. Select, transfer to the sending buffer 32 and set. When predetermined data is stored in the transmission buffer 32, a data set completion notification is transmitted to the bus processing unit 33, and at the same time, an entry number is notified to the common buffer control unit 22 and the corresponding entry of the common buffer 21 is Notifies that the vacant state has been reached, and starts the next arbitration.

The common buffer control unit 22 having received the notification of the entry number from the buffer arbitration unit 23
The corresponding entry 1 is invalidated so that the next transfer data flowing on the upper bus 2 can be accepted by the empty entry.

On the other hand, upon receiving the data set completion notification from the buffer arbitration unit 23, the bus processing unit 33 cancels the data set request signal to the buffer arbitration unit 23, and transfers the transfer data stored in the transmission buffer 32 to the lower bus 3. When the transmission is completed and the transmission buffer 32 becomes empty, the instruction buffer 31 is checked, and if there is an unprocessed entry number, the above-mentioned processing is repeated. Becomes

Next, a case where two data transfers to the lower bus 3 occur consecutively, and then one data transfer to the lower bus 4 occurs will be described.

These transfer data are sequentially stored in the three entries of the common buffer 21 in the same procedure as described above, and the transfer data is stored in the common buffer 21 in response to a data transfer request from the host device. The instruction buffer 31 stores the entry numbers of the two entries stored first and the instruction buffer 41 stores the entry numbers of the entries stored last.

Here, the bus processing unit 33 detects the first information from the instruction buffer 31 and makes a data set request to the buffer arbitration unit 23. The bus processing unit 43 also makes a similar request to the buffer arbitration unit 23. At this time, the buffer arbitration unit 23 performs the processing of the bus processing unit 33 first,
Next, it is assumed that the processing of the bus processing unit 43 is performed. The buffer arbitration unit 23 transfers and sets the storage data of the corresponding entry to the transmission buffers 32 and 42, and the common buffer control unit 22 releases the two corresponding entries in response to the data set completion notification to make the entry empty. At this time, since the second transfer data to the lower bus 3 has not been processed, the entry is not empty. During this period, if there is a subsequent data transfer from the upper bus 2, the data is sequentially stored in the empty entry including the released entry in the common buffer 21. When the bus processing unit 33 completes sending the first transfer data from the sending buffer 32,
Since the instruction buffer 31 has information on the subsequent second data transfer, the same operation as described above is repeated to perform processing for this.

At this time, if the data transmission process of the bus processing unit 33 to the lower bus 3 is stalled for some reason and enters a waiting state, the transmission buffer 32 and the common buffer 2
Although one entry of 1 cannot be used, data transfer to the lower buses 4 and 5 can be processed without delay using other entries of the common buffer 21 if there is no abnormality in the bus processing units 43 and 53. Even if transfer data to the lower bus 3 is further generated, the transfer efficiency is reduced but data transfer to another lower bus is possible unless all the entries of the common buffer 21 are used.
That is, data transfer from the upper bus to the lower bus can be performed almost without being affected by other lower buses.

In the above-described embodiment, the number of entries in the instruction buffer is equal to the number of entries in the common buffer. Therefore, all the entries in the common buffer can be used for data transfer to one lower bus, and efficient data transfer can be performed. On the other hand, all the entries in the common buffer are transferred by the transfer data to the waiting lower bus. Used, and data transfer to other lower buses may be hindered.
To avoid this, set the number of entries in the instruction buffer to be smaller than the number of entries in the common buffer, and when there are no more empty entries in the instruction buffer, the common buffer control unit will not accept data transfer to the lower bus. May be notified to the host device. The number of entries in the instruction buffer is set to a number that enables efficient data transfer in a normal state in consideration of how much transfer data is continuously received from the upper bus.

The sending buffer has the same capacity as one entry of the common buffer, and receives one entry at a time from the common buffer when the storage data has been sent to the lower bus. This facilitates data transfer from the common buffer to the sending buffer and minimizes the buffer capacity depending on the number of lower buses. However, there is a possibility that data transmission to the lower bus will not be continued due to waiting for data set to the transmission buffer. In particular, when the number of lower buses increases, the probability of occurrence of this state also increases. In order to avoid this problem, the buffer capacity depending on the number of lower buses increases, but the transmission buffer has a two-entry configuration, and the bus processing unit has completed data transmission of one entry by using each entry alternately. At this time, the next transfer data set request may be made. Although the capacity of the transmission buffer is not limited to a multiple of the capacity of one entry of the common buffer, the data set from the common buffer to the transmission buffer and the management of the common buffer become complicated. desirable.

Although the description of the above-described embodiment has not been made particularly clear for easy understanding, it is assumed that the performance of each lower bus is the same, and the instruction buffer, transmission buffer, bus The processing units were performed as if they had the same performance. However, the technical idea of the present invention is not limited to the case where the performance of each lower bus is the same, and can be applied even if the configuration of the instruction buffer, the transmission buffer, and the bus processing unit differs for each lower bus. For example, when the number of entries in the instruction buffer differs for each lower bus, if the number of entries in the common buffer is set to be larger than the sum of the numbers of entries in the two instruction buffers having the maximum number of entries in the instruction buffer, Even if the process is stalled and becomes a waiting state, data transfer to another lower bus can be executed without lowering the efficiency.

[0035]

As described above, according to the buffer system of the present invention, a bus adapter connected between one upper bus and a plurality of lower buses uses a buffer used when transferring data from the upper bus to the lower bus. , A two-stage configuration of a common buffer of a plurality of entries and a transmission buffer provided for each lower bus, an instruction buffer of a plurality of entries and a bus processing unit are provided for each lower bus, and transfer data from the upper bus is shared by a common buffer control unit. While storing in a buffer,
The buffer arbitration unit sets the transfer data from the common buffer to each transmission buffer when the transmission buffer becomes empty. As a result, efficient data transfer can be performed with a small buffer capacity while suppressing interference between buses.

[Brief description of the drawings]

FIG. 1 is a block diagram showing a configuration of an embodiment of the present invention.

FIG. 2 is a block diagram showing a basic buffer configuration in a hierarchical bus structure.

[Explanation of symbols]

 1, 1a Bus adapter 2 Upper bus 3, 4, 5 Lower bus 6 System bus 7 Local bus 8, 9 Data buffer 8A, 8B, 9A, 9B Buffer unit 21 Common buffer 22 Common buffer control unit 23 Buffer arbitration unit 31, 41 , 51 instruction buffer 32, 42, 52 transmission buffer 33, 43, 53 bus processing unit

Claims (6)

[Claims] 1. A buffer system used for transferring data from an upper bus to a plurality of lower buses by a bus adapter connected between buses having different performances, wherein each of the lower buses is connected to the upper bus. A buffer having a plurality of entries for storing data to be transferred to the lower-level bus; a first-in first-out instruction buffer provided for each of the lower-level buses for storing identification information of an entry in the common buffer storing the transfer data; A transmission buffer connected to the transmission buffer for storing transfer data to be transmitted to the lower bus, and a common buffer for managing the common buffer and storing the transfer data from the higher bus in the common buffer, and simultaneously identifying a transfer destination to the corresponding instruction buffer. A common buffer control unit for transmitting identification information of an entry storing transfer data; And controlling the transmission of the data stored in the transmission buffer to the lower bus and monitoring the instruction buffer, and setting a data set from the common buffer to the transmission buffer in accordance with the instruction content of the instruction buffer when the transmission buffer has a free space. A bus processing unit that makes a request, arbitrates a data set request from each of the bus processing units, sets corresponding data from the common buffer to the transmission buffer, and notifies the common buffer control unit of the completion of setting. A buffer arbitration unit, wherein the number of entries in the common buffer is set to be equal to or greater than the maximum number of entries in the instruction buffer. 2. Each of the transmission buffers has the same storage capacity as one entry of the common buffer, and each of the bus processing units transmits the data stored in the corresponding transmission buffer to the lower bus every time transmission of the data to the lower bus is completed. 2. The buffer system according to claim 1, wherein a next data set request is made to the arbitration unit. 3. The transmission buffer includes two entries each having the same storage capacity as one entry of the common buffer, and each of the bus processing units stores storage data of one entry of the transmission buffer corresponding to the lower bus. 2. The buffer method according to claim 1, wherein a next data set request is made to the bus arbitration unit every time transmission to the bus is completed. 4. The buffer system according to claim 1, wherein the number of entries in each of said instruction buffers is set to be equal to the number of entries in said common buffer. 5. The method according to claim 1, wherein the number of entries in each of said instruction buffers is set to be larger than the number of entries in each of said transmission buffers, and the number of entries in said common buffer is set to be larger than the number of entries in each of said instruction buffers. The buffer system according to claim 2 or 3, wherein 6. The method according to claim 5, wherein the number of entries in the common buffer is set to be larger than the sum of the numbers of entries in two instruction buffers having the maximum number of entries among the instruction buffers. Buffer method.