JP3990569B2 - Data memory control device - Google Patents

Description

[0001]
BACKGROUND OF THE INVENTION
The present invention relates to a data memory control device, and more particularly to a data memory control device in which a data memory is shared by a plurality of blocks by arbitration control of a data memory control unit.
[0002]
[Prior art]
In recent system LSIs, especially LSIs that implement media processing that handles image data and the like, the memory occupation ratio tends to be very high with respect to the total area. Therefore, when the area is reduced for cost reduction, it can be said that the memory capacity reduction is very effective and is an important effort. As one of memory capacity reduction techniques, there is memory sharing. In access arbitration control when a data memory is shared by a plurality of blocks, priority is given to each access block, and arbitration control is executed according to the priority. As a result, an access to a block having a high priority is preferentially executed, and the process can be performed more smoothly.
[0003]
[Problems to be solved by the invention]
In the conventional data memory control device, the priority order when executing access to the data memory for each block of a plurality of blocks is defined, and the access from each block is arbitrated according to the priority order. Therefore, when adding a block for executing access to the data memory, it becomes necessary to change the access arbitration mechanism. At the same time, when there are many blocks for executing access to the data memory, the access arbitration mechanism is complicated. There is a problem of becoming.
[0004]
In addition, when processing a block composed of a plurality of tasks, it is necessary to define processing priority for each task, and there is a problem that software becomes complicated.
The present invention has been made in view of the above problems, and an object of the present invention is to provide a data memory control device capable of improving access efficiency and setting priorities for each task. .
[0019]
[Means for Solving the Problems]
  To solve the problems mentioned above, this bookClaims of the invention1The data memory control device described in the above item arbitrates and controls access requests from the plurality of blocks in the data memory control device that controls access requests from the plurality of blocks in order to share the data memory among the plurality of blocks. A data memory control unit; a first address bus connecting the data memory and the data memory control unit; a first data bus connecting the data memory and the data memory control unit; A first access request signal line connecting the data memory control unit; a plurality of second address buses connecting the plurality of blocks and the data memory control unit; and the plurality of blocks and the data memory control. A plurality of second data buses that connect the plurality of blocks, and the plurality of blocks and the data memory control unit A plurality of second access request signal lines, and a plurality of access permission signal lines connecting the plurality of blocks and the data memory control unit, wherein the data memory control unit includes the plurality of blocks and the plurality of access permission signal lines. The access request is received by the second access request signal line, and the arbitration control of the plurality of access requests is performed using the address information from the plurality of second address buses. Data is transferred between the block and the data memory, the data memory control unit includes a read register that holds data read by the first block sharing the data memory, and the first block includes the first block A continuous access detector for detecting that the data memory is being read from the same address more than once in succession; Further comprising, detecting two or more consecutive read operations from the same address of said data memory by said first block in the continuous access detection unitBeforeThe data read from the data memory by the first block is stored in the read register,When the second block sharing the data memory issues an access request while the continuous access detection unit is continuously detecting continuous read operations from the same address,Data stored in the read register is transmitted to the first block, and access to the data memory of the second block is permitted.
[0020]
  ThisPriorities that could only be defined in units of accessed blocks as in the past can be defined using address information, so the number of blocks can be easily expanded without changing the access arbitration mechanism in the data memory controller In addition, the arbitration control of access from a plurality of blocks can be simplified, and the data transfer efficiency can be improved.
  Also,During continuous reading from the same address from a certain block, access can be made without waiting for contention when another access request comes, so that the processing performance of the entire system can be improved.
[0021]
  Further, the claims of the present invention2A data memory control device according to claim1In the data memory control device according to claim 1, the data memory control unit detects that the address from which the second block issues a write request and the address from which the first block is reading are the same address. An address detection unit, wherein the address detection unit detects that the read address of the first block and the write address of the second block are the same address, and the address to the same address by the second block is detected. After the data is written, reading from the same address by the first block is performed, and at the same time, the read data is written to the read register to update the read register.
[0022]
As a result, during continuous reading from the same address, it is possible to access without waiting for contention when another access request comes, so that the processing performance of the entire system can be improved and the same address can be improved. When the data is updated by writing to, the result can be reflected to continuous reading by reading again.
[0023]
  Further, the claims of the present invention3A data memory control device according to claim1In the data memory control device according to claim 2, when the address detection unit detects that the read address of the first block and the write address of the second block are the same address, the second block causes the Simultaneously with writing data to the same address, the write data is written to the read register to update the read register.
[0024]
As a result, during continuous reading from the same address, it is possible to access without waiting for contention when another access request comes, so that the processing performance of the entire system can be improved and the same address can be improved. When data is updated by writing to, the result can be reflected to continuous reading without executing reading again.
[0025]
  Further, the claims of the present invention4The data memory control device described in the above item arbitrates and controls access requests from the plurality of blocks in the data memory control device that controls access requests from the plurality of blocks in order to share the data memory among the plurality of blocks. A data memory control unit; a first address bus connecting the data memory and the data memory control unit; a first data bus connecting the data memory and the data memory control unit; A first access request signal line connecting the data memory control unit; a plurality of second address buses connecting the plurality of blocks and the data memory control unit; and the plurality of blocks and the data memory control. A plurality of second data buses that connect the plurality of blocks, and the plurality of blocks and the data memory control unit A plurality of second access request signal lines, and a plurality of access permission signal lines connecting the plurality of blocks and the data memory control unit, wherein the data memory control unit includes the plurality of blocks and the plurality of access permission signal lines. The access request is received by the second access request signal line, and the arbitration control of the plurality of access requests is performed using the address information from the plurality of second address buses. The data memory controller transfers data between a block and the data memory, and the data memory control unit includes a temporary storage memory that holds data for n (n ≧ 2) words and a first block that shares the data memory A continuous access detecting unit for detecting that the data memory is continuously read from the data memory at least twice. An address detector for detecting that an address from which a second block sharing the memory issues a write request and an address read from the first block are the same address; Is continuously notified of periodic address access of m (m ≦ n) words, and m word data read by the periodic address access is stored in the temporary storage memory. The data in the temporary storage memory is transmitted to the block to permit access to the data memory in the second block, and the write address of the second block and the reading of the first block are read by the address detection unit When it is detected that the address is the same address, the temporary storage memo is written simultaneously with the writing by the second block. Data is written in the memory and the temporary storage memory is updated.
[0026]
  ThisPriorities that could only be defined in units of accessed blocks as in the past can be defined using address information, so the number of blocks can be easily expanded without changing the access arbitration mechanism in the data memory controller In addition, the arbitration control of access from a plurality of blocks can be simplified, and the data transfer efficiency can be improved.
  Also,In the case of access to an area where periodic access is performed, such as coefficient reference, other access can be permitted, so that the processing efficiency of the entire system can be improved.
[0027]
  Further, the claims of the present invention5The data memory control device described in the above item arbitrates and controls access requests from the plurality of blocks in the data memory control device that controls access requests from the plurality of blocks in order to share the data memory among the plurality of blocks. A data memory control unit; a first address bus connecting the data memory and the data memory control unit; a first data bus connecting the data memory and the data memory control unit; A first access request signal line connecting the data memory control unit; a plurality of second address buses connecting the plurality of blocks and the data memory control unit; and the plurality of blocks and the data memory control. A plurality of second data buses that connect the plurality of blocks, and the plurality of blocks and the data memory control unit A plurality of second access request signal lines, and a plurality of access permission signal lines connecting the plurality of blocks and the data memory control unit, wherein the data memory control unit includes the plurality of blocks and the plurality of access permission signal lines. The access request is received by the second access request signal line, and the arbitration control of the plurality of access requests is performed using the address information from the plurality of second address buses. Data is transferred between the block and the data memory, and the data memory control device is provided with a plurality of direct buses for directly transferring data between the plurality of blocks, and for the plurality of blocks. A direct transfer control unit for controlling direct transfer of data, wherein the single block among the plurality of blocks If the address making the write access request to the data memory and the address making the read access request from all or some of the plurality of blocks are the same address, all access requests are permitted. The write data output from the block that has received write access permission is written to the data memory, and at the same time, the direct transfer control unit passes to the block that has received read access permission through the direct bus. The delivery of the write data ofAt the same time, when writing to the data memory from the block that has received the write access permission is unnecessary, the writing to the data memory is not performed, and the block to the block that has received the read access permission via the direct bus is not executed. Only the write data is transferred, and during that time, access requests from other blocks are permitted.Is.
[0028]
  As a result, priorities that can only be defined in units of blocks to be accessed as in the prior art can be defined using address information, so the number of blocks can be reduced without changing the access arbitration mechanism in the data memory control unit. In addition to being easily expandable, the arbitration control of access from a plurality of blocks can be simplified, and the data transfer efficiency can be improved.
  Further, in the case of transferring data between a plurality of blocks via the data memory, write access and read access can be executed at the same time, so that the processing efficiency of the entire system can be improved.
  In addition, when transferring between multiple blocks via the data memory and there is no need to write the transfer data to the data memory, write access and read access can be executed simultaneously, and other accesses can be performed between them. Since it can be permitted, the processing performance of the entire system can be improved.
[0037]
DETAILED DESCRIPTION OF THE INVENTION
Embodiment 1 FIG.
FIG. 1 is a basic configuration diagram of a data memory control device according to the first embodiment.
In the figure, as a basic configuration, a data memory control unit 100 that arbitrates and controls access requests from a plurality of blocks, which will be described later, a data memory 101, a processor core 102 that is a plurality of blocks, dedicated hardware (hereinafter referred to as a dedicated HW). 103) and a peripheral 104.
[0038]
Further, the connection between the data memory 101 and the data memory control unit 100 is the first access that outputs the address bus 101a serving as the first address bus, the data bus 101a serving as the first data bus, and the access request signal 101c. The connection between the plurality of blocks 102, 103, and 104 and the data memory control unit is performed by request signal lines. The address buses 102b, 103b, and 104b, which are a plurality of second address buses, and the plurality of second data Data buses 102a, 103a, and 104a serving as buses, a plurality of second access request signal lines that output access request signals 102c, 103c, and 104c, and a plurality of access permissions that output access permission signals 102d, 103d, and 104d Connected with signal lines.
[0039]
Next, the operation of the data memory control device according to the first embodiment of the present invention is performed with reference to FIG.
2 shows the data memory address space of the data memory area A 105a, the data memory area B 105b, and the data memory area C 105c according to the contents of the data to be stored in the data memory 101 in FIG. It is divided into three areas.
[0040]
In the data memory control device according to the first embodiment, the processor core 102, the dedicated HW 103, the address space representing the areas of the data memory area A 105a, the data memory area B 105b, and the data memory area C 105c in the data memory 101 are provided. Each block that accesses the data memory 101, such as the peripheral 104, gives priority when the block accesses the data memory 101. There is no limitation on the order of priority. That is, the priority order may be fixed in advance, or the priority order may be changed in accordance with the status of processing executed in each block.
[0041]
For example, in the figure, it is assumed that priorities when the blocks execute access are given in the order of the data memory area A 105a, the data memory area B 105b, and the data memory area C 105c. A case where the processor core 102, the dedicated HW 103, and the peripheral 104 execute access to the data memory 101 when such priority is given will be described.
[0042]
When the processor core 102, the dedicated HW 103, and the peripheral 104 execute access to the data memory 101, each of the blocks described above accesses the data memory 101 to the data memory control unit 100 with access request signals 102c, 103c, and 104c. Notify that access is to be executed. The data memory control unit 100 determines which block is to access the data memory 101 from the access request signals 102c, 103c, and 104c from each block. If there is no access conflict, the data memory control unit 100 notifies the block that access from the block is permitted by the access permission signals 102d, 103d, and 104d. Thereafter, the block that has received the access permission signal starts to access the data memory 101.
[0043]
When there is an access conflict, access to the data memory 101 at the same time from the address buses 102b, 103b, and 104b indicating which area in the data memory 101 each block performs access to. A data memory control unit based on the address bus value of the block making the request and the priority given to the data memory area A105a, data memory area B105b, and data memory area C105c in the data memory 101 100 notifies the block which is going to execute the access to the area with high priority by the access permission signal that the access is permitted. After that, the block that receives the access permission signal and executes the access to the high priority area in the data memory 101 starts to access the data memory 101.
[0044]
As described above, the data memory control device according to the first embodiment defines the priority order for each data area in the data memory 101, so that the value of the address space to which each block attempts to perform access. Access arbitration can be performed only, and the priority order is not defined for each of the blocks that execute access. Therefore, even if the number of blocks that execute access to the data memory 101 is changed, the data memory Arbitration control in the data memory control unit 100 can be simplified without changing the control unit 100, and the number of blocks for executing access to the data memory 101 can be easily expanded.
[0045]
Also, by increasing the priority for the data memory area that stores data used by tasks with higher priority, it is possible to define the priority according to the content of the data used by each task rather than the function of each task. Since this is possible, the definition of priority can be flexibly realized.
[0046]
Embodiment 2. FIG.
The data memory control device according to the second embodiment of the present invention is the one in which means for realizing high-speed processing in each block while suppressing an increase in hardware cost is applied to the first embodiment.
[0047]
FIG. 3 is a block diagram showing the configuration of the data memory control apparatus according to the second embodiment.
The basic configuration of FIG. 3 is the basic configuration of FIG. 1 described above, and the data memory 101 allocates an address space of the data memory according to the content of the data to be stored, as in FIG. The area is divided into three areas A105a, data memory area B105b, and data memory area C105c.
[0048]
In addition, an access to the data memory 101 such as the processor core 102, the dedicated HW 103, and the peripheral 104 is performed on the address space representing the areas of the data memory area A 105a, the data memory area B 105b, and the data memory area C 105c in the data memory 101. The priority order in the case where each block to perform the access to the data memory 101 is given.
[0049]
As in FIG. 2, it is assumed that priorities in the case where each block executes access are given in the order of the data memory area A 105a, the data memory area B 105b, and the data memory area C 105c.
[0050]
In addition to the above-described configuration, the data memory control device according to the second embodiment is configured so that the memory elements constituting the data memory region A105a having a high priority are assigned to the data memory region B105b having a lower priority than the data memory region A105a, And a high-performance memory element that can be accessed at a higher speed than the data memory area C105c.
[0051]
In general, there are processing that requires real-time processing and processing that must be executed with priority over other processing. Data necessary for such processing is stored in a high priority area in the data memory 101 so that access to the data memory 101 is preferentially executed. It becomes possible to perform processing.
[0052]
Furthermore, high-speed access is possible by using high-performance storage elements capable of high-speed access to the storage elements constituting the data memory 101, data can be supplied to each block at high speed, and processing speed can be increased. It becomes.
[0053]
In general, high-performance storage elements that can be accessed at high speed consume a large amount of power and have high hardware costs. Therefore, high-performance storage elements that can be accessed at high speed are as small as possible in order to suppress an increase in hardware costs. It is preferable to use it only.
[0054]
As described above, the data memory control device according to the second embodiment allows the storage elements included in the data memory area A105a having a higher priority in the data memory 101 to be transferred to the data having a lower priority than the data memory area A105a. Processing using data in the high-priority data memory area A105a while suppressing an increase in hardware cost by configuring the memory area B105b and the data memory area C105c with high-performance storage elements that can be accessed at high speed. Can be speeded up.
[0055]
In addition, since processing with high priority can be speeded up, data region B 105b and data region C 105c with low priority for which execution is awaited by processing for executing access to data memory region A 105a with high priority. The waiting time for processing using the data in the system becomes shorter, and the processing efficiency of the entire system can be improved.
[0056]
Embodiment 3 FIG.
The data memory control device according to the third embodiment of the present invention is obtained by adding means for realizing a higher processing speed in each block while suppressing an increase in hardware cost. is there.
[0057]
FIG. 4 is a block diagram showing the configuration of the data memory control apparatus according to the third embodiment.
The basic configuration of FIG. 4 is the basic configuration of FIG. 1 described above. In FIG. 4, the data memory 101 has an address space of the data memory corresponding to the contents of data to be stored, as in FIGS. By allocating, the data memory area A105a, the data memory area B105b, and the data memory area C105c are divided into three areas.
[0058]
In addition, access to the data memory 101 such as the processor core 102, the dedicated HW 103, and the peripheral 104 is performed on the address space representing the areas of the data memory area A 105a, the data memory area B 105b, and the data memory area C 105c in the data memory 101. The priority order in the case where each block to perform the access to the data memory 101 is given.
[0059]
Similar to FIGS. 2 and 3, it is assumed that priorities in the case where each block executes access are given in the order of the data memory area A 105a, the data memory area B 105b, and the data memory area C 105c.
[0060]
Further, as in FIG. 3, the memory elements constituting the data memory area A105a having a higher priority are higher in speed than the data memory area B105b and the data memory area C105c having a lower priority than the data memory area A105a. It consists of a performance memory element.
[0061]
In addition to the above-described configuration, the data memory control device according to the third embodiment further includes a high-performance storage element as a storage element that constitutes an area with a high access frequency in the high-priority data memory area A105a. The data memory areas A2 and 106b are constituted by ultra-high performance storage elements that can be accessed at a higher speed than the data memory areas A1 and 106a and the data memory areas A3 and 106c. For this purpose, in the high-priority data memory area A105a, a high-performance storage element that can be accessed at a higher speed than the low-priority data memory area B105b and the data memory area C105c, It also includes making up.
[0062]
In general, the fact that there is an area with high access frequency in each data memory area in the data memory 101 means that it takes time to process the data stored in that area. Therefore, by configuring the memory elements that make up the frequently accessed area with high-performance memory elements that can be accessed at a higher speed than other areas, the data supply capacity for each block is improved and the processing speed is increased. It becomes possible.
[0063]
In general, high-performance storage elements that can be accessed at high speed consume a large amount of power and have high hardware costs. Therefore, high-performance storage elements that can be accessed at high speed are as small as possible in order to suppress an increase in hardware costs. It is preferable to use it only.
[0064]
As described above, the data memory control device according to the third embodiment of the present invention further increases the speed of access to the memory elements constituting the frequently accessed area in the data memory area A 105a with high priority in the data memory 101. By configuring with a possible ultra-high performance memory element, it is possible to further increase the speed of the process of using data in the data memory area A 105a having a high priority while suppressing an increase in hardware cost.
[0065]
In addition, since processing with high priority can be speeded up, data region B 105b and data region C 105c with low priority for which execution is awaited by processing for executing access to data memory region A 105a with high priority. The waiting time for processing using the data in the system can be further shortened, and the processing efficiency of the entire system can be improved.
[0066]
Embodiment 4 FIG.
In the fourth embodiment, a means for realizing a higher processing speed in each block while suppressing an increase in hardware cost is added to the third embodiment.
[0067]
FIG. 5 is a block diagram showing the configuration of the data memory control apparatus according to the fourth embodiment.
The basic configuration of FIG. 5 is the basic configuration of FIG. 1 described above, and the data memory 101 of the data memory control device stores data according to the contents of data to be stored, as in FIGS. 2, 3, and 4. By allocating the memory address space, it is divided into three areas: a data memory area A 105a, a data memory area B 105b, and a data memory area C 105c.
[0068]
Further, access to the data memory 101 such as the processor core 102, the dedicated HW 103, and the peripheral 104 is performed on the address space representing the areas of the data memory area A 105a, the data memory area B 105b, and the data memory area C 105c in the data memory 101. The priority order in the case where each block to perform the access to the data memory 101 is given.
[0069]
As in FIGS. 2, 3, and 4, the priority order when each block executes access is given in the order of the data memory area A 105a, the data memory area B 105b, and the data memory area C 105c. To do.
[0070]
In addition to the above-described configuration, the data memory control device according to the fourth embodiment further includes a memory element that constitutes an area with high access frequency in each of the data memory A 105a, the data memory area B 105b, and the data memory area C 105c. Is configured with a high-performance storage element that can be accessed at a higher speed than the data memory area other than the frequently accessed area.
[0071]
In general, the fact that there is an area with high access frequency in each data memory area in the data memory 101 means that it takes time to process the data stored in that area. Therefore, by configuring the memory elements that make up the frequently accessed area with high-performance memory elements that can be accessed at a higher speed than other areas, the data supply capacity for each block is improved and the processing speed is increased. It becomes possible.
[0072]
In general, high-performance storage elements that can be accessed at high speed consume a large amount of power and have high hardware costs. Therefore, high-performance storage elements that can be accessed at high speed are as small as possible in order to suppress an increase in hardware costs. It is preferable to use it only.
[0073]
As described above, the data memory control device according to the fourth embodiment of the present invention includes a storage element that constitutes a frequently accessed area in each data memory area to which priority is given in the data memory 101. By using high-performance storage elements that can be accessed at high speed, it is possible to increase the processing speed of each block while suppressing an increase in hardware cost.
[0074]
Further, since the processing speed of each block can be increased, the waiting time of each block for which execution is awaited during an access conflict can be shortened, and the processing efficiency of the entire system can be improved.
[0075]
Embodiment 5 FIG.
The data memory control device according to the fifth embodiment of the present invention uses the same address in order to improve the processing performance of the entire system when read access contention from a plurality of blocks occurs in the same area of the data memory. Read access contention is detected, and read access from a plurality of blocks is permitted.
[0076]
FIG. 6 is a block diagram showing the configuration of the data memory control apparatus according to the fifth embodiment of the present invention.
The difference from FIG. 1 is that the same address read / read access conflict monitoring block 600a for monitoring the read access conflict for the same address of the data memory 101 is provided, and the dedicated HW 103 of FIG. It is a point.
[0077]
Next, the operation of the data memory control device according to the fifth embodiment of the present invention will be described.
The same address read / read access conflict monitoring block 600a receives the address buses 102b, 601b, and 104b and the access request signals 102c, 601c, and 104c. For example, let us consider a case where the processor core 102 is constantly in a polling state by continuously reading the flag 602 stored in the data memory 101, and a case where the processor core 601 tries to execute polling of the flag 602.
[0078]
At this time, the same address read / read access conflict monitoring block 600a monitors the coincidence between the address buses 102b and 601b and the coincidence between the access request signals 102c and 601c, and outputs the access permission signal 601d when they coincide. The data memory control device 100 is controlled to output the data on the data bus 101a to the data bus 601a. As a result, since the data on the data bus 101a is output to the data bus 102a and the data bus 601a and the access permission signals 102d and 601d are output, both the processor cores 102 and 601 can shift to the polling state, thereby eliminating read access contention. .
[0079]
As described above, the data memory control device according to the fifth embodiment of the present invention uses the address bus and the access request signal input to the same address at the time of read access contention from a plurality of blocks to the same area of the data memory. Since the read access conflict is detected and the read access conflict is permitted, the processing performance of the entire system can be improved.
[0080]
Embodiment 6 FIG.
The data memory control device according to the sixth embodiment of the present invention detects contention between a block that performs read access and a block that performs write access to the same address as the block, and performs processing performance of the entire system. In order to improve this, write access is permitted.
[0081]
FIG. 7 is a block diagram showing the configuration of the data memory control apparatus according to the sixth embodiment of the present invention.
The difference from FIG. 6 is that instead of the same address read / read access conflict monitoring block 600a, the same address read / write access conflict monitoring block 600b for monitoring the conflict between read access and write access to the same address of the data memory 101 is provided. It is a point that has.
[0082]
Next, the operation of the data memory control device according to the sixth embodiment of the present invention will be described.
The same address read / write access conflict monitoring block 600b receives the address buses 102b, 601b, and 104b and the access request signals 102c, 601c, and 104c. For example, a case will be described in which the processor core 102 always reads a certain flag 602 in the data memory 101 and is in a polling state, and the peripheral 104 rewrites the flag 602 and attempts to cancel polling of the processor core 102.
[0083]
At this time, the same address read / write access conflict monitoring block 600b monitors the match between the address buses 102b and 104b and the match between the access request signals 102c and 104c, and if they match, the access permission signal 104d and the access request signal The data memory control unit 100 is controlled to output the data on the data bus 104a to the data bus 101a and the data bus 102a simultaneously with the output of 101c. As a result, it is possible to cancel the polling state of the processor core 102 by outputting the same data to the data bus 102a while performing write access of the data bus 101a to the data memory 101, thereby eliminating access contention.
[0084]
As described above, the data memory control device according to the sixth embodiment of the present invention performs write access contention for read access using the address bus and the access request signal respectively inputted when accessing the same area of the data memory. Since it detects and permits write access contention, the processing performance of the entire system can be improved.
[0085]
Embodiment 7 FIG.
In the data memory control device according to the seventh embodiment of the present invention, when data is continuously read from a block to the same address, the data read from the block is stored in the data memory in order to improve the processing performance of the entire system. While the data is held in the control unit and there is a read request from the block, the held data is transmitted to the block so that access from other blocks can be permitted.
[0086]
FIG. 8 is a block diagram showing the configuration of the data memory control apparatus according to the seventh embodiment of the present invention.
The difference from FIG. 1 is that the access request signal of any of the blocks 102, 103, and 104 continues in the data memory control unit 100 twice or more, and the access destination is the same address. A continuous access detection unit 800 for detecting the data, and any one of the blocks 102, 103, and 104 includes a read register 801 that can hold data read from the data memory 101.
[0087]
For example, when an access request has not been received from the blocks 102 and 104 to the data memory 101 and an access request has been consecutively received from the block 103 to the data memory 101 twice or more, the previous access is first performed by the continuous access detection unit. It is detected whether the address and the address read this time are the same address. When the same address is detected, the read data is stored in the read register 801. After the storage, the data in the read register 801 is stored in the block 103 while a read request for data on the same address is received. Continue to send to.
[0088]
In this way, while the data in the read register 801 continues to be transmitted to the block 103, access to the data memory 101 from another block is permitted, so when an access request comes from the block 102 or the block 104, The access request is allowed.
[0089]
In the data memory control device according to the seventh embodiment of the present invention as described above, the continuous access detection unit 800 detects continuous reading to the same address of a certain block, and stores the read data in the read register 801. However, since the data of the block is read by transmitting the data from the read register 801 storing the data to the block, an access request is received from another block during continuous reading from the block to the same address. Can be accessed without waiting for contention, and the processing performance of the entire system can be improved.
[0090]
Embodiment 8 FIG.
The data memory control device according to the eighth embodiment of the present invention transmits data held in the read register from the read register in the data memory control unit to the block that continuously reads the same address. In addition, when there is a write request from another block to the same address as the block requesting the read, the block requesting the read after writing the data in the data memory in order to update the read register At the same time, the data memory is read again, and at the same time, the read data is written to the read register.
[0091]
FIG. 9 is a block diagram showing the configuration of the data memory control apparatus according to the eighth embodiment of the present invention.
The difference from FIG. 8 is that, in the data memory control unit 100, when access to the data memory 101 competes from each block 102, 103, and 104, the address detection unit detects whether the addresses are the same. This is the point where 802 is added.
[0092]
For example, since the block 103 continuously reads the same address to the data memory 101, when a data write request is received from the block 102 or 104 to the data memory 101 while the data in the read register 801 is being read, the address The conflict detection unit 802 detects whether the address is the same as the address read by the block 103.
[0093]
When it is detected that the block requesting writing and the block 103 have the same address, access to the block 102 or 104 is permitted and the data in the data memory 101 is updated. Thereafter, the block 103 reads the data in the data memory 101 again and simultaneously updates the data in the read register 801. After the update, the data in the read register 801 is continuously transmitted to the block 103.
[0094]
Further, when the read register 801 needs to be updated, the data in the read register 801 can be updated at the same time when the block 102 or the block 104 accesses the data memory 101. Accordingly, the block 103 does not need to access the data memory 101 again in order to update the read register 801.
[0095]
The data memory control device according to the eighth embodiment as described above can access without competing and waiting when another access request is received during continuous reading from the same address. Can be improved.
[0096]
Also, even if the data in the data memory 101 is updated by writing to the same address as the block that is being continuously read from another block, the block 103 that is reading the data reads out again to the data memory 101, and the read Since the data in the register 801 is also updated, the updated data can be reflected in the read register 801, and the update result can be reflected in the block that is being continuously read.
[0097]
In addition, by updating the data in the read register 801 at the same time as writing to the same address as that of the block 103 being read from another block, the block 103 can update the data memory 101 to update the read register 801. There is no need to re-access, and the overhead at the time of updating the read register 801 can be eliminated to shorten the access time.
[0098]
Embodiment 9 FIG.
In the data memory control device according to the ninth embodiment of the present invention, in the case where a block reads data continuously from the data memory periodically, the block is a data memory in order to improve the processing efficiency of the entire system. The data read from is temporarily stored in the data memory control unit, and the stored data is transmitted to the block so that access from other blocks can be permitted.
[0099]
FIG. 10 is a block diagram showing the configuration of the data memory control apparatus according to the ninth embodiment of the present invention.
The difference from FIG. 1 is that the access request signal of any of the blocks 102, 103, and 104 continues in the data memory control unit 100 twice or more and the access destination is the same address. A continuous access detection unit 800, an address conflict detection unit 802 that detects whether the addresses of the blocks 102, 103, and 104 conflict with each other in the data memory 101, and the data memory. And a temporary storage memory 803 that holds n (n ≧ 2) words of data read from 101 to any of the blocks 102, 103, and 104.
[0100]
For example, there is no access request from the blocks 102 and 104 to the data memory 101, and the data memory is notified that m (m ≦ n) words of data are continuously read from the data memory 101 periodically from the block 103. When the data is transferred to the control unit 100, the m-word data read from the data memory 101 is stored in the temporary storage memory 803. After the storage, the data in the temporary storage memory 803 is transmitted to the block 103 as long as the notification from the block 103 continues. to continue.
[0101]
While the data in the temporary storage memory 803 continues to be transmitted to the block 103, access to the data memory 101 from another block is permitted, so when an access request comes from the block 102 or the block 104, Access requests are allowed. Therefore, when an access request is received from another block during the notification from the block 103, it is possible to access without waiting for contention.
[0102]
However, when the access request from the block 102 or the block 104 is an access request to the address accessed by the block 103, the address conflict detection unit 802 detects the access request. When it is detected that the addresses are the same, access to the block 102 or the block 104 is permitted, and the data memory 101 is updated. The data can be updated simultaneously with the temporary storage 803 simultaneously with the data memory 101, and the temporary storage 803 can be updated without overhead due to access to the data memory.
[0103]
As described above, the data memory control device according to the ninth embodiment notifies the data memory control unit 100 when the cyclic data of m words is continuously read from the data memory 101, so that the data of m words Is transmitted from the temporary storage memory 803, it is possible to permit access to the data memory 101 of another block.
[0104]
Further, when the data memory 101 is updated by another block and the temporary storage memory 803 needs to be updated, the temporary storage memory 803 is also updated at the same time as the data memory 101, so that the data memory 101 is not accessed again and accessed. Time can be shortened.
[0105]
Embodiment 10 FIG.
The data memory control device according to the tenth embodiment of the present invention starts from a certain block in order to improve the processing efficiency of the entire system when transferring data at the same address between a plurality of blocks via the data memory. The write data is output to the data memory, and at the same time, the data is directly transferred to another block to perform write access and read access simultaneously.
[0106]
FIG. 11 is a block diagram showing the configuration of the data memory control apparatus according to the tenth embodiment of the present invention. The difference from FIG. 1 is that direct buses 102e, 103e, and 104e that directly transfer data between a plurality of blocks and a direct control unit 1201 that controls direct transfer of data are provided.
[0107]
Next, the operation of the data memory control device according to the tenth embodiment of the present invention will be described in the case where data is transferred from the peripheral 104 to the dedicated HW 103 via the direct bus 103e.
[0108]
First, the peripheral 104 issues a data write request to the data memory control unit 100 to the data memory control unit 100, and the direct transfer control unit 1201 transfers the data directly from the peripheral 104 to the dedicated HW 103 via the direct bus 103e. Data is output to the bus 101a. At this time, the peripheral 104 continues to output only the transfer data to the data memory control unit 100 and enters a write request acceptance waiting state. The dedicated HW 103 issues a data read request for the data memory 101 to the data memory control unit 100. At this time, the dedicated HW 103 enters a read request acceptance waiting state. If the address of the data memory 101 requested from both is the same address and the access request to the data memory is a type in which reading and writing are opposite, the data memory control unit 100 receives an access permission signal for the data memory 101 from both 103 c and 104 c are asserted, and write data output from the peripheral 104 is stored in the variable 1202 of the data memory 101. The peripheral 104 that has issued the write request receives the access permission signal 104d output from the data memory control unit 100, and transitions from the write acceptance waiting state to the write state. On the other hand, the dedicated HW 103 that has issued the read request receives the access permission signal 103 d output from the data memory control unit 100, transitions from the read acceptance wait state to the read state, and the direct transfer control unit 1201 performs the peripheral processing. Direct transfer from 104 to dedicated HW 103 is performed.
[0109]
However, direct transfer is performed only during a period in which valid data, that is, the peripheral 104 outputs data to the data memory 101. For example, valid / invalid can be determined by providing an identification signal in the direct buses 104e and 103e. When the invalid data, that is, the peripheral 104 has finished outputting data to the variable 1202 of the data memory 101, the dedicated HW 103 reads from the variable 1202 of the data memory 101.
[0110]
As described above, the data memory control device according to the tenth embodiment of the present invention receives write data from a block that requests write when the address of the block that requests read and the address of the block that requests write are the same. Since the write data is output to the data memory simultaneously with the direct transfer to the read block, the read access and the write access can be executed simultaneously, and the processing efficiency of the entire system can be improved.
[0111]
In the above example, when the data output from the peripheral 104 to the data memory 101 can be transferred to the dedicated HW 103 by direct transfer and the data stored in the data memory 101 is not used in the subsequent processing, the data memory 101 For example, the processor core 102 other than the peripheral 104 and the dedicated engine 103 can access the data memory 101 by performing control to suppress writing to the data memory 101.
[0112]
In addition, direct transfer connecting each block connects to a plurality of blocks, so that a plurality of blocks can simultaneously read out write data in reading.
[0113]
Further, the direct buses 102e, 103e, and 104e can be shared with the data buses 102a, 103a, and 104a, respectively, and even when the direct buses 102e, 103e, and 104e are not provided, the data buses 102a, 103a, and 104a are used. Direct transfer is possible.
[0114]
Embodiment 11 FIG.
The data memory control device according to the eleventh embodiment of the present invention includes a clock control unit that controls on / off of a clock for a plurality of blocks in order to reduce power consumption, and permits access permission from the data memory control unit. It controls the clock for the block in the waiting state.
[0115]
FIG. 12 is a block diagram showing the configuration of the data memory control apparatus according to Embodiment 11 of the present invention.
A difference from FIG. 1 is that a data memory control unit 100 includes a clock control unit 200 that controls clocks of a plurality of blocks, and the clock control unit 200 is connected to the block 102 by clock control signals 102f, 103f, and 104f. , 103, and 104.
[0116]
The blocks 102, 103, and 104 issue access requests to the data memory 101 using the access request signals 102c, 103c, and 104c. However, if there are access requests from a plurality of blocks, access contention occurs. The memory control unit 100 performs arbitration control, and only the blocks that are permitted to access read or write data in the data memory 101.
However, if there is a block other than the block for which access is permitted, the block enters a so-called waiting state until access permission is received from the data memory control unit 100.
[0117]
At this time, the clock control unit 200 outputs a control signal for stopping the clock to the block entering the waiting state. As a result, the block entering the waiting state stops the clock. Thereafter, the processing of the block that has received the access permission is completed, and the clock control unit 200 activates the clock of the block in the waiting state when the block in the waiting state receives the permission of access.
[0118]
By the operation of the clock control unit described above, the clock can be stopped only while the block is in a waiting state.
In this method, the clock of the block is stopped. If the target block has a clock control mechanism, the clock can be turned on / off using the clock control signal as a control signal. However, even when the target block does not have a clock control mechanism, the clock of the target block can be turned on / off by supplying the clock supplied to this block through a simple circuit such as a logical product with the clock control signal. realizable. When the clock control signal itself is supplied as a clock signal to the target block, the block clock can be turned on / off without adding a clock control mechanism.
[0119]
As described above, in the data memory control device according to the eleventh embodiment of the present invention, when access competition to the data memory by a plurality of blocks occurs, the access permission is suspended by the clock control unit, and the waiting state is entered. Power consumption can be reduced by stopping the clock for the block that is included.
[0120]
Embodiment 12 FIG.
The data memory control device according to the twelfth embodiment of the present invention includes a memory speed control unit that controls the operation speed of the data memory in order to reduce the power consumption of the block in which the access conflict has occurred, and operates the data memory at a high speed The frequency of the block waiting for transfer is reduced.
[0121]
FIG. 13 is a block diagram showing a configuration of a data memory control apparatus according to Embodiment 12 of the present invention.
The difference from FIG. 1 is that the data memory control unit 100 includes a memory speed control unit 300 that controls the operation speed of the data memory 101. The memory speed control unit 300 is connected to the data memory 101 by a memory speed control signal 101g. It is a connected point.
[0122]
The blocks 102, 103, and 104 issue access requests to the data memory 101 using the access request signals 102 d, 103 d, and 104 d, but when there are access requests from a plurality of blocks, access contention occurs, so data The memory control unit 100 needs to perform arbitration control.
[0123]
In the twelfth embodiment, for example, when an access request from two blocks is generated, the memory speed control unit 300 increases the operating speed of the data memory 101 through the memory speed control signal line 101g more than twice, The extracted block is processed without waiting, and the data memory is read and written. With this process, even when an access conflict from two blocks occurs, each block can access the data memory 101 simultaneously.
[0124]
Even when access requests from three or more blocks are generated, processing can be similarly performed by increasing the operation speed of the data memory in accordance with the number of competing accesses. In this way, by dynamically changing the operation speed of the data memory 101, the data memory control unit 100 performs contention control on access requests from a plurality of blocks. However, the number of contention access requests processed simultaneously is limited according to the maximum operation speed of the data memory 101.
[0125]
As described above, in the data memory control device according to the twelfth embodiment of the present invention, when there is an access request from a plurality of blocks, the memory speed control unit increases the operation speed of the data memory to increase the number of blocks. Can process the access request, and the frequency of the block waiting for transfer is reduced, so that the power consumption of the block can be reduced.
[0126]
Embodiment 13 FIG.
The data memory control device according to the thirteenth embodiment of the present invention is scalable by connecting a plurality of data memory control units to enable flexible response in a relatively short period of time to system requirements. It is an extended function.
[0127]
FIG. 14 is a block diagram showing a configuration of a data memory control apparatus according to Embodiment 13 of the present invention.
In the figure, details of access arbitration control to the data memory 401 from the processor core 402 and the dedicated HW 403 executed by the data memory control unit 400, and the processor core 502 and the dedicated HW 503 executed by the data memory control unit 500 are shown. The contents of access arbitration control to the data memory 501 are the same as those in the first to twelfth embodiments. The feature shown in the thirteenth embodiment is that the data memory control unit 400 and the data memory control unit 500 are connected by a data bus 404a, an address bus 404b, an access request signal 404c, and an access permission signal 404d. It is a point comprised by the data memory control part.
[0128]
With the above configuration, for example, the processor core 402 can issue an access request to the data memory 501. Specifically, when the processor core 402 issues a write access request to the data memory control unit 400 using the access request signal 402c, the data memory control unit 400 uses the access request signal 404c. A write access request is issued to 500. When receiving an access request from the access request signal 404c, the data memory control unit 500 confirms a conflict with an access request from another block, and executes write access to the data memory 501 if there is no conflict.
[0129]
As described above, the data memory control device according to the thirteenth embodiment connects other data memory control units to each other by a data bus, an address bus, an access request signal, and an access permission signal, thereby controlling other data memory controls. Since it is possible to request access to the data memory controlled by the control unit and to expand the function in a scalable manner, it is possible to respond flexibly to the system request in a relatively short time.
[0130]
In the thirteenth embodiment, the write access from the processor core 402 to the data memory 501 is taken as an example, but a read access request or access from another block can be executed in the same manner. Furthermore, in the thirteenth embodiment, the coupling of the two data memory control units has been described. However, expansion to n (n is a natural number of 2 or more) systems can be easily performed.
[0138]
【The invention's effect】
  BookClaims of the invention1According to the data memory control device described in the above, in the data memory control device that arbitrates and controls access requests from the plurality of blocks in order to share the data memory among the plurality of blocks, the access requests from the plurality of blocks are arbitrated. A data memory control unit to be controlled, a first address bus connecting the data memory and the data memory control unit, a first data bus connecting the data memory and the data memory control unit, and the data A first access request signal line connecting the memory and the data memory control unit; a plurality of second address buses connecting the plurality of blocks and the data memory control unit; and the plurality of blocks and the data A plurality of second data buses connecting the memory control unit, the plurality of blocks, and the data memory control unit; A plurality of second access request signal lines to be connected; and a plurality of access permission signal lines for connecting the plurality of blocks and the data memory control unit; One or a plurality of access requests are received by a plurality of second access request signal lines, arbitration control of the plurality of access requests is performed using address information from the plurality of second address buses, and one or more according to the permitted access request The data memory controller transfers the data between the block and the data memory, the data memory control unit includes a read register that holds data read by the first block sharing the data memory, and the first block Continuous access detection that detects that data is being read from the same address twice or more consecutively. Anda part, detecting two or more consecutive read operations from the same address of said data memory by said first block in the continuous access detection unitBeforeThe data read from the data memory by the first block is stored in the read register,When the second block sharing the data memory issues an access request while the continuous access detection unit is continuously detecting continuous read operations from the same address,Since the data stored in the read register is transmitted to the first block and access to the data memory of the second block is permitted, another access request comes during continuous reading from the same address. The system can be accessed without waiting for contention, and the processing performance of the entire system can be improved.
[0139]
  Further, the claims of the present invention2According to the data memory control device described in claim1In the data memory control device according to claim 1, the data memory control unit detects that the address from which the second block issues a write request and the address from which the first block is reading are the same address. An address detection unit, wherein the address detection unit detects that the read address of the first block and the write address of the second block are the same address, and the address to the same address by the second block is detected. After the data is written, the first block reads from the same address, and at the same time, the read data is written to the read register and the read register is updated. Can be accessed without waiting for contention It is possible to improve the processing performance, and when the data memory is updated by writing to the same address, it is possible to reflect the result to continuous reading by executing the reading again. .
[0140]
  Further, the claims of the present invention3According to the data memory control device described in claim1In the data memory control device according to claim 2, when the address detection unit detects that the read address of the first block and the write address of the second block are the same address, the second block causes the Simultaneously with writing data to the same address, the write data is written to the read register and the read register is updated. Therefore, during continuous reading from the same address, it waits in competition when another access request comes. It is possible to improve the processing performance by being able to access without having to access, and when the data memory is updated by writing to the same address, the result is reflected to continuous reading without executing the reading again. There is an effect that can.
[0141]
  Further, the claims of the present invention4According to the data memory control device described in the above, in the data memory control device that arbitrates and controls access requests from the plurality of blocks in order to share the data memory among the plurality of blocks, the access requests from the plurality of blocks are arbitrated. A data memory control unit to be controlled, a first address bus connecting the data memory and the data memory control unit, a first data bus connecting the data memory and the data memory control unit, and the data A first access request signal line connecting the memory and the data memory control unit; a plurality of second address buses connecting the plurality of blocks and the data memory control unit; and the plurality of blocks and the data A plurality of second data buses connecting the memory control unit, the plurality of blocks, and the data memory control unit; A plurality of second access request signal lines to be connected; and a plurality of access permission signal lines for connecting the plurality of blocks and the data memory control unit; One or a plurality of access requests are received by a plurality of second access request signal lines, arbitration control of the plurality of access requests is performed using address information from the plurality of second address buses, and one or more according to the permitted access request The data memory controller transfers the data between the block and the data memory, and the data memory control unit shares the data memory with a temporary storage memory that holds n (n ≧ 2) words of data. A continuous access detection unit for detecting that a block is continuously reading from the data memory at least twice to the same address; An address detector for detecting that an address from which a second block sharing the data memory issues a write request and an address from which the first block is reading are the same address; Upon receiving notification that the block continuously performs periodic address access of m (m ≦ n) words, data of m words read by the periodic address access is stored in the temporary storage memory, and the first The data of the temporary storage memory is transmitted to the block of the second block to permit access to the data memory of the second block, and the write address of the second block and the first block of the first block are permitted by the address detection unit. When it is detected that the read address is the same address, the temporary recording is performed simultaneously with the writing by the second block. Since data is written to the memory and the temporary memory is updated, other accesses can be permitted when accessing an area that performs periodic access such as coefficient reference, improving the processing efficiency of the entire system. There is an effect that can.
[0142]
  Further, the claims of the present invention5According to the data memory control device described in the above, in the data memory control device that arbitrates and controls access requests from the plurality of blocks in order to share the data memory among the plurality of blocks, the access requests from the plurality of blocks are arbitrated. A data memory control unit to be controlled, a first address bus connecting the data memory and the data memory control unit, a first data bus connecting the data memory and the data memory control unit, and the data A first access request signal line connecting the memory and the data memory control unit; a plurality of second address buses connecting the plurality of blocks and the data memory control unit; and the plurality of blocks and the data A plurality of second data buses connecting the memory control unit, the plurality of blocks, and the data memory control unit; A plurality of second access request signal lines to be connected; and a plurality of access permission signal lines for connecting the plurality of blocks and the data memory control unit; One or a plurality of access requests are received by a plurality of second access request signal lines, arbitration control of the plurality of access requests is performed using address information from the plurality of second address buses, and one or more according to the permitted access request The data memory controller transfers data between the blocks and the data memory, and the data memory control device provides a plurality of direct buses for directly transferring data between the plurality of blocks, and the plurality of blocks. A direct transfer control unit for controlling direct transfer of the data of the plurality of blocks. If the address making the write access request to the data memory from the memory block and the address making the read access request from all or some of the plurality of blocks are the same address, At the same time that the write data output from the block that received the write access permission is written to the data memory, the direct transfer control unit receives the read access permission via the direct bus. Control the passing of the write data to the blockAt the same time, when writing to the data memory from the block that has received the write access permission is unnecessary, the writing to the data memory is not performed, and the block to the block that has received the read access permission via the direct bus is not executed. Only the write data is transferred, and during that time, access requests from other blocks are permitted.SoPriorities that could only be defined in units of accessed blocks as in the past can be defined using address information, so the number of blocks can be easily expanded without changing the access arbitration mechanism in the data memory controller In addition, the arbitration control of access from a plurality of blocks can be simplified, and the data transfer efficiency can be improved.
  Also,In the case of transfer between a plurality of blocks via the data memory, write access and read access can be executed simultaneously, and the processing efficiency of the entire system can be improved.
  In addition, when transferring between multiple blocks via the data memory and there is no need to write the transfer data to the data memory, write access and read access can be executed simultaneously, and other accesses can be performed between them. Since the permission can be granted, the processing performance of the entire system can be improved.
[Brief description of the drawings]
FIG. 1 is a basic configuration diagram of a data memory control device of the present invention.
FIG. 2 is a block diagram showing a configuration of a data memory control device according to the first embodiment.
FIG. 3 is a block diagram illustrating a configuration of a data memory control device according to a second embodiment.
4 is a block diagram illustrating a configuration of a data memory control device according to a third embodiment. FIG.
FIG. 5 is a block diagram showing a configuration of a data memory control device according to a fourth embodiment.
FIG. 6 is a block diagram showing a configuration of a data memory control device according to a fifth embodiment.
FIG. 7 is a block diagram showing a configuration of a data memory control device according to a sixth embodiment.
FIG. 8 is a block diagram illustrating a configuration of a data memory control device according to a seventh embodiment.
FIG. 9 is a block diagram illustrating a configuration of a data memory control device according to an eighth embodiment.
FIG. 10 is a block diagram showing a configuration of a data memory control device according to a ninth embodiment.
FIG. 11 is a block diagram illustrating a configuration of a data memory control device according to a tenth embodiment.
12 is a block diagram showing a configuration of a data memory control device according to an eleventh embodiment. FIG.
13 is a block diagram showing a configuration of a data memory control apparatus according to Embodiment 12. FIG.
14 is a block diagram showing a configuration of a data memory control apparatus according to Embodiment 13. FIG.
[Explanation of symbols]
100 Data memory controller
101 Data memory
101a Data bus
101b Address bus
101c Access request signal
102 processor core
102a Data bus
102b Address bus
102c access request signal
102d access permission signal
103 Dedicated HW
103a Data bus
103b Address bus
103c Access request signal
103d access permission signal
104 peripheral
104a Data bus
104b Address bus
104c access request signal
104d access permission signal
105a Data memory area A
105b Data memory area B
105c Data memory area C
106a Data memory area A1
106b Data memory area A2
106c Data memory area A3
107a Data memory area B1
107b Data memory area B2
108a Data memory area C1
108b Data memory area C2
600a Read / read access conflict monitoring block for the same address
600b Contention monitoring block for read / write access to the same address
602 flag
800 Continuous access detector
801 Read register
802 Address conflict detection unit
803 Temporary memory
1201 Direct transfer control unit
1202 variables
102e Direct bus
103e Direct bus
104e direct bus
200 Clock control signal
102f Clock control signal
103f Clock control signal
104f Clock control signal
300 Memory speed control signal
101g Memory speed control signal
400 Data memory controller
401 Data memory
401a Data bus
401b Address bus
401c Access request signal
402 processor core
402a Data bus
402b Address bus
402c access request signal
402d Access permission signal
403 Dedicated HW
403a Data bus
403b Address bus
403c Access request signal
403d Access permission signal
404a Data bus
404b Address bus
404c Access request signal
404d access permission signal
500 Data memory controller
501 Data memory
501a Data bus
501b Address bus
501c Access request signal
502 processor core
502a data bus
502b Address bus
502c access request signal
502d access permission signal
503 Dedicated HW
503a Data bus
503b Address bus
503c access request signal
503d access permission signal

Claims (5)

In a data memory control device that arbitrates and controls access requests from the plurality of blocks in order to share the data memory among the plurality of blocks,
A data memory control unit that arbitrates and controls access requests from the plurality of blocks;
A first address bus connecting the data memory and the data memory control unit;
A first data bus connecting the data memory and the data memory control unit;
A first access request signal line connecting the data memory and the data memory control unit;
A plurality of second address buses connecting the plurality of blocks and the data memory control unit;
A plurality of second data buses connecting the plurality of blocks and the data memory control unit;
A plurality of second access request signal lines connecting the plurality of blocks and the data memory control unit;
A plurality of access permission signal lines connecting the plurality of blocks and the data memory control unit;
The data memory control unit receives access requests from the plurality of blocks through the plurality of second access request signal lines, and uses address information from the plurality of second address buses for arbitration control of the plurality of access requests. In accordance with the permitted access request, and passing data between one or more blocks and the data memory,
The data memory control unit includes a read register that holds data read by a first block sharing the data memory;
A continuous access detection unit for detecting that the first block is continuously reading from the same address twice or more to the data memory;
When the two or more consecutive read operations from the same address of said data memory by said first block detected by the continuous access detection unit, a data pre-Symbol first block is read out from the data memory When the second block sharing the data memory issues an access request while saving in the read register and subsequently detecting a continuous read operation from the same address in the continuous access detector, the first access Sending the data stored in the read register to the block and allowing access to the data memory of the second block;
A data memory control device. In the data memory control device according to claim 1,
The data memory control unit includes an address detection unit that detects that the address from which the second block issues a write request and the address from which the first block is reading are the same address,
The address detection unit detects that the read address of the first block and the write address of the second block are the same address, and after writing data to the same address by the second block, Reading from the same address by the first block, simultaneously writing the read data to the read register, and updating the read register;
A data memory control device. In the data memory control device according to claim 1,
When the address detection unit detects that the read address of the first block and the write address of the second block are the same address, simultaneously with the writing of data to the same address by the second block Write the write data to the read register and update the read register.
A data memory control device. In a data memory control device that arbitrates and controls access requests from the plurality of blocks in order to share the data memory among the plurality of blocks,
A data memory control unit that arbitrates and controls access requests from the plurality of blocks;
A first address bus connecting the data memory and the data memory control unit;
A first data bus connecting the data memory and the data memory control unit;
A first access request signal line connecting the data memory and the data memory control unit;
A plurality of second address buses connecting the plurality of blocks and the data memory control unit;
A plurality of second data buses connecting the plurality of blocks and the data memory control unit;
A plurality of second access request signal lines connecting the plurality of blocks and the data memory control unit;
A plurality of access permission signal lines connecting the plurality of blocks and the data memory control unit;
The data memory control unit receives access requests from the plurality of blocks through the plurality of second access request signal lines, and uses address information from the plurality of second address buses for arbitration control of the plurality of access requests. In accordance with the permitted access request, and passing data between one or more blocks and the data memory,
The data memory control unit includes a temporary storage memory that holds data for n (n ≧ 2) words;
A continuous access detection unit for detecting that the first block sharing the data memory is performing a read operation to the data memory at least twice continuously to the same address;
An address detection unit for detecting that an address from which a second block sharing the data memory issues a write request and an address from which the first block is reading are the same address;
Upon receiving notification that the first block continuously performs periodic address access of m (m ≦ n) words, data of m words read by the periodic address access is stored in the temporary storage memory. , Transmitting the data in the temporary storage memory to the first block to permit access to the data memory in the second block,
When the address detecting unit detects that the write address of the second block and the read address of the first block are the same address, data is stored in the temporary storage memory simultaneously with the writing by the second block. To update the temporary storage memory,
A data memory control device. In a data memory control device that arbitrates and controls access requests from the plurality of blocks in order to share the data memory among the plurality of blocks,
A data memory control unit that arbitrates and controls access requests from the plurality of blocks;
A first address bus connecting the data memory and the data memory control unit;
A first data bus connecting the data memory and the data memory control unit;
A first access request signal line connecting the data memory and the data memory control unit;
A plurality of second address buses connecting the plurality of blocks and the data memory control unit;
A plurality of second data buses connecting the plurality of blocks and the data memory control unit;
A plurality of second access request signal lines connecting the plurality of blocks and the data memory control unit;
A plurality of access permission signal lines connecting the plurality of blocks and the data memory control unit;
The data memory control unit receives access requests from the plurality of blocks through the plurality of second access request signal lines, and uses address information from the plurality of second address buses for arbitration control of the plurality of access requests. In accordance with the permitted access request, and passing data between one or more blocks and the data memory,
The data memory control device includes a plurality of direct buses for directly transferring data between the plurality of blocks;
A direct transfer control unit that controls direct transfer of data to the plurality of blocks,
The address making a write access request to the data memory from a single block of the plurality of blocks is the same as the address making a read access request from all or some of the plurality of blocks. In the case of an address, permission is given to all access requests, write data output from a block that has received write access permission is written to the data memory, and at the same time, the direct transfer control unit through the controls the transfer of the write data to the block that receives a read access permission,
When writing to the data memory from the block that has received the write access permission is unnecessary, the writing to the data memory is not executed, and the writing to the block that has received the read access permission via the direct bus is not performed. Executes only the data transfer, while permitting access requests from other blocks.
A data memory control device.

Images