JPH09269927A - Bus access method, bus and bus connection system - Google Patents

Abstract

PROBLEM TO BE SOLVED: To speed up bus access by starting a slave arbitration processing in an early stage in a bus system which is hierarchically constituted wit plural CPUs. SOLUTION: Plural bus masters requesting access simultaneously transmit target indication information and arbitration priority as arbitration codes on a host bus 105a. The transmission is executed with a start phase. One back arbitration code in a contention phase remains and a bus bridge device judges whether or not a comparator is necessary to be connected to a slave bus 105b. When it is necessary, a slave bus distribution arbitration circuit starts the arbitration processing of the slave bus. Since the arbitration processing can be executed after the decision phase of the host bus, speed becomes fast compared to a method for starting the arbitration processing after a master phase lie in a conventional method.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an information processing system in which a plurality of bus masters are connected to a plurality of buses, and obtains a right to use one bus at a high speed to speed up access across a plurality of buses. How to access the bus,
Bus, bus connection system.

[0002]

[Prior art]

Conventional Technology 1. FIG. 21 is a functional block diagram for explaining a bus bridge device in the related art, in which an upper address / data bus 213a to which a plurality of bus masters 210 are connected to a lower address / data to which a plurality of bus slaves 211 are connected. A bus bridge device 212 for bridging data to the bus 213b is shown. The bus master 210 makes an access request to the upper address data bus 213a, and is composed of, for example, a processor. The bus slave 211 is a memory that operates by receiving data / instruction from the lower address / data bus 211,
It consists of input / output devices. In this system, a plurality of bus masters 210 or bus slaves 211 are connected to one address data bus.
In order to access the data bus, it is necessary to acquire the usage right. The process of deciding who has this usage right is called arbitration process. Arbitration control signals 214a and b and arbitration buses 215a and b are used for this arbitration processing. The arbitration control signals 214a and b are signals for identifying each phase of the arbitration processing, and the arbitration buses 215a and 215a are used to transmit the access priority.

FIG. 22 is a timing chart for explaining the access method of the system shown in FIG. In FIG. 22, the same symbols as those in FIG. 21 represent the signals of the same parts. The arbitration process in the conventional technique will be described with reference to FIG. The arbitration process is composed of five phases: start, race, decision, wait, and master. The start phase is a phase in which each bus master 210 simultaneously requests the right to use the bus and outputs its own priority to the arbitration bus 215a. Next, in the competition phase, each bus master 2
10 detects a signal on the arbitration bus 215a, and another bus master 2 having a higher priority than its own priority
When there is 10, the output to the arbitration bus 215a is stopped.

In the decision phase, low priority requests are eliminated in the competition phase, and the address / data bus 21
The bus master 210 that uses 3a is determined. Next, in the standby phase, the address / data bus 21 waits until the address / data bus becomes available. Finally, in the master phase, the address / data bus 21
Access using 3a is started. The reason why the waiting phase is necessary is that the arbitration process is performed even when the address / data bus 213a is in use.

When the master phase is entered and an address is transmitted on the address data bus 213a, the bus bridge 212 receives this address and determines whether it is necessary to transfer the data on the upper bus to the lower bus. When it is determined that it is necessary, the bus bridge 212 serves as a bus master and performs an arbitration process to acquire the right to use the lower address / data bus 213b. This arbitration processing is performed according to the arbitration control signal 214b of the lower bus, and is performed in the same manner as the above-mentioned arbitration processing.

The upper address / data bus 213
After acquiring the right to use both the a and the lower address / data bus 213b, data transfer between both buses is performed.

Prior art 2. Further, conventionally, in a method of shortening the bus acquisition time in a system in which a plurality of units are connected to a plurality of buses, Japanese Patent Laid-Open No. 1-20536
No. 5 publication. In this Japanese Patent Laid-Open No. 1-205365, when there are a plurality of buses, bus request signal lines are provided between the bus arbiter and the bus master corresponding to these buses. When the bus master uses the bus, it outputs the use request signal to a plurality of buses at the same time.

Prior art 3. In addition, conventionally, in the bus control method when a module that supports split transfer and a module that does not support split transfer coexist,
There is JP-A-3-278156. This Japanese Patent Laid-Open No. 3-2
In the bus control method of Japanese Patent No. 78156, split transfer is performed for a module that supports split transfer and interlock transfer is performed for a module that does not support split transfer. When performing split transfer, the bus master that has output the request releases the bus and waits for a reply from the bus bridge. Then, when there is data transfer from the bus bridge, this data is accepted and one transaction ends.

Prior art 4. Japanese Patent Laid-Open No. 4-365150 discloses a bus master which has an access request buffer between two buses and accepts a plurality of access requests. This bus master is provided with one buffer for a plurality of bus slaves, temporarily stores the requests generated in its own bus master in the buffer, and outputs the requests to the bus slaves in the order of acceptance. Then, when a response to the request is received from the bus slave,
Responses are output in the order in which they were received. Therefore, the request processing can be efficiently performed regardless of the difference between the request generation frequencies of the main memory and the shared memory, which corresponds to the bus slave, and the "sequential order at the time of request transmission" in the data buffer circuit is maintained. It has the effect of eliminating the need for it.

[0010]

In the prior art 1 described above, the bus master transmits an address after the distributed arbitration cycle ends, and the bus bridge receives the address to start arbitration to the lower bus. However, there is a problem that the overhead increases and the performance decreases. It is an object of the present invention to provide a bus bridge device that can reduce the overhead from a bus master request to a lower bus request.

In the above-mentioned conventional technique 2, there is a problem in that even in the data transfer between the units connected to the same bus, the bus right of the other bus is additionally acquired, and the bus occupation rate becomes higher than necessary. Further, there is a problem that the bus request signal line also increases as the number of buses increases. An object of the present invention is to provide a bus bridge that can apparently eliminate the bus acquisition time and speed up access in a system that requires immediacy in data transfer. Another object of the present invention is to provide a bus bridge that can prevent the occupation ratio from increasing while the bus right is acquired more than necessary without performing data transfer.

In the above-mentioned conventional technique 3, when there is a bus that does not support the split access method in the system, the interlock access method is always selected, so that the bus occupation time of the bus master is extended and other master devices are in the meantime. However, there is a problem that the transfer throughput cannot be increased because the transfer of the data is delayed. Also, on the master side,
Since it is necessary to wait for a response from the bus bridge and receive the data, a function as a bus slave must be provided, and a circuit for that is required. An object of the present invention is to provide a bus bridge that suppresses bus occupancy time and improves transfer performance even when there is a mixture of bus protocols that support / does not support the split access method in the system. It is to provide an access method that can be used even for access to a master that does not exist.

In the above-mentioned conventional technique 4, the bus master controls only its own access request. Therefore, in a system in which the request generation frequency to the slaves varies, the processing concentrates on the slaves having a high request generation frequency and the processing time is long. There is a problem of becoming. An object of the present invention is to provide a bus bridge that improves the processing performance of the entire system by monitoring the load of slaves in the system and prioritizing access to the idle slaves.

[0014]

In a bus access method for transferring data between a first bus and a second bus according to the present invention, a plurality of access request devices connected to the first bus. In order to acquire the right to use the first bus, a plurality of first priority signals indicating the priorities of the plurality of access requesting devices and a plurality of pieces of target instruction information indicating the location of the device to be accessed. A first start step of accepting, a first competition step of selecting a first priority signal having a high priority from the plurality of first priority signals accepted in the first start step, The right to use the first bus is granted to the access request device corresponding to the first priority signal selected in the first competition step, and the target indication information corresponding to the selected first priority signal is given. A first determining step of outputting the selected first priority signal as a second priority signal for acquiring the right to use the second bus when the connection destination of the second bus is indicated. And a second starting step of receiving a third priority signal indicating the priority of the access requesting device connected to the second bus and the second priority signal,
A second competition step of selecting a priority signal having a higher priority from the plurality of priority signals received in the second start step, and the access corresponding to the priority signal selected in the second competition step. A second determining step for granting the requesting device the right to use the second bus. The access request device is also called a bus master,
For example, a processor. The access target is also called a bus slave and is, for example, a memory or an input / output device.

In the first determining step, the target designating information corresponding to the first priority signal selected in the first competing step is converted into information that can be recognized by the bus arbiter managing the second bus. It is what is output.

The target designation information is an address of the device to be accessed, and the first determining step corresponds to the selected first priority information on the address bus of the first bus. Outputting the address, and the second determining step outputs the address corresponding to the selected priority information onto the address bus of the second bus.
On the address bus of the first bus which is executed after the second determining step and which is accessed through the first bus based on an address on the address bus of the first bus. Second master step of accessing via the second bus based on the address of

The first bus comprises a first priority bus for transmitting the first priority signal and a first data bus for transferring data, and the second bus is the second bus.
Second priority bus for transmitting the first priority signal or the third priority signal and a second data bus for transferring data, wherein the first master step is within the first bus. Data bus and the first priority bus are used to transmit data, and the first master step is
Data is transmitted using the data bus in the second bus and the second priority bus.

In the bus access method of a bus bridge device for connecting a first bus and a second bus, an access request device connected to the first bus accesses an access target on the first bus. A first bus request step of selectively outputting an internal bus request signal transmitted when performing an access, or an external bus request signal transmitted when accessing an access target on the second bus; The first bus acquisition step for acquiring the right to use the first bus, which is executed after the bus request step of, and the right to use the second bus when the external bus request signal is output. A second bus request step of outputting a requesting bus request signal; and a second step of executing after the second bus request step is executed to acquire a right to use the second bus.
And the bus acquisition step of.

In the bus access method, the data is transferred between the first bus and the second bus via a bus bridge device connecting the first bus and the second bus. A first request executed by an access requesting device connected to the first bus, acquiring the right to use the first bus, and designating an access target connected to the second bus and outputting a processing request. Step, a retry request step executed after execution of the first request step, the bus bridge device accepts the processing request, and outputs a retry request to the access request device, and the access request device accepting the retry request Is executed after the execution of the first request step and a waiting step of abandoning the right to use the first bus and waiting for a predetermined time. A second requesting step of Tsu di device outputs the processing request to the access requested,
A first processing result transmitting step of transmitting a processing result corresponding to the processing request from the access target and storing the processing result in the bus bridge device, and executed after completion of the waiting step. A third request step of acquiring a usage right and outputting a transfer request for requesting the transfer of the processing result, and the processing result corresponding to the transfer request by the bus bridge device via the first bus. A second processing result transmitting step of transmitting to the access requesting device.

The retry request step calculates a retry time interval according to the access target, and the waiting step waits for the retry time interval.

In the bus according to the present invention, a data bus for transmitting data and prior to acquiring the right to use the data bus, priority information for determining the right to use the bus is transmitted from a plurality of access requesting devices. And an arbitration bus for transmitting data in parallel with the data bus after the acquisition of the usage right.

In the bus connection system according to the present invention, an internal bus request signal connected to the first bus and requesting access to the first bus, or an external requesting access to the second bus or another bus. A connection is provided between an access request device that selectively outputs a bus request signal, acquires the right to use the first bus, and transmits data to the first bus, and the first bus and the second bus. However, while accepting the internal bus request signal or the external bus request signal output by the access requesting device, and when accepting the external bus request signal, the external bus request signal is output to another bus arbiter, A bus arbiter for acquiring the right to use the second bus and transmitting the data received from the first bus to the second bus.

A plurality of the other bus arbiters are provided, and the access requesting device outputs a bus code for identifying the second bus or another bus when outputting the external bus request signal, and the bus arbiter is the bus arbiter. Based on the code, another bus arbiter that outputs the external bus request signal is selected from the plurality of other bus arbiters, and the external bus request signal is output to the selected other bus arbiter.

A second bus, to which a first bus to which a processing request is transmitted and a processing device of a request destination that processes the processing request are connected
Connected to this first bus, and a bus monitoring unit that monitors the second bus and records the history of request destination information of the processing request made using the second bus as access history information. A plurality of request buffer registers for accumulating the processing request transmitted through the first bus and request destination information of the processing request and the access history information are referred to, and the requests stored in these request buffer registers respectively. A transfer control unit that selects request destination information from which a lot of time has passed since the last access and outputs the instruction information of the request buffer register corresponding to the selected request destination information, and the instruction information. Select one request buffer register from the plurality of request buffer registers based on
A selector unit for outputting the processing request and the request destination information accumulated in the selected request buffer register to the second bus;
It is provided with. The processing request is, for example, a write command and write data, a read command, and other data for controlling the processing device. The request destination is, for example, an identifier of a processing device specified from an address that specifies the processing device of the request destination of the instruction. The processing device is a bus slave, and is, for example, a memory, an input / output device, or the like.

[0025]

BEST MODE FOR CARRYING OUT THE INVENTION

Embodiment 1. The first embodiment is an embodiment provided with a bus prefetch means in which target designation information is put in an arbitration code. FIG. 1 is a configuration diagram of an information processing system including a bus bridge device according to the first embodiment. In FIG. 1, 103 is a processor that performs information processing while transmitting and receiving data via the bus 105, and is also called a bus master. Reference numeral 104 denotes a memory that receives a read / write command from the processor and transmits / receives data, and is also called a bus slave. 1
Reference numeral 06 denotes an input / output device, which is also a type of bus slave. A bus 105 serves as a data transmission / reception path between the bus master and the bus slave, and includes an address / data bus, an arbitration bus for solving a conflict problem among a plurality of bus masters, and an arbitration control signal.

FIG. 2 is a functional block diagram of the bus bridge device according to the first embodiment, and shows a configuration peculiar to the first embodiment. 2, the same reference numerals as those in FIG. 1 denote the same or corresponding parts. In FIG. 2, 11
Reference numerals a, 12a and 13a are an address / data bus, an arbitration control signal and an arbitration bus of the upper bus 105a, and 11b, 12b and 13b are an address / data bus, an arbitration control signal and an arbitration bus of the lower bus 105b. The arbitration buses 11a and 11b have an arbitration code composed of an arbitration priority 101 for determining one from a plurality of bus requesters (for example, the processor 103) and target instruction information 102 indicating the position of the final target bus. Forward. As the target instruction information 102, for example, as shown in FIG. 1, a value (bus 1 to 6) that does not overlap all the buses in the system is determined, and if the final access destination is the "bus 6", the value is set. The code that indicates is the target designation information.

Reference numeral 110 is an upper bus 105a and a lower bus 10.
5b is a bus bridge, 111 is a distributed arbitration circuit of a higher-level bus, 112 is a hardware configuration of the entire system, and particularly a system configuration that shows the position of each bus 105 and the position of a target device connected to those buses. Data, 113 is the target instruction information 102 in the arbitration bus 13a of the upper bus 105a.
And a system configuration data 112 to determine whether the target is ahead of the lower bus 105a,
Reference numeral 114 is a lower bus distributed arbitration circuit that executes distributed arbitration to the lower bus 105a to request the lower bus from the result of the comparator 113.

For the sake of simplicity, this block diagram focuses on the access from the upper bus 105a to the lower bus 105b, but in reality, the lower bus 105a.
In order to access the upper bus 105a from b, a comparator 113 and the like are provided in the reverse direction, and data can be transferred from the lower bus 105b to the upper bus 105a.

Next, the operation will be described. Upper bus 10 in FIG.
5 shows a timing diagram from the start of arbitration of 5a to the request of the lower bus 105b. In FIG. 3, the same reference numerals as those in FIG. 2 represent the signals of the same parts. First, in the upper bus 105a, the bus requestor acquires the right of use in synchronization with the arbitration control signal 12a. The acquisition of the usage right is performed by the following five phases, and each phase is identified by the arbitration control signal 12a. For example, the three signal lines A, B, C of the arbitration control signal 12a are 0,
When it becomes 1 or 0, it can be identified as the start phase.

[Starting Phase] In the starting phase, the bus masters requesting bus acquisition output the arbitration code to the arbitration bus 13 all at once. This arbitration code is the bus acquisition priority of the bus master.

◆ Competition Phase Next, the competition phase will be started. Early in the competition phase,
Since a plurality of bus requesters output the arbitration code, a signal in which the arbitration code of each bus requester is wired-OR exists in the arbitration bus 13a. Then, in this competition phase, each bus requester compares its own priority with the priority of other bus requesters, and the requester with the arbitration code having a lower priority than the other bus requesters determines the arbitration bus. 1
Stop the output to 3. The bus requester determines the priority by a well-known technique such as IEEE Std 896.1-1991 p41 fig5. The bus requester who has acquired the right to use the bus becomes the bus master.

◆ Decision Phase Next, the decision phase is entered. As a result of the output of the low priority bus requester being stopped in the competition phase, the bus acquirer's arbitration code remains in the decision phase and the bus requester with that code can use the bus after the waiting phase. In this determination phase, unlike the conventional bus connection method, the arbitration control signal 12a remaining on the upper bus is output to the arbitration control signal 12b on the lower bus. This arbitration control signal 1
The output control of 2b is performed as follows.

First, the comparator 113 receives the target instruction information 102 from the arbitration code of the arbitration bus 13a, and the system configuration data 11
It is determined by referring to 2 whether or not the target is connected ahead of the lower bus 105b. At this time, the lower bus 10
If it is determined that the connection is made after 5b, the bus request signal 1 is sent to the lower bus distributed arbitration circuit 114.
16 is output. For example, in the example of FIG. 1, in the bridge 110 in which the bus 3 is the upper bus 105a and the bus 4 is the lower bus 105b, the upper bus 105a to the lower bus 1 are connected.
The access transferred to 05b is access to the bus 4, bus 5, and bus 6. This information is stored as the system configuration data 112, and the comparator 113 determines whether the target instruction information 102 indicates any of the buses 4, 5, and 6.

Upon receiving the bus request signal 116, the lower bus distributed arbitration circuit 114 starts the arbitration process in synchronization with the arbitration control signal 12b. Then, the arbitration bus 11b of the lower bus is connected to the arbitration bus 13 of the upper bus.
Output the arbitration code on a. At this time, the arbitration process for the lower bus 105b is
Similar to the start, race, and decision phases described above, the lower bus arbitration circuit 114 becomes one of the bus requestors.

Standby Phase The standby phase is a phase of waiting until the address / data bus becomes idle. Here, the reason why the waiting phase is necessary is that the arbitration processing is performed even when the address / data bus is in use.

Master Phase In the master phase, the bus master that has acquired the usage right transfers the address and data to the address / data bus 11 and executes the access. The address or data is output to the address / data bus 13b via the output buffer 118. At this time, the lower bus distributed arbitration circuit 114 outputs the output buffer 118.
Output control. That is, output is not performed when the right to use the lower bus 105b is not obtained as in the start phase, and is output when the right to use is obtained as in this master phase. Switch. This switch operation is controlled by the output control signal 119.

According to the first embodiment, the following effects can be obtained. As apparent from FIG. 22, in the conventional bus bridge device, the right to use the upper bus 105a is acquired and the address is transmitted in the master phase.
It is determined based on this address whether to output to the lower bus 105b. Therefore, the arbitration processing to the lower bus 105b was started after the master phase. On the other hand, according to the first embodiment, in the best case, the arbitration process of the lower bus 105b is started from the decision phase as shown in FIG.
Lower bus 105 earlier than the prior art as shown in FIG.
The usage right of b can be acquired. That is, the upper bus 105a
In the above, the bus owner starts the arbitration of the lower bus 105b before starting the access on the address / data bus 11a and preempts the bus, thereby reducing the overhead generated at the time of access through the hierarchical bus.

According to the bus bridge device of the present invention, the bus prefetching means predicts an access from the arbitration code to another bus from the instruction information of the access destination in the arbitration code, and the lower order is made before starting the access by the address / data bus. By starting the arbitration of the bus 105b, the time from the request for the upper bus 105a to the request for the lower bus 105b can be shortened.

Embodiment 2 The second embodiment is an embodiment provided with a bus prefetching means having a conversion function of target instruction information.

FIG. 4 shows a bus bridge device in which the target information conversion function is added to the bus bridge device 110 of FIG. 2 of the first embodiment. Therefore. 4, the same reference numerals as those in FIG. 2 represent the same or corresponding parts. A conversion table 120 stores conversion information for converting the target information of the lower bus 105b defined by the upper bus 105a into the target information defined by the lower bus 105b.
Reference numeral 21 is a target information conversion circuit that converts the target information received from the upper bus 105a for the lower bus 105b based on this conversion table.

Next, the operation will be described. In the operation of the second embodiment, the target instruction information 102 of the arbitration bus 13a of the upper bus 105a is transferred to the lower bus 1
Embodiment 1 except that the information defined in the lower bus 105b is converted in the process of transferring to 05b.
This is the same as the operation of the bus bridge. Therefore, the operation characteristic of the second embodiment will be described below.

When the target information conversion circuit 121 receives the target instruction information 102 from the higher order arbitration bus 13a, it receives the target instruction information 1
The target information conversion table 120 is searched for the target instruction information of the lower bus corresponding to No. 02. The target instruction information received by the target information conversion circuit 121 is
It is extracted from the arbitration code remaining in the decision phase. For example, the target information conversion table 120
Assuming that the contents are as shown in 120a, when the target designation information "bus 4" is received, the target designation information "bus A" is searched. The search result is transmitted to the lower bus distributed arbitration circuit 114 and used as the target designation information 102.

As described above, in the second embodiment, the target designation information can be individually defined for each layer bus, and even in such a case, the arbitration is normally performed and the bus bridge device functions. Therefore, a flexible system can be constructed.

Embodiment 3. The third embodiment has an address early output means and is capable of performing arbitration processing at a higher speed.

FIG. 5 shows a bus bridge device in which the function of outputting an address to a lower bus at an early stage is added to the bus bridge device 110 of FIG. 2 of the first embodiment. Therefore. FIG.
2, the same reference numerals as those in FIG. 2 represent the same or corresponding parts. 511a is connected to the address / data bus 11a, and judges from the address sent to the address / data bus 11a whether or not there is a bus slave indicated by the address at the connection destination of the lower bus 105b. In this case, the address decoder outputs the lower bus request signal. Similarly, 512a is connected to the address / data bus 11a, and the address on the address / data bus 11a,
Alternatively, it is an address / data buffer for temporarily storing data. An output buffer 513a outputs the address or data stored in the address / data buffer 512 to the lower bus 105b based on the output control signal output from the lower bus distributed arbitration circuit 114. The address decoder 511a described above,
Address buffer 512a and output buffer 513
A functions to access the upper bus 105a to the lower bus 105b. Conversely, lower bus 105b
The address decoder 511b, the address / data buffer 512b, and the output buffer 513b are provided to access the upper bus 105a.
These circuits have address decoders 511a and 511a, respectively.
Address / data buffer 512a, output buffer 51
The operation corresponding to 3b is performed. An output control signal for controlling the output buffer 513b is given from the upper bus distributed arbitration circuit 112.

Next, the operation will be described. FIG. 6 shows a timing chart of the arbitration bus 13a and the address / data bus 11a of the upper bus 105a. Upper bus 1
At 05a, the bus requestor acquires the right of use in synchronization with the arbitration control signal lines A, B, and C. Acquisition of this usage right is composed of five phases. The operation of each phase will be described below. Since the basic operation is the same as the operation described in the first embodiment, the operation characteristic of the third embodiment will be described.

◆ (Upper Bus) Start Phase In the start phase, the bus requester sends the arbitration priority 101 to the arbitration bus 13a and the address to the address / data bus 11a. At this time, there are a plurality of bus requesters. In the first embodiment, the target instruction information 101 is transmitted to the arbitration bus 13a, but in the third embodiment, the address substitutes for the target instruction information 101, so it is not necessary to transmit the target instruction information 102. (Thus, the number of signal lines required for the arbitration bus 13a can be reduced.)

◆ (Upper Bus) Competition Phase In the competition phase, each bus requester compares its own arbitration priority with the signal on the arbitration bus 13a, and its own arbitration priority is higher than other bus requesters. When it is determined to be low, the transmission of the arbitration priority and the address is stopped.

◆ (Upper bus) decision phase In the decision phase, the arbitration priority and the address of the bus requester who did not stop the transmission in the competition phase remain. The address decoder 511a decodes the address on the address / data bus 11a and determines whether or not the address represents the connection destination of the lower bus 105b.

When the address indicates the connection destination of the lower bus 105b, the lower decoder request signal is output from the address decoder 511a. Upon receiving the lower bus request signal, the lower bus distributed arbitration circuit 114 starts the arbitration process for the lower bus 105b. This arbitration process is executed by the lower bus distributed arbitration circuit 114 acting as a bus requester and performing the start, race, and decision phases as described above for the lower bus 105b. At this time, the address is also output as described above.

Decoding by the address decoder 511a shown in FIG. 5 is determined depending on the configuration of a predetermined logic circuit, whether to output the lower bus request signal or not. However, when the system configuration is hierarchical as shown in FIG. 1 or has a complicated configuration such as a large number of bus slaves connected,
The system configuration data may be separately stored so that a large amount of information can be stored, and the address may be determined by referring to the system configuration data. In this case, when the system configuration is changed, it is possible to deal with a system having a new configuration simply by updating the system configuration data.

◆ (Upper bus) master phase After the decision phase, the standby phase ends and the master phase is entered. In the master phase, the bus master transmits data to the upper bus 105a. This data is stored in the address / data buffer 512a.

◆ (Lower Bus) Master Phase When the lower bus distributed arbitration circuit 114 acquires the right to use the lower bus 105b and enters the master phase,
The lower bus distributed arbitration circuit 114 outputs an output control signal meaning "output" to the output buffer 513a. The output buffer 513a receiving this output control signal starts outputting the data stored in the address / data buffer 512a to the lower bus 105a. At this time, since the address has already been output to the address / data bus 11b, the access can be executed immediately. As described above, data transfer from the upper bus 105a to the lower bus 105b becomes possible. And
When the master phase ends and the data transfer to the lower bus 105b ends, the output control signal changes to a signal meaning "stop output", and output by the output buffer 513a stops.

According to the third embodiment, the arbitration processing of the lower bus is started early and the data can be output to the lower bus early, so that the overhead of bus access can be reduced. In particular, since the address is obtained in the decision phase, the bus access overhead can be further reduced as compared with the case where the address is transmitted in the master phase as in the first embodiment.

In the above description, the access from the upper bus to the lower bus has been described, but the same operation can be performed and the same effect can be obtained from the lower bus to the upper bus. In that case,
The address decoder 511b, the address / data buffer 512b, the output buffer 513b, and the high-order bus distributed arbitration circuit 112 are respectively replaced by the address decoder 511a, the address / data buffer 512a, the output buffer 513a, and the low-order bus distributed arbitration circuit 114 described above. Perform an action.

Embodiment 4 The fourth embodiment is an embodiment in which the data transfer amount is increased by using the arbitration bus as a data bus. FIG. 7 is a functional block diagram illustrating the configuration of the bus bridge device according to the fourth embodiment. In FIG. 7, FIG.
The same reference numerals denote the same or corresponding parts. 512c
5 corresponds to the address / data buffer 512a in FIG. 5, and temporarily stores the data of the address / data bus 11a and the data of the arbitration bus 13a and outputs them to the output buffers 513a and 514a, respectively. Is. Similarly, 512d corresponds to the address / data buffer 512b in FIG. 5, and temporarily stores the data of the address / data bus 11b and the data of the arbitration bus 13b, and outputs the addresses to the output buffers 513b and 514b, respectively. -It is a data buffer.

Reference numeral 514a is an output buffer for outputting the data of the upper bus arbitration bus 13a stored in the address / data buffer 512c to the lower bus arbitration bus 13b in accordance with the output control signal of the lower bus distributed arbitration circuit 114, When the output control signal is a signal that means "output", output is performed, and when the output control signal is a signal that means "stop output", output is stopped. Similarly, according to the output control signal of the higher-order bus distributed arbitration circuit 112, the address 514b also receives an address
It is an output buffer that outputs the data of the arbitration bus 13b of the lower bus, which is stored in the data buffer 513d, to the arbitration bus 13a of the upper bus, and operates similarly to the output buffer 514a.

Next, the operation will be described. Since the operation of the fourth embodiment is basically the same as that of the third embodiment, the characteristic operation of the fourth embodiment will be described. FIG. 8 shows the arbitration buses 13a and 13b of the upper bus 105a and the address / data bus 11a.
11b shows a timing diagram of 11b. The operation up to the standby phase is the same as that of the bus bridge of the third embodiment, so the characteristic operation of the fourth embodiment in the master phase will be described.

After the decision phase, the transmission of the arbitration code to the arbitration bus 13 is stopped. Then, in the master phase, part of the data is transmitted to the arbitration bus 13a. This data becomes all the data including the data on the address / data bus 11. For example, when the arbitration bus 13a has a width of 32 bits and the bus for transferring the data of the address / data bus 11a has a width of 32 bits, a total of 64-bit width data can be transferred.

The operation in this master phase is performed as follows. First, in the master phase, when data is transmitted to the address / data bus 11a and the arbitration bus 13a, this data is stored in the address / data buffer 512c. On the other hand, in the lower bus distributed arbitration circuit 114, the arbitration process for acquiring the right to use the lower bus is started from the decision phase, and when the right to use the lower bus is obtained, the output control signal means “output”. Turn into a signal. Output buffer 513 that has received this output control signal
a and 514a sequentially output the data stored in the address / data buffer 512c by the FIFO. At this time, the output buffer 513a outputs the data of the address / data bus 11a, and the output buffer 514a outputs the data of the arbitration bus 13a.

When the data transfer is completed and the master phase of the lower bus is completed, the lower bus distributed arbitration circuit 114 outputs the output control signal which means "output stop", and the data of the output buffers 513a and 514a is output. The output stops.

In the bus bridge device of the fourth embodiment, the data width can be expanded without expanding the address / data bus by using the arbitration bus during the unused period as the data bus.

In the above description, the access from the upper bus to the lower bus has been described, but the lower bus and the upper bus operate in the same manner and the same effect can be obtained. In that case, the address / data buffer 512d and the output buffer 514b perform the above-mentioned operations instead of the address / data buffer 512c and the output buffer 514a, respectively.

Embodiment 5. The fifth embodiment is an embodiment in which the bus occupancy rate of the entire system is reduced when the internal bus is used by selectively using the internal bus request signal and the external bus request signal.

FIG. 9 is a functional block diagram showing an information processing system having a plurality of buses according to the fifth embodiment. In FIG. 9, reference numerals 901a to 901c denote a processor that requests data transmission / reception, a bus master such as a DMA controller, and 9
Reference numerals 02a to 02c are bus slaves that receive or transmit data in accordance with instructions from the bus master, and are, for example, memories, input / output devices, and the like. Reference numerals 903a to 903 denote buses connecting the bus master 901 and the bus slave 902, and 90
Reference numerals 4a to 4c are internal bus request signals connected to the bus masters 901a to 901c and requesting access to each of the bus arbiters 906a to 906c using the internal bus.
Here, the internal bus means a bus that the bus master 901 can directly access without going through the bus adapter 907, like the bus 903a for the bus master 901a.

Reference numerals 905a-i are external bus request signals for requesting access using the external bus. Here, the external bus is a bus that must be accessed through the bus adapter 907, like the bus 903d for the bus master 901a. 906a to 906 accept the internal bus request signal and the external bus request signal, arbitrate the bus use right based on these request signals (that is, arbitration processing), and permit the bus use based on the arbitration result. A bus arbiter that outputs a signal 908. Here, the bus arbiter 906a is the bus 903.
The permission of use of a is arbitrated, and the permission of use of buses 903b to 903b is also arbitrated for the bus arbiters 906b to 906d.

Reference numerals 907a to 907c are bus adapters which are connected to the two buses 903 and transfer data between the two buses 903 based on the arbitration result of the bus arbiter 906. Also performs protocol conversion. Reference numerals 908a to 908 are bus use permission signals for notifying the arbitration result of the right to use the bus arbiter. Bus request signals 909 a to f request the right to use the bus 903 from the bus arbiter 906 to another bus arbiter 906.

In this specification, the bus master 9
When describing any of 01a to 01c without distinction, it is referred to as a bus master 901. Similarly, bus slaves 902a-
c is a bus slave 902, and buses 903a to 903a to d are the bus 90.
3. Internal bus request signals 904a-c are internal bus request signal 904, external bus request signals 905a-i are external bus request signal 905, bus arbiters 906a-d are bus arbiter 906, and bus adapters 907a-c are bus adapter 90.
7. Bus use permission signals 908a-i are bus use permission signals 908 and bus request signals 909a-f are bus request signals 90
9

Next, the operation will be described. FIG.
10 is a timing chart for explaining the transmission timing of the bus 903, the internal bus request signal 904, the external bus request signal 905, etc. shown in FIG. 9. In FIG. 10, the same symbols as those in FIG. 9 represent the signals of the same parts. FIG. 10 shows two types of access cases. Access case 1 is a case where the bus master 901a accesses the bus slave 902a, which is an access via a so-called internal bus. The other access case 2 is the bus master 901a.
Is accessing the bus slave 902c, which is an access via a so-called external bus.

Access Case 1 First, access through the internal bus of Access Case 1 will be described. The bus master 901a determines from the address to be accessed that the target bus slave 902a is connected to the bus 903a. Then, in step S1, the internal bus request signal 904 is determined based on this determination.
Let a be High. This internal bus request signal 904 is H
When it is IGH, it indicates that the right to use the internal bus is requested.

Next, the internal bus request signal 904a goes low.
Bus arbiter 90 which detected that it became High from
6a starts arbitration of the right to use the bus 903a (that is, arbitration processing). And step S
When the usage right is assigned to the bus master 901a in 2, the bus usage permission signal 908a is set to High. here,
When the bus use permission signal 908 is High, use of the bus 903 is permitted. Next, in step S3, when the bus master 901a detects that the bus use permission signal 908a has become High, it designates an address on the bus 903a and transmits data. The so-called transaction is started.
When the transaction ends, the bus master 901a sets the internal bus request signal 904a to Low at step S4.
Switch to The bus arbiter 906a that has detected this Low signal uses the bus use permission signal 90 in step S5.
Switch 8a to Low.

With the above processing, the access using the internal bus is completed. In this access case 1, another bus 9
03 (external bus) is not subjected to arbitration processing, and addresses and the like are not output to occupy another bus 903, so that the bus occupancy rate of the entire system can be reduced.

Access Case 2 Next, Access Case 2 which is an access via the external bus will be described. First, it is determined that the bus 903 used from the address that the bus master 901a tries to access is an external bus. Here, the bus master 901
It is assumed that a wants to access the bus slave 902c. Then, based on the determination that it is the external bus, the external bus request signal 905a is set to High in step S6.
And When the external bus request signal 905a is HIGH, it indicates that the right to use the external bus is requested.

High of this external bus request signal 905a
The bus arbiter 906a receiving the signal is the bus 903a.
At the same time as arbitrating the usage right for
As a result, a high level bus request signal 909a is output to the bus arbiter 906d. This bus request signal 9
When 09a is High, it indicates that the bus usage right is requested. When the usage right is assigned to the bus master 901a, the bus usage permission signal 908a becomes High in step S7, and it is notified that the usage right has been given.
Addresses and data are transmitted and received using 3a to perform transactions. The address and data output by the bus master 901a are transmitted to the bus adapter 907a and stored in the buffer in the bus adapter 907a. At this time,
One bus 903d according to the instruction of the bus arbiter 906a
If the right to use is not obtained, the stored address and data are not output.

On the other hand, the bus arbiter 906d which detects that the bus request signal 909a is High requests the bus use right to the other bus arbiters 906b and 906c.
The bus request signals 909c and 909 are set to High. At the same time, arbitration of the right to use the bus 903d is started. When the use right is obtained, the bus use permission signal 908e is sent in step S9.
Is High. The bus arbiter 906d that detects this High signal controls the output of the bus adapter 907a and outputs the address or data stored in the buffer in the bus adapter 907a to the bus 903d. These addresses and data are the bus adapter 907.
It is stored in the buffers in b and c.

On the other hand, the bus arbiter 906c which has detected that the bus request signal 909e is High causes the bus 90
Start arbitration of usage rights of 3c. When the use right is obtained, the bus use permission signal 908h is set to High in step S10. Bus arbiter 906 that detects this High signal
The d controls the output of the bus adapter 907c, and outputs the address or data stored in the buffer in the bus adapter 907c to the bus 903c. These addresses and data are transmitted to the bus slave 902c.
The bus slave 902c operates based on these data. If there is data to be transmitted from the bus slave 902c, the data is transmitted.

When the bus master 901a ends the transaction, the external bus request signal 905a
Is set to Low, and the usage right is abandoned. The bus arbiter 906a which has detected this Low signal sets the bus request signal 909a to Low, abandons the right to use the bus 903d, and controls the bus adapter 907a to stop the output to the bus 903d. This stop is performed after transmitting all the addresses and data received from the bus master 901a. The same applies to the data received from the bus slave 902c, which means that the data transmission / reception has been normally completed, that is, this means the end of the transaction.

The termination processing is similarly performed for the bus arbiters 906b and 906c.

As described above, according to the present embodiment, by selectively using the internal / external bus request signal depending on the bus slave to be accessed, it is possible to eliminate unnecessary bus requests, reduce the bus occupation rate, and improve the processing performance of the entire system. The effect is that you can do it. This is apparent from FIG. 10, and in the access case 1 which is an access via the internal bus, the other buses 903c and 903c are not occupied. Therefore, separate communication is possible on these buses 903c and 903d.

Further, in the third embodiment, the signals requesting the bus use right are propagated all at once, and the use right acquisition process, that is, the arbitration process is started early.

Embodiment 6 FIG. The sixth embodiment is an embodiment in which a bus code signal designating a bus used for access is transmitted to prevent access to a bus not used for access, thereby reducing the bus occupation rate.

FIG. 11 is a functional block diagram showing an information processing system having a plurality of buses according to the sixth embodiment.
11, the same reference numerals as those in FIG. 12 represent the same or corresponding parts. 910a-d are the bus arbiter 90 of FIG.
6 is added with a new function to receive the bus code signal 911 to be accessed, the connection relation of each bus 903 is stored, and the bus use permission signal 908 and the bus code signal 9 are stored based on the bus code signal 911 received from the outside.
It is a bus arbiter that determines the bus arbiter 906 that outputs 11. 911a to f are bus code signals for notifying the bus number of the bus 903 to be accessed. In the sixth embodiment, the bus code signal 9
When describing one of 11a to 11f without specifying it, it is referred to as a bus code signal 911.

The bus master holds a mapping table showing the correspondence between the address to be accessed and the bus number to which the slave corresponding to that address is connected.
The contents of the mapping table are set / updated when the system starts up or when the system configuration changes.

Next, the operation will be described with reference to FIG. FIG.
2, the same reference numerals as those in FIG. 11 represent the same signals. ◆ Access Case 1 First, regarding Access Case 1 via the internal bus,
This is the same as the fifth embodiment.

Access Case 2 Next, the access case 2 via the external bus will be described. Since the basic operation of the access case 2 is the same as that of the fifth embodiment, the characteristic operation of this embodiment will be described. First, when the bus master 901a accesses the bus slave 902c, the bus master 901a calculates the number of the bus to which the bus slave 902c is connected, that is, the bus code, from the address to be accessed. This bus code is calculated from the above mapping table.

Next, at the same time as the external bus request signal 905a, the calculated bus code is output as a bus code signal 911a. The bus arbiter 910a which has received the bus code signal 911a receives the bus code signal 911a.
The bus arbiter 910 that should output the bus request signal 909 is selected based on the above. This selection is performed based on the bus code signal 911a from the bus code table storing the connection relationship of each bus. And the selected bus arbiter 911
To the bus request signal 909 and the bus code signal 911
Is output. In the case of the bus arbiter 910a, the bus request signal 909 and the bus code signal 911 are sent to the bus arbiter 9
Output to 10d.

The bus arbiter 9 that receives these signals
10d selects the bus arbiter 910 that outputs the bus request signal 909 and the bus code signal 911 as described above. The bus arbiter 910d has three bus arbiters 9
Since 10 are connected, these bus arbiters 91
The bus arbiter 910c is selected from 0. The reason why the bus arbiter 910c is selected is that the bus arbiter 910c is selected.
c is a bus 903 to which a bus slave 902c is connected
This is because it is the bus arbiter 910 that manages the right to use c. The reason why the bus arbiter 910b is not selected is that the bus arbiter 910b is an unnecessary bus arbiter 910 for accessing the bus slave 902c.

FIG. 12 shows two types of access cases. In access case 1, the bus master 901a accesses the bus slave 902a. In access case 2, the bus master 901a transfers the bus slave 902a.
2c is accessed. In access case 1, the bus master 901a determines from the address to be accessed that the slave is connected to the bus 903a, and outputs the internal bus request signal 904a. Bus arbiter 910
a receives the internal bus request signal 904a, the bus 90
It arbitrates the usage right of 3a and outputs the bus usage permission signal 908a after the usage right is acquired. When the bus master 901a receives the bus use permission signal 908a, it confirms that the bus 903a is in the idle state and then starts a transaction.

Finally, the bus request signal 909e to the bus arbiter 910c becomes High, and the access, that is, the transaction is started as in the fifth embodiment.

According to the sixth embodiment, by using the bus code signal of the bus slave to be accessed,
There is an effect that the bus occupancy rate can be reduced by eliminating unnecessary requests to the bus arbiter 910. That is, in the above example, the bus 903 not involved in the access between the bus master 901a and the bus slave 902c.
For b, the arbitration process is not performed and the bus is not occupied.

Embodiment 7 FIG. The seventh embodiment is an embodiment in which an access request accepted from a bus master is transmitted to a bus slave, and a retry request signal is output to the bus master to release the bus, thereby reducing the load on the bus. FIG. 13 is a block diagram showing the seventh embodiment. In FIG. 13, 1301 is a bus master device that activates a transaction on the bus, 1302 and 1303 are bus slaves that respond to requests from the bus master, 1304 is a bus that connects a bus bridge and a bus slave, 1305 is a bus that connects 1304 and 1306. Bus bridge, 1
306 is a bus that connects the bus master device and the bus bridge, 1307 is a register that holds the address range of the bus 1304, 1308 is a comparator that compares the address on the bus with the value of the register, and 1309 is a retry request according to the result of the comparator. A retry control unit 1310 for outputting is a retry request signal for notifying the bus master device 1301 of a retry request. The register 1307 is preset when the system is started up.

Next, the operation will be described with reference to FIG. A case where the bus master device 1301 makes a read access to the bus slave 1302 will be described. Bus master device 1
301 receives the bus use permission of the bus 1306,
After confirming that the bus 1306 is idle,
Output a transfer request. Bus bridge 1305 is bus 1
When the request from 306 is received, the address is sent to register 1
Compare with 307. When the retry control unit 1309 determines from the result of the comparator 1308 that the bus 1304 is accessed, the retry control unit 1309 outputs a retry request signal 1310 to the bus master device 1301.

When the bus master device 1301 receives the retry request signal 1310, it releases the bus 1306 and enters the retry wait state. The bus bridge 1305
A retry request signal 13 is sent to the request from the bus master device 1301.
At the same time as outputting 07, a request for acquiring the bus 1304 is output. When the use permission of the bus 1304 is acquired, a read transfer request for the address that has output the retry request is issued. The bus master device 1301 acquires the bus 1306 again at a predetermined retry interval,
Start a transaction, bus bridge 1305
Receives a request from the bus master device 1301 and returns the data read during the retry interval to the master device 1301. If the read data cannot be read from the bus slave 1302 during the retry interval, the bus bridge 1305 outputs the retry request signal 1310 to the bus master device 1301 again.

According to the above embodiment, even when the bus protocol that does not support the split access method is mixed in the system, the bus occupation time is shortened while maintaining the compatibility with the conventional bus protocol and the bus transfer is performed. The performance can be improved. And a bus master that does not support the split access method does not need to have a special circuit for the split access method,
The existing retry request circuit can reduce the bus load as in the split access method. That is,
Since the bus is temporarily released for read access on a bus that does not support split transfer,
This has the effect of avoiding wasted bus occupation time.

Embodiment 8 FIG. The eighth embodiment is an embodiment in which the bus bridge device of the seventh embodiment is loaded with a function capable of setting a different retry time for each address range.

FIG. 15 is a functional block diagram showing an information processing system using the bus bridge device according to the eighth embodiment. 15, the same reference numerals as those in FIG. 16 represent the same or corresponding parts. Reference numeral 1501 is a table holding the address ranges of a plurality of bus slaves and retry times corresponding to those address ranges, 1502 is a comparator for comparing the address ranges of the table with the addresses on the bus, 1503
Is a retry controller that outputs a retry request and a retry time according to the result of the comparator. Table 1
501 is preset when the system is started up.

Next, the operation will be described with reference to FIG. A case where the bus master device 1301 makes a read access to the bus slave 1302 will be described. Bus master device 1
301 receives the bus use permission of the bus 1306,
After confirming that the bus 1306 is idle,
Output a transfer request. Bus bridge 1305 is bus 1
Upon receiving the request from 306, the address and table 1
The address ranges of 501 are compared. Retry control unit 15
Based on the result of the comparator 1502, 03 outputs a retry request signal 1310 to the bus master device 1301 when accessing the bus 1304. At this time, the comparator 150
Based on the comparison result of 2, the retry time corresponding to the address range is read from the table 1501 and the read retry time is output onto the bus 1306.

When the bus master device 1301 receives the retry request 1310, it acquires the data on the bus 1306 and then releases the bus. The acquired data is stored in the retry interval register (not shown). Bus bridge 1
The 305 outputs a retry request to the request of the bus master device 1301, and then outputs a bus request to acquire the bus 1304. If you get permission to use the bus 1304,
Issue a read transfer request for the address that issued the retry request. The bus master device 1301 acquires the bus 1306 again when the time set in the retry interval register has elapsed, and performs a read access to the bus slave 1302. The bus bridge 1305 is used by the bus master device 13
When the request of 01 is received, the read data read during the retry interval is returned.

According to the above-described embodiment, the bus protocol that does not support the split access method is mixed in the system, and the unnecessary retry process until the read data is acquired is deleted. Transfer performance can be improved while maintaining compatibility. The bus slaves 1302 and 1303 often have different times for receiving a processing request and then returning a processing result. For example, when accessing a memory, a value is returned in a very short time, but a low-speed device is accessed. In such an input / output device, it takes a very long time to obtain a processing result. In the eighth embodiment, the transfer performance can be improved even in the above case.

Ninth Embodiment In the ninth embodiment, the access order to each bus slave is controlled, and the access requests to the bus slaves that have not been accessed for a long time are preferentially executed to equalize the number of access to the bus slaves. In this embodiment, the processing is performed at high speed.

FIG. 17 is a functional block diagram of an information processing apparatus that executes the bus access method according to the ninth embodiment. In FIG. 17, reference numeral 1700 is a bus master that accesses the bus slaves 1713a and 1713b via the bus 1715, and 1713a and 1713b are bus slaves to be accessed, such as a memory and an input / output device. In FIG. 17, two bus slaves 1713a and 1713b are connected, but in reality, more bus slaves 1713
Are often connected. In addition, this Embodiment 9
In the description, when the bus slaves 1713a and 1713b are described without specifying them, they are described as the bus slaves 1713.

Reference numeral 1701 denotes a bus control device which is provided in the bus master 1700 and connects the internal bus 1711 and the bus 1715. In the ninth embodiment, the internal bus means a bus provided in the bus master. 1702a ~
c receives an address and data from the internal bus 1711, respectively, stores the received data, and
It is a request buffer register that outputs to the selector 1706.

Reference numerals 1703a to 1703c are conversion maps for acquiring the addresses stored in the corresponding request buffer registers 1702a to 1702c and outputting them to the area division ID based on a predetermined storage table using the addresses as keys. This area division ID is the bus slave 1713a, b
Is an identifier for identifying the bus slave 171.
The area division ID “3” is assigned to 3a and the bus slave 1713b is assigned “2”. FIG. 18 is an example of the stored contents of the conversion maps 1703a to 1703c, in which area division IDs are stored for each memory area sequentially mapped from address 0. Here, assuming that addresses 1000 to 2000 are area divisions 1 assigned to the bus slave 1713a and addresses 2000 to 3000 are memory areas 2 assigned to the bus slave 1714b,
When the address input to the conversion map is 1500, the output is area division 2, that is, area division ID = 2.

Reference numeral 1704 is a bus monitor for monitoring the access status of the bus 1715 and outputting the access status to the transfer control circuit 1705.
This is performed by monitoring which bus slave 1713a is accessed and storing the access history of a predetermined period. The storage content of the access history is the area division ID, and the address is converted into the area division ID and stored based on the information of the address conversion map 1709 that stores the same content as the conversion maps 1703a to 1703c. Then, the stored area division IDs are sequentially discarded from the oldest information.

1705 receives the area classification ID from the conversion maps 1703a to 1c, receives the access history from the bus monitoring circuit 1704, determines the bus slave 1713 to be accessed next, and requests buffer register 1702a corresponding to this bus slave 1713. It is a transfer control circuit for instructing ~ c. The bus slave is determined based on the access frequency to the bus slave 1713. In the ninth embodiment, for example, the area division IDs are stored for the ten most recent accesses from the latest,
The one having a low access frequency is set to have a high priority, and the address of the area division having no identical area among the ten area division IDs has the highest priority, and the next highest priority is 10. Although the same ID exists in each area division ID, it is an address of an area division for which the time during which it is not accessed for a long time is long from the present.

Reference numeral 1706 designates a plurality of request buffer registers 1
The selectors 702a to 702c are connected to the request buffer registers 1702a to 1702c to select the address and data of the request buffer register designated by the transfer control circuit 1705 and output to the bus 1715.

Next, the operation will be described. The request buffer register 1702 stores, as an access request to the bus slave 1713, the memory area 1, the memory area 2, and the I area, respectively.
It is assumed that the access request for the / O area is stored. Here, the memory area is, for example, an area in which a processor operation instruction or data is stored.
The / O area is an area where control commands such as DMA control are stored, and they do not interfere with each other.

First, in the bus control section 1701, the address and data received from the internal bus 1711 and output to the bus 1715 are stored in the empty request buffer register of the request buffer register 1702. Internal bus 171
1 is released after transferring the address and data, and can move to the next bus cycle. In this way,
Access requests from the internal bus 1711 to the bus 1715 are received one after another independently of acquisition of the usage right of the bus 1715, distributed to a plurality of request buffer registers, and stored.

The address signal 1707 stored in the request buffer register 1702 is the address conversion map 1 respectively.
The data is converted into an ID value that identifies the transmission destination bus slave by 703, and is output to the transfer control circuit 1705. The transfer control circuit 1705 sends the select signal 1 to the selector 1706.
710 is sent to sequentially transfer the access requests 1712 from the request buffer register 1702 to the bus 1715.

The bus master device uses the bus 17 to process the request stored in the request buffer register 1702.
The request signal is output to 15. When the use permission is acquired, the bus monitoring circuit 1704 is referred to and the access to the bus slave device which has not been accessed in the previous transaction is preferentially processed. For example, the request buffer register 1702
When the access request to the bus slaves 1713a and 17b is stored in and the ID of the bus slave device 1713a is held in the bus monitoring circuit 1704, the transfer control circuit 1705 selects the access to the bus slave device 1714b. .

Next, the operation will be described below in detail while following the actual flow of data. 19 and 2
0 is a diagram showing a data flow of the information processing apparatus shown in FIG. 19 and 20, the same reference numerals as those in FIG. 17 represent the same or corresponding parts.

First, assume that the bus control device is in a state as shown in FIG. Request buffer register 1702
b and 1702c have 2500 address and 3500, respectively.
An address called an address and data (not shown) corresponding to the address are stored. The request buffer register 1702a is assumed to be in a state immediately after outputting the already stored address and data to the bus 1715, and there is no address currently stored. here,
It is assumed that the address stored in the request buffer register 1702b is an access request older than the address stored in the request buffer register 1702c, that is, the access request stored earlier.

Further, the bus monitoring circuit 1704 uses the bus 17
The access made in the past is monitored at 15 and it is stored as the access history that the access is made in the order of “2 → 2 → 1 → 2 → 7 → 6 → 5 → 2 → 3 → 2”. .

Next, the processing when a new access request is transmitted to the internal bus 1711 from the state shown in FIG. 19 will be described with reference to FIG. First, the data is step S100 → S101 → S102 → S103 → S10.
It is output in the order of 4 → S105.

In step S100, a microprocessor unit or the like (not shown) transfers to the internal bus 1711 150.
Suppose there is a read request for address 0. This read request is sent from the internal bus 1711 to the request buffer register 170.
2a. Here, from the plurality of request buffer registers 1702a to 1702c to the request buffer register 1702a.
Is selected because the request buffer register 1702a
Because it was empty. Step S10
In 1, the address 1500, which is stored in the request buffer register 1702a, is output to the conversion map 1703a. Conversion map 17 that received this address
In 03a, the area division ID is calculated according to the address map stored in advance as shown in FIG. Here, 1
The value of area division ID = 1 is calculated from the address of address 500.

In step S102, the calculated area division ID is output to the transfer control circuit 1705. The transfer control circuit that has received this area division ID selects the request buffer register that outputs the storage content to the bus 1715 from among the plurality of request buffer registers 1702a to 1702c. This selection is made by referring to the access history. For example, when the transfer control circuit 1705 receives the three area division IDs “1”, “2”, and “3” from the three conversion maps 1703a to 1703c, the most access interval among these area division IDs is selected. Choose the long one. In this case, "1" is the area segment ID with the longest access interval, the second is "3", and the shortest access interval is "2" that was accessed last time. The reason for selecting the access to the area section having the longest access interval is that the bus slave 1713 that has made an access immediately before is likely to be busy and may be waited for access. This is because, in the case of, the possibility of waiting for access is low, and the access can be performed at high speed.

In step S103, the transfer control circuit 17
05 outputs a select signal instructing the request buffer register having the area division ID selected. Here, the request buffer register that stores the address corresponding to the selected "1" is 1702a, and the request buffer register 17
Since the values 02a to c are sequentially assigned the values 1 to 3, "1" corresponding to the request buffer register 1702a is output.

In step S104, step S103
The selector 1706, which has received the signal output in step S1, selects one request buffer register a designated by the transfer control circuit 1705 from the plurality of request buffer registers 1702a to 1702c and outputs the storage content to the bus 1715. To do. Here, the commands of address "1500 address" and "read" are output. Request buffer register 1
If the instruction stored in 702 is a write request, for example, the address, the instruction “write”, and the data “10”
"0" is output.

The address, data and the like output to the bus are received by the bus slave 1713 and processed according to their contents. This completes the access.

On the other hand, the bus monitoring device 1704 monitors the address output to the bus and stores which area section has been accessed. This stored content is output to the transfer control circuit 1705 as the above-mentioned access history. In the above example, the address output from the selector 1706 is the address 1500, so the conversion map 1709
The value of the area division “1” is calculated in accordance with the above and is stored as the latest access history. On the other hand, the oldest access history “2” is discarded. Therefore, next, the transfer control circuit 170
The access history output to 5 is “2 → 1 → 2 → 7 → 6 →
5 → 2 → 3 → 2 → 1 ”.

After the above processing, the same processing is performed for the next access request. In the ninth embodiment,
Although the bus monitoring circuit 1704 has the conversion map 1709, if the access by another bus master is not considered, the area division ID selected by the transfer control circuit may be stored directly as the access history. In this case, The conversion map 1709 is not always necessary.

According to the ninth embodiment, since the loads of the slaves are equalized in the system, the processing performance of the entire system is improved.

[0123]

Since the present invention is configured as described above, it has the following effects.

In the bus access method for transferring data between the first bus and the second bus according to the present invention, a plurality of access request devices connected to the first bus can be used to access the first bus. A first indicating the priority of each of the plurality of access requesting devices in order to acquire the right to use the bus.
Of the priority signal and a plurality of target instruction information indicating the location of the device to be accessed, and a priority from the plurality of first priority signals received in the first starting step. A first race step for selecting a high priority first priority signal, and a right to use the first bus to the access requesting device corresponding to the first priority signal selected in the first race step. And the target designation information corresponding to the selected first priority signal indicates the connection destination of the second bus, the selected first priority signal is set as the second priority signal. A first determining step for outputting to acquire the right to use the second bus; a third priority signal indicating the priority of the access requesting device connected to the second bus; and the second priority. Degree accepting signal Starting step, a second competition step of selecting a priority signal having a higher priority among the plurality of priority signals received in the second starting step, and a priority signal selected in the second competition step. A second determining step of granting the right of use of the second bus to the access requesting device corresponding to the second requesting step for starting the second starting step after the first determining step. The right to use the bus can be acquired early, and the bus access can be speeded up.

In the first determining step, the target designating information corresponding to the first priority signal selected in the first competing step is converted into information that can be recognized by the bus arbiter managing the second bus. Since the data is output, even if the location information of each access target corresponding to the first bus and the second bus is different, the bus request signal normally accesses based on the location information of the first bus. It can be carried out.

The target designation information is an address of the device to be accessed, and the first determining step corresponds to the selected first priority information on the address bus of the first bus. Outputting the address, and the second determining step outputs the address corresponding to the selected priority information onto the address bus of the second bus.
On the address bus of the first bus, which is executed after the second determining step and is accessed via the first bus based on the address on the address bus of the first bus. The second master step of accessing via the second bus based on the address of 1) and the address can be obtained at an early stage, so that the access can be performed at high speed.

The first bus includes a first priority bus for transmitting the first priority signal and a first data bus for transferring data, and the second bus is the second bus.
Second priority bus for transmitting the first priority signal or the third priority signal and a second data bus for transferring data, wherein the first master step is within the first bus. Data bus and the first priority bus are used to transmit data, and the first master step is
Since the data bus can be transmitted using the data bus in the second bus and the second priority bus and the priority bus can be used as the data bus, the same effect as that of expanding the data bus width can be obtained. Therefore, data transfer can be performed at high speed.

In the bus access method of the bus bridge device for connecting the first bus and the second bus, the access request device connected to the first bus accesses the access target on the first bus. A first bus request step of selectively outputting an internal bus request signal transmitted when performing an access, or an external bus request signal transmitted when accessing an access target on the second bus, and the first bus request step. The first bus acquiring step for acquiring the right to use the first bus, which is executed after the bus requesting step of the above, and the right to use the second bus when the external bus request signal is output. A second bus request step of outputting a request bus request signal; and a second step of executing after the second bus request step is executed to acquire the right to use the second bus.
And a second bus are accessed, the second bus is requested irrespective of the acquisition of the first bus, and high-speed access is performed for early arbitration processing. If you want to access only the first bus, you do not request the second bus,
The second bus can perform other accesses.

In the bus access method for transferring data between the first bus and the second bus via a bus bridge device connecting the first bus and the second bus, A first request executed by an access requesting device connected to the first bus, acquiring the right to use the first bus, designating an access target connected to the second bus, and outputting a processing request. Step, a retry request step executed after execution of the first request step, the bus bridge device accepts the processing request, and outputs a retry request to the access request device, and the access request device accepting the retry request Is executed after the execution of the first request step and a waiting step of abandoning the right to use the first bus and waiting for a predetermined time. A second requesting step of Tsu di device outputs the processing request to the access requested,
A first processing result transmitting step of transmitting a processing result corresponding to the processing request from the access target and storing the processing result in the bus bridge device, and the processing is executed after the waiting step is completed, and the access requesting device is the first bus A third request step of acquiring a usage right and outputting a transfer request for requesting transfer of the processing result, and the processing result corresponding to the transfer request by the bus bridge device are transmitted via the first bus. A second processing result transmitting step of transmitting to the access requesting device, and even when a bus protocol that does not support the split access method is mixed in the system, the bus protocol is maintained while maintaining compatibility with the conventional bus protocol. The occupied time can be shortened and the transfer performance of the bus can be improved. And an access requesting device that does not support the split access method does not need to have a special circuit for the split access method, and the existing retry request circuit reduces the bus load as in the split access method. High-speed access is possible.

The retry request step calculates a retry time interval according to the access target, and the waiting step waits for the retry time interval, and a different retry time interval can be set for each access target. Since it is possible to set the retry time interval according to, it is possible to reduce unnecessary retries and reduce the load on the bus.

In the bus according to the present invention, a data bus for transmitting data, and prior to acquiring the right to use the data bus, a plurality of access requesting devices transmit priority information for determining the right to use the bus. , And an arbitration bus that transmits data in parallel with the data bus after the acquisition of the right to use, and the arbitration bus can be used as a data bus, the same effect as when the data bus width is expanded is obtained, Access can be performed at high speed.

In the bus connection system according to the present invention, an internal bus request signal connected to the first bus and requesting access to the first bus or an external bus request signal requesting access to the second bus or another bus. A connection is provided between an access request device that selectively outputs a bus request signal, acquires the right to use the first bus, and transmits data to the first bus, and the first bus and the second bus. However, while accepting the internal bus request signal or the external bus request signal output by the access request device, and when accepting the external bus request signal, the external bus request signal is output to another bus arbiter, A bus arbiter that acquires the right to use the second bus and transmits the data received from the first bus to the second bus. In this case, the second bus is requested irrespective of the acquisition of the first bus, and the arbitration process is performed early so that high-speed access can be performed. When only the first bus is accessed, Since it does not require two buses, the second bus can perform other accesses.

A plurality of the other bus arbiters are provided, the access request device outputs a bus code for identifying the second bus or another bus when the external bus request signal is output, and the bus arbiter is the bus arbiter. Select another bus arbiter that outputs the external bus request signal from the plurality of other bus arbiters based on the code, and output the external bus request signal to the selected other bus arbiter,
Since the bus arbiter selects another bus arbiter and relays the external bus request signal, there is no need for signal lines according to the number of bus arbiters, and it is possible to prevent the output of the external bus request signal to the bus arbiter that is not related to access. The entire system can reduce the load on the bus and enable high-speed access.

A second bus in which the first bus to which the processing request is transmitted and the processing device which is the request destination for processing the processing request are connected.
Connected to this first bus, and a bus monitoring unit that monitors the second bus and records the history of request destination information of the processing request made using the second bus as access history information. A plurality of request buffer registers for accumulating the processing request transmitted through the first bus and request destination information of the processing request and the access history information are referred to, and the requests stored in these request buffer registers respectively. A transfer control unit that selects request destination information from which a lot of time has passed since the last access and outputs the instruction information of the request buffer register corresponding to the selected request destination information, and the instruction information. Select one request buffer register from the plurality of request buffer registers based on
A selector unit for outputting the processing request and the request destination information accumulated in the selected request buffer register to the second bus;
In order to distribute the load of each request destination and control the access order, it is possible to prevent sending access that cannot receive processing requests in a busy state and reduce the bus load.
High-speed access is possible as a whole system.

[0135]

[Brief description of drawings]

FIG. 1 is a configuration diagram of a system including a bus bridge device according to a first embodiment of the present invention.

FIG. 2 is a functional block diagram showing a configuration of a bus bridge device according to the first embodiment of the present invention.

FIG. 3 is a timing chart of the bus bridge device according to the first embodiment of the present invention.

FIG. 4 is a functional block diagram showing a configuration of a bus bridge device according to a second embodiment of the present invention.

FIG. 5 is a functional block diagram showing a configuration of a bus bridge device according to a third embodiment of the present invention.

FIG. 6 is a timing chart of the bus bridge device according to the third embodiment of the present invention.

FIG. 7 is a functional block diagram showing a configuration of a bus bridge device according to a fourth embodiment of the present invention.

FIG. 8 is a timing chart of the bus bridge device according to the fourth embodiment of the present invention.

FIG. 9 is a functional block diagram showing a configuration of a bus connection system according to a fifth embodiment of the present invention.

FIG. 10 is a timing chart of the bus bridge device according to the fifth embodiment of the present invention.

FIG. 11 is a functional block diagram showing a configuration of a bus connection system according to a sixth embodiment of the present invention.

FIG. 12 is a timing chart of the bus bridge device according to the sixth embodiment of the present invention.

FIG. 13 is a functional block diagram showing an information processing system using a bus bridge device according to the seventh embodiment of the present invention.

FIG. 14 is a timing chart of the bus bridge device according to the seventh embodiment of the present invention.

FIG. 15 is a functional block diagram showing an information processing system using a bus bridge device according to an eighth embodiment of the present invention.

FIG. 16 is a timing chart of the bus bridge device according to the eighth embodiment of the present invention.

FIG. 17 is a functional block diagram showing a configuration of an information processing device using a bus control device according to a ninth embodiment of the present invention.

FIG. 18 is a diagram showing a data structure of an address map in the ninth embodiment of the present invention.

FIG. 19 is a functional block diagram showing a data flow of the bus control device according to the ninth embodiment of the present invention.

FIG. 20 is a functional block diagram showing a data flow of the bus control device according to the ninth embodiment of the present invention.

FIG. 21 is a functional block diagram showing a configuration of a system using a bus bridge device in a conventional technique.

FIG. 22 is a timing chart of a bus bridge device in the related art.

[Explanation of symbols]

11a Upper bus address / data bus, 11b Lower bus address data bus, 12a Upper bus arbitration control signal, 12 Upper bus arbitration control signal, 13a Lower bus arbitration bus, 13b Lower bus arbitration bus, 1
01 arbitration priority, 102 target instruction information, 110 bus bridge, 111 upper bus distributed arbitration circuit, 112 system configuration data, 113 comparator, 114 lower bus distributed arbitration circuit, 120 target information conversion table, 121 target information conversion circuit, 5
11a / b address decoder, 512a / b address / data buffer, 513a / b address / data output buffer, 901a-c bus master, 9
02a-c bus slave, 906a-d bus arbiter, 907a-d bus adapter, 904a-c
Internal bus request signal, 905a-c external bus request signal, bus code signals 911a-f, 1306 bus, 1307 address range table, 1308 comparator, 1309 retry control unit, 1701 bus control device, 1702a-c request buffer register,
1703a to c conversion map, 1705 transfer control circuit, 1704 bus monitoring circuit, 1715 bus

Claims (11)

[Claims] 1. A bus access method for transferring data between a first bus and a second bus, wherein a plurality of access request devices connected to the first bus are connected to the first bus. A first start step of receiving a plurality of first priority signals indicating the respective priorities of the plurality of access requesting devices and a plurality of target instruction information indicating the location of the device to be accessed in order to acquire the usage right; A first competition step of selecting a first priority signal having a high priority from a plurality of first priority signals received in the first start step; and a selection in the first competition step. The right to use the first bus is granted to the access request device corresponding to the first priority signal, and the target designation information corresponding to the selected first priority signal indicates the connection destination of the second bus. Show A first determining step of outputting the selected first priority signal as a second priority signal to acquire the right of use of the second bus, if the selected second priority signal is connected to the second bus. A second start step of accepting a third priority signal indicating the priority of the access requesting device and the second priority signal, and the priority of the plurality of priority signals accepted in the second start step. A second race step of selecting a high priority signal, and a second decision step of granting the right to use the second bus to the access request device corresponding to the priority signal selected in the second race step. And, the bus access method equipped with. 2. The first determining step converts the target indication information corresponding to the first priority signal selected in the first competition step into information that can be recognized by a bus arbiter managing the second bus. The bus access method according to claim 1, wherein the bus access method is performed by outputting. 3. The target designation information is an address of the device to be accessed, and the first determining step corresponds to the selected first priority information on the address bus of the first bus. And outputting the address corresponding to the selected priority information onto the address bus of the second bus, wherein the second determining step outputs the address corresponding to the selected priority information. A first master step executed after the first decision step and accessing via the first bus based on an address on the address bus of the first bus; and a second master step executed after the second decision step, the address bus 2. A bus access method according to claim 1, further comprising a second master step of accessing via the second bus based on the above address. 4. The first bus comprises a first priority bus for transmitting the first priority signal and a first data bus for transferring data, and the second bus includes the first data bus. A second priority bus for transmitting the second priority signal or the third priority signal and a second data bus for transferring data are provided, and the first master step is the first master step. Data is transmitted using the data bus in the bus and the first priority bus, and the first master step uses the data bus in the second bus and the second priority bus. The bus access method according to claim 3, wherein the data is transmitted. 5. A bus access method for a bus bridge device for connecting a first bus and a second bus, wherein an access request device connected to the first bus is an access target on the first bus. A first bus requesting step of selectively outputting an internal bus requesting signal transmitted when accessing the memory or an external bus requesting signal transmitted when accessing the access target on the second bus, A first bus acquisition step that is executed after the first bus request step and acquires the right to use the first bus; and a second bus usage that is executed when the external bus request signal is output. A second bus request step for outputting a bus request signal for requesting the right, and a second bus acquisition step for executing the second bus request step and executing the second bus request step to acquire the right to use the second bus. Bus access method with Tsu and up, the. 6. A bus access method for performing data transfer between a first bus and a second bus via a bus bridge device connecting the first bus and the second bus, Executed by an access requesting device connected to the first bus to acquire the right to use the first bus,
First request step for outputting a processing request by designating an access target connected to the bus, and executed after the execution of the first request step, the bus bridge device accepts the processing request, and the access request device A retry request step for outputting a retry request, a waiting step in which the access request device that accepts the retry request gives up the right to use the first bus, and waits for a predetermined time; Second request step in which the bus bridge device outputs the processing request to the access request target, and the processing result for the processing request is transmitted from the access target to the bus bridge device. The first processing result transmitting step stored in the device and the above-mentioned access step are executed after completion of the waiting step. The request device acquires the right to use the first bus and outputs a transfer request for requesting transfer of the processing result, and the bus bridge device displays the processing result corresponding to the transfer request. A second processing result transmitting step of transmitting to the access requesting device via the first bus. 7. The bus access method according to claim 6, wherein the retry request step calculates a retry time interval according to the access target, and the waiting step waits for the retry time interval. . 8. A data bus for transmitting data, and prior to acquiring the right to use the data bus, a plurality of access requesting devices transmits priority information for determining the right to use the bus, and after acquiring the right to use the bus. A bus having an arbitration bus for transmitting data in parallel with the data bus. 9. An internal bus request signal connected to the first bus and requesting access to the first bus, or selectively outputting an external bus request signal requesting access to the second bus or another bus. Then, the access requesting device that acquires the right to use the first bus and transmits data to the first bus is connected to the first bus and the second bus, and the access requesting device outputs the data. When the internal bus request signal or the external bus request signal is received, and when the external bus request signal is received, the external bus request signal is output to another bus arbiter to acquire the right to use the second bus. And a bus arbiter for transmitting the data received from the first bus to the second bus. 10. A plurality of the other bus arbiters are provided, wherein the access requesting device outputs a bus code for identifying the second bus or another bus when the external bus request signal is output, and the bus arbiter, The other bus arbiter that outputs the external bus request signal is selected from the plurality of other bus arbiters based on the bus code, and the external bus request signal is output to the selected other bus arbiter. 9. The bus connection system according to item 9. 11. A first bus to which a processing request is transmitted, a second bus to which a request destination processing device that processes the processing request is connected, and a second bus that monitors the second bus. A bus monitoring unit that records, as access history information, a history of request destination information of a processing request made using a bus; a processing request connected to the first bus and transmitted by the first bus; A plurality of request buffer registers for accumulating request destination information of requests and the above access history information are referred to, and a large amount of time has passed from the previous access among the request destination information stored in each of these request buffer registers. A transfer control unit that selects request destination information and outputs instruction information of the request buffer register corresponding to the selected request destination information, and a transfer control unit that selects one of the plurality of request buffer registers based on the instruction information. Bus connection system with select et one request buffer register, a selector for outputting a request destination information stored processing request to the selected request buffer register to the second bus, the.