JP2012150735A - Interconnection apparatus - Google Patents

Abstract

PROBLEM TO BE SOLVED: To suppress increase in storage capacitance with increase of a maximum value for the number of transactions allowed by a bus system.SOLUTION: A transaction information write unit 500 writes transaction information into any one of a plurality of transaction information write regions on the basis of a request each time the request is issued. An entry number write unit 550 writes region information related to the transaction information into a FIFO memory corresponding to a transaction identifier for identifying transaction processing relating to the request each time the transaction information is written. An entry number read unit 600 reads region information from a FIFO memory corresponding to the transaction identifier relating to a response each time the response is redirected. A transaction information read unit 650 reads transaction information from a transaction information write region indicated by the region information each time the region information is read out.

Description

  The present invention relates to an interconnect device, and more particularly to an interconnect device that allows split transactions and transfers data.

  Conventionally, when transferring data from one module to another, a method of connecting the modules with a bus is often used. Of the modules, a module that leads data transfer is called a master, and a module that operates passively is called a slave. For example, a processor is assumed as the master module. As a module serving as a slave, for example, a memory is assumed.

  In a bus system including a plurality of buses having different bus widths and endian systems, a bus bridge that performs data conversion according to a difference in the bus width or the like may be provided. By connecting each bus to this bus bridge, data transfer between the buses becomes possible. These buses and bus bridges are also called interconnects.

  In such a bus system, transfer efficiency can be improved by allowing split transactions. The split transaction is to independently control a data transfer request and actual data transfer in a series of operations (transactions) for data transfer. A bus standard that allows split transactions includes an AXI (Advanced eXtensible Interface) bus.

  When a split transaction is allowed, an interconnect such as a bus bridge needs to hold transaction information regarding the transfer while the transfer between the master and the slave is outstanding. Here, unresolved means a state in which the requested data transfer is not completed. Transaction information is information necessary for control of response transfer. For example, the transaction information is information including a burst length and the number of bursts when performing burst transfer.

  The necessity of the interconnect holding transaction information in the split transaction will be described. Assume a bus system in which two masters M1 and M2 and two slaves S1 and S2 are connected to an interconnect. In this bus system, after M1 issues a request A requesting data transfer to S1, M2 issues a request B requesting data transfer to S2. Request A requests burst transfer, and request B does not request burst transfer. The slaves S1 and S2 return responses in response to the corresponding requests, but the return order of these responses is not necessarily the same as the order in which the requests A and B are issued. In such a case, the interconnect needs to hold transaction information corresponding to each request while each transfer is unresolved in order to determine which response should be burst transferred. By referring to the stored transaction information, the interconnect can appropriately control data transfer.

  As a method for retaining transaction information in the AXI bus, a bus system in which a FIFO (First In First Out) is provided for each transaction identifier has been proposed (for example, see Patent Document 1). The number of FIFO stages is equal to or greater than the maximum allowable number of unresolved transfers. The interconnect stores transaction information corresponding to each request in a FIFO corresponding to the transaction related to the request. According to this configuration, when the interconnect reads transaction information from the FIFO, it is not necessary to search for a corresponding transaction, so that transaction information can be read at high speed.

JP 2008-41099 A

  However, in the above-described conventional technology, it is difficult to suppress an increase in the size of the FIFO accompanying an increase in the maximum number of transactions allowed by the bus system. When FIFOs are provided for each transaction identifier, it is necessary to provide FIFOs for the number of transactions. For this reason, the total storage capacity of each FIFO increases in proportion to the increase in the maximum number of transactions allowed by the bus system.

  The present invention has been made in view of such a situation, and an object thereof is to suppress an increase in storage capacity accompanying an increase in the maximum value of the number of transactions allowed by the bus system.

  The present invention has been made to solve the above problems, and a first aspect thereof is an identifier for identifying a transaction process including a request transfer process and a response transfer process corresponding to the request. A plurality of first-in first-out memories provided for each transaction identifier with respect to a certain transaction identifier, and a buffer including a plurality of transaction information write areas for writing transaction information which is information for controlling the transfer process of the response; A transaction information writing unit that writes the transaction information to any of the transaction information writing areas based on the request each time the request is issued, and the request related to the request every time the transaction information is written An area information writing unit for writing area information indicating the transaction information writing area in which the transaction information is written to the first-in first-out memory corresponding to the transaction identifier, and each time the response is returned, A region information reading unit that reads the region information from the first-in first-out memory corresponding to the transaction identifier, and a transaction information reading unit that reads the transaction information from the transaction information writing region indicated by the region information each time the region information is read When the request is issued from the master, the request is transferred to the slave, and the response is read based on the transaction information read when the response is returned from the slave. The scan is an interconnection device comprising an interconnect portion for transfer to the master. Thereby, the area information indicating the area where the transaction information is written is written in the first-in first-out memory, and the transaction information is read out from the area indicated by the area information read out from the first-in first-out memory.

  The first aspect further includes an overflow first-in first-out memory that holds the area information overflowing from the plurality of first-in first-out memories, and the area information writing unit includes the area information from the first-in first-out memory according to the request. When the area information does not overflow, the area information is written into the first-in first-out memory, and when the area information overflows from the first-in first-out memory according to the request, the area information is written into the overflow first-in first-out memory. The area information is read from the overflow first-in first-out memory when the area information is written into the overflow first-in first-out memory, and when the area information is not written into the overflow first-in first-out memory, the area information is read from the first-in first-out memory. Read Succoth can also. As a result, the area information overflowing from the first-in first-out memory is overflowed and held in the first-in first-out memory.

  In the first aspect, the first-in first-out memory further includes a full flag indicating that the first-in first-out memory cannot hold the area information for each first-in first-out memory, and the area information writing unit It may be determined whether or not the area information overflows. Thus, it is possible to determine whether or not the area information overflows from the first-in first-out memory based on the full flag.

  The first aspect further includes an empty flag indicating that the overflow first-in first-out memory is empty, and the area information reading unit writes the area information into the overflow first-in first-out memory based on the empty flag. It may be determined whether or not. As a result, it is possible to determine whether or not the area information is written in the overflow first-in first-out memory based on the empty flag.

  Further, according to the first aspect, the first-in first-out memory and the overflow first-in first-out memory include one or more entries that are areas for holding the area information, and the number of entries in the first-in first-out memory is the number of unresolved transaction processes. The number of entries in the overflow first-in first-out memory may be a difference between the maximum value and the number of entries in the first-in first-out memory. This brings about the effect that the number of entries in the first-in first-out memory is made more than half of the maximum value of the number of unresolved transaction processes.

  In addition, the second aspect of the present invention provides each group identifier with respect to a group identifier that is an identifier for identifying a group to which a transaction process including a request transfer process and a response transfer process corresponding to the request belongs. A plurality of first-in first-out memories, transaction information that is information for controlling the response transfer process, and a partial bit string that is information obtained by removing the group identifier from the transaction identifier for identifying the transaction process A buffer comprising a plurality of management information write areas for writing as management information, and a management information write for writing the management information to one of the transaction information write areas based on the request each time the request is issued And the management information An area information writing unit that writes area information indicating the transaction information writing area in which the management information is written to the first-in first-out memory corresponding to the group identifier related to the request, and the response is returned The area information reading unit that reads out the area information from the first-in first-out memory corresponding to the group identifier related to the response each time it is read from the transaction information writing area indicated by the area information every time the area information is read out Based on the transaction information reading unit that reads transaction information, and when the request is issued from the master, the request is transferred to the slave, and the transaction information that is read when the response is returned from the slave. An interconnection device comprising an interconnect portion that transfers the response to the master. Thereby, the area information indicating the area where the transaction information is written is written in the first-in first-out memory corresponding to the group identifier, and the transaction information is read from the area indicated by the area information read out from the first-in first-out memory corresponding to the group identifier. This brings about the effect.

  In the second aspect, the management information writing unit writes the management information in any of the transaction information writing areas based on the request, and the transaction identifier in the request A first identifier processing unit excluding the partial bit string from the management information reading unit, the management information reading processing unit that reads the transaction information from the transaction information writing region indicated by the region information, and the response A second identifier processing unit that generates the transaction identifier from the partial bit string and the group identifier included in the read management information. Thereby, the partial bit string is removed from the transaction identifier, and the transaction identifier is generated from the partial bit string and the group identifier.

  According to the present invention, it is possible to achieve an excellent effect that an increase in storage capacity due to an increase in the maximum number of transactions allowed by the bus system is suppressed.

1 is an overall view showing a configuration example of a bus system according to a first embodiment of the present invention. It is a figure which shows the signal which comprises the read address channel in an AXI protocol. It is a figure which shows the signal which comprises the read data channel in an AXI protocol. It is a figure which shows the signal which comprises the write address channel in an AXI protocol. It is a figure which shows the signal which comprises the write data channel in an AXI protocol. It is a figure which shows the signal which comprises the write response channel in an AXI protocol. It is a block diagram which shows the example of 1 structure of the bus bridge in the 1st Embodiment of this invention. It is a block diagram which shows the example of 1 structure of the interconnection part in the 1st Embodiment of this invention. It is a figure which shows one structural example of the FIFO memory group in the 1st Embodiment of this invention. It is a figure which shows an example of the valid flag and transaction information which are hold | maintained at each buffer entry of the buffer 450 in the 1st Embodiment of this invention. It is a figure which shows one structural example of the buffer in the 1st Embodiment of this invention. It is a block diagram which shows one structural example of the transaction information writing part in the 1st Embodiment of this invention. It is a figure which shows an example of operation | movement of the transaction information reading part in the 1st Embodiment of this invention. It is a flowchart which shows an example of operation | movement of the bus bridge in the 1st Embodiment of this invention. It is a flowchart which shows an example of the transaction information write-in process in the 1st Embodiment of this invention. It is a flowchart which shows an example of the transaction information reading process in the 1st Embodiment of this invention. It is a figure for demonstrating operation | movement of the bus bridge at the time of the request issuance in the 1st Embodiment of this invention. It is a figure which shows an example of the state of the buffer after the request issuance in the 1st Embodiment of this invention. It is a figure which shows an example of the state of the FIFO memory after the request issuance in the 1st Embodiment of this invention. It is a figure for demonstrating operation | movement of the bus bridge at the time of the response return in the 1st Embodiment of this invention. It is a figure which shows an example of the state of the FIFO memory after the response return in the 1st Embodiment of this invention. It is a figure which shows an example of the state of the buffer after the response return in the 1st Embodiment of this invention. It is a block diagram which shows the example of 1 structure of the bus bridge in the 2nd Embodiment of this invention. It is a figure which shows one structural example of the FIFO memory group in the 2nd Embodiment of this invention. It is a figure which shows an example of the effective flag and management information in the 2nd Embodiment of this invention It is a figure which shows the example of 1 structure of the buffer in the 2nd Embodiment of this invention. It is a flowchart which shows an example of operation | movement of the bus bridge in the 2nd Embodiment of this invention. It is a block diagram which shows an example of the management information write-in process in the 2nd Embodiment of this invention. It is a flowchart which shows an example of the management information read-out process in the 2nd Embodiment of this invention. It is a block diagram which shows the example of 1 structure of the bus bridge in the 3rd Embodiment of this invention. It is a figure which shows one structural example of the FIFO memory group in the 3rd Embodiment of this invention. It is a flowchart which shows an example of operation | movement of the bus bridge in the 3rd Embodiment of this invention. It is a flowchart which shows an example of the entry number write-in process in the 3rd Embodiment of this invention. It is a flowchart which shows an example of the entry number read-out process in the 3rd Embodiment of this invention.

Hereinafter, modes for carrying out the present invention (hereinafter referred to as embodiments) will be described. The description will be made in the following order.
1. First Embodiment (Example in which buffer entry number is held in FIFO memory)
2. Second embodiment (example in which a FIFO memory is provided for each group)
3. Third embodiment (example of providing an overflow FIFO)

<1. First Embodiment>
[Bus system configuration]
FIG. 1 is an example of an overall view of the bus system according to the first embodiment of the present invention. The bus system includes M masters 110, AXI buses 120 and 130, N slaves 140, and a bus bridge 200. M and N are each an integer of 1 or more. The master 110 is connected to the AXI bus 120, and the slave 140 is connected to the AXI bus 130. The AXI buses 120 and 130 are connected to the bus bridge 200.

  The master 110 is a connection device that leads data transfer, and the slave 140 is a connection device that operates passively. As the master 110, for example, a processor is assumed. For example, a memory is assumed as the slave 140.

  The AXI buses 120 and 130 are buses for transferring data according to the AXI protocol. The bus bridge 200 transfers data according to the AXI protocol, and performs data conversion as necessary in the data transfer. For example, when the bus widths and endian systems of the AXI buses 120 and 130 are different, the bus bridge 200 performs data conversion according to the bus width of the transfer destination bus.

  Here, in the AXI protocol, a read address channel and a read data channel are prepared as paths for a read operation. When a request including a read address is transferred from the master 110 to the slave 140 via the read address channel, read data is transferred from the slave 140 to the master 110 via the read data channel in response to the request. In the AXI protocol, a write address channel, a write data channel, and a write response channel are prepared as paths for a write operation. When a request is transferred from the master 110 to the slave 140 via the write address channel and the write data channel, a write operation is performed in the slave 140 in response thereto. Then, the result of the write operation is transferred from the slave 140 to the master 110 via the write response channel.

  Hereinafter, a signal transferred from the master to the slave via the read address channel and the write address channel is referred to as a request. A signal transferred from the slave to the master via the read data channel and the write response channel is called a response.

  In the AXI protocol, a request transfer process and a response transfer process corresponding to the request form one transaction process. The principle in the AXI protocol is that the same identifier is given to a request and a response included in one transaction. When the same identifier is assigned between different transactions, the order is guaranteed between those transactions.

  Note that the bus bridge 200 according to the above-described embodiment is an example of the interconnection device described in the claims.

[Channel configuration in AXI protocol]
FIG. 2 is a diagram showing signals constituting a read address channel in the AXI protocol. The read address channel is a channel for transmitting a read address from the master 110 to the slave 140. The read address channel includes a read address identifier, a read address, a burst length, a burst size, a burst type, a lock type, a cache type, a protection type, a read address valid signal, and a read address ready signal. Of these signals, only the read address ready is a signal from the slave 140, and the other signals are signals from the master 110.

  The read address identifier ARID [3: 0] is a 4-bit tag for identifying the read address group of the signal. In the AXI protocol, when the master issues a transaction, the same identifier is assigned when the slave requests to maintain the order relationship. In other words, there is no guarantee that the order relationship is maintained between transactions having different identifiers.

  The read address ARADDR [31: 0] is a 32-bit address to be read and is a signal indicating an initial address in burst transfer.

  The burst length ARLEN [3: 0] is a 4-bit signal indicating the number of data for burst transfer. Any number of data from “1” to “16” is encoded into 4 bits.

The burst size ARSIZE [2: 0] is a 3-bit signal indicating the transfer size at each burst transfer. Any transfer size of “2 ⁰ ”, “2 ¹ ”, “2 ² ”, “2 ³ ”, “2 ⁴ ”, “2 ⁵ ”, “2 ⁶ ”, “2 ⁷ ” is encoded to 3 bits Shown.

  The burst type ARBURST [1: 0] is a 2-bit signal indicating the type of burst transfer address calculation. Specifically, any one of FIFO type, continuous access, and cache line can be designated.

  The lock type ARLOCK [1: 0] is a 2-bit signal indicating information for atomic access. Specifically, any type of normal access, exclusive access, and locked access can be designated.

  The cache type ARCACHE [3: 0] is a 4-bit signal indicating information necessary for cache memory control. Specifically, control information such as whether cache is possible or not, whether write-through or write-back is shown.

  The protection type ARPROT [2: 0] is a 3-bit signal indicating information necessary for protection control. Specifically, each protection level of privileged access, non-secure access, and instruction access can be designated.

  The read address valid ARVALID is a valid signal indicating the validity of the address and control signal. The read address ready ARREADY is a ready signal indicating whether or not the slave 140 is ready to receive an address and a control signal. As described above, when both the read address valid ARVALID and the read address ready ARREADY are asserted, the address and the control signal are transferred.

  FIG. 3 is a diagram showing signals constituting the read data channel in the AXI protocol. The read data channel is a channel for transferring read data from the slave 140 to the master 110. The read data channel includes a read identifier tag, read data, read response, read last, read valid, and read ready signals. Of these signals, only read ready is a signal from the master 110, and other signals are signals from the slave 140.

  The read identifier tag RID [3: 0] is a 4-bit tag for identifying a read data group of a signal. The read identifier tag RID [3: 0] is generated in the slave, and must match the read address identifier ARID [3: 0] in the same transaction.

  Read data RDATA [31: 0] is read data from the slave 140 by a read transaction. Although a 32-bit read data bus is assumed here, the bit width of RDATA changes according to the read data bus width. The read data bus has a bit width of 8, 16, 32, 64, 128, 256, 512, or 1024.

  The read response RRESP [1: 0] is a 2-bit signal indicating the state of data transfer by the read transaction. For example, the read response includes a signal indicating success or failure of the read access.

  The read last RLAST is a signal indicating that the data is the final data transfer in the read transaction.

  The read valid RVALID is a valid signal indicating the validity of the requested read data. The read ready RREADY is a ready signal indicating whether or not the master 110 is ready to receive read data. As described above, read data is transferred when both the read valid RVALID and the read ready RREADY are asserted.

  FIG. 4 is a diagram showing signals constituting the write address channel in the AXI protocol. The write address channel is a channel for transmitting a write address from the master 110 to the slave 140. The write address channel includes a write address identifier, a write address, a burst length, a burst size, a burst type, a lock type, a cache type, a protection type, a write address valid signal, and a write address ready signal. Of these signals, only the write address ready is a signal from the slave 140, and the other signals are signals from the master 110.

  The write address identifier AWID [3: 0] is a 4-bit tag for identifying the write address group of the signal. The write address AWADDR [31: 0] is a 32-bit address to be written and is a signal indicating an initial address in burst transfer.

  The burst length AWLEN [3: 0] is a 4-bit signal indicating the number of data for burst transfer. The burst size AWSIZE [2: 0] is a 3-bit signal indicating the transfer size at each burst transfer. The burst type AWBURST [1: 0] is a 2-bit signal indicating the type of address calculation for burst transfer. The lock type AULOCK [1: 0] is a 2-bit signal indicating information for atomic access. The cache type AWCACHE [3: 0] is a 4-bit signal indicating information necessary for cache memory control. The protection type AWPROT [2: 0] is a 3-bit signal indicating information necessary for protection control. These are basically the same as in the case of the read address channel.

  The write address valid AWVALID is a valid signal indicating the validity of the address and control signal. The write address ready AWREADY is a ready signal indicating whether or not the slave 140 is ready to receive an address and a control signal. As described above, when the write address valid AWVALID and the write address ready AWREADY are both asserted, the address and the control signal are transferred.

  FIG. 5 is a diagram showing signals constituting the write data channel in the AXI protocol. The write data channel is a channel for transferring write data from the master 110 to the slave 140. The write data channel includes a write identifier tag, write data, write strobe, write last, write valid, and write ready signals. Of these signals, only the write ready is a signal from the slave 140, and the other signals are signals from the master 110.

  The write identifier tag WID [3: 0] is a 4-bit tag for identifying the write data group of the signal. This write identifier tag WID [3: 0] must match the write address identifier AWID [3: 0] in the same transaction.

  Write data WDATA [31: 0] is write data to the slave 140 by a write transaction. Although a 32-bit write data bus is assumed here, the bit width of WDATA changes according to the read data bus width. The write data bus has a bit width of 8, 16, 32, 64, 128, 256, 512, or 1024.

  Write strobe WSTRB [3: 0] is a 4-bit signal indicating the byte position to be updated in the memory of slave 140. One bit of the write strobe WSTRB [3: 0] is assigned for every 8 bits of the write data bus. That is, if the value of [3: 0] is i, WSTRB [i] corresponds to WDATA [(8 × i) +7: (8 × i)].

  The write last WLAST is a signal indicating that the data is the final data transfer in the write transaction.

  The write valid WVALID is a valid signal indicating the validity of the write data. The write ready WREADY is a ready signal indicating whether or not the slave 140 is ready to receive write data. As described above, the write data is transferred when both the write valid WVALID and the write ready WREADY are asserted.

  FIG. 6 is a diagram showing signals constituting a write response channel in the AXI protocol. The write response channel is a channel for transmitting the result of the write transaction from the slave 140 to the master 110. The write response channel is composed of response identifier, write response, write response valid, and response ready signals. Of these signals, only the response ready is a signal from the master 110, and the other signals are signals from the slave 140.

  The response identifier BID [3: 0] is a 4-bit tag for identifying the write response. This response identifier BID [3: 0] must match the write address identifier AWID [3: 0] in the same transaction.

  Write response BRESP [1: 0] is a 2-bit signal indicating the state of data transfer by a write transaction. For example, the write response includes a signal indicating success or failure of the write access.

  The write response valid BVALID is a valid signal indicating the validity of the write response. The response ready BREADY is a ready signal indicating whether or not the master 110 is ready to receive a write response. As described above, the write response is transmitted when both the write response valid BVALID and the response ready BREADY are asserted.

[Bus bridge configuration]
FIG. 7 is a block diagram showing a configuration example of the bus bridge 200 according to the first embodiment of the present invention. The bus bridge 200 includes an interconnecting unit 300, a FIFO memory group 400, a buffer 450, a transaction information writing unit 500, an entry number writing unit 550, an entry number reading unit 600, and a transaction information reading unit 650.

  The interconnection unit 300 transfers requests and responses between the master 110 and the slave 140. Specifically, when a request is received from the AXI bus 120 via the signal line 802, the interconnection unit 300 acquires a valid signal related to the request via the signal line 801, and receives a corresponding ready signal via the signal line 817. Get the signal. Hereinafter, the valid signal and the ready signal are referred to as a handshake signal. If the ready signal and valid signal relating to the request are asserted, the interconnecting unit 300 outputs the request to the transaction information writing unit 500 via the signal line 804. When the buffer full notification is received from the transaction information writing unit 500 via the signal line 806, the interconnection unit 300 negates the ready signal related to the request and outputs it to the AXI bus 120 via the signal line 801. Here, the buffer full notification is information indicating that data cannot be held in the buffer 450. If the buffer full notification is not received, the interconnection unit 300 transfers the request to the AXI bus 130 via the signal line 818.

  Further, when a response is received from the AXI bus 130 via the signal line 819, the interconnection unit 300 acquires a valid signal related to the response via the signal line 817, and sends a corresponding ready signal via the signal line 801. get. If the valid signal and the ready signal are asserted, interconnecting unit 300 outputs a response to entry number reading unit 600 and transaction information reading unit 650 via signal line 811. The interconnection unit 300 receives transaction information corresponding to the response from the transaction information reading unit 650 via the signal line 816. The transaction information is information for controlling response transfer processing. Details of the information included in the transaction information will be described later. The interconnection unit 300 transfers the response to the AXI bus 120 via the signal line 803 based on the received transaction information.

  The FIFO memory group 400 holds data by a first-in first-out method. The FIFO memory group 400 is provided with a FIFO memory for each transaction identifier ID. Each FIFO memory has one or more areas for holding data. Hereinafter, this area is referred to as a FIFO entry. The number of FIFO entries in each FIFO memory is equal to or greater than the maximum number of outstanding transactions allowed by the bus system. For example, when the maximum number of unresolved transactions allowed by the bus system is 16, each FIFO memory is provided with at least 16 FIFO entries. Each FIFO memory holds a buffer entry number as data. Here, the buffer entry is an area for holding data in the buffer 450, and the buffer entry number is a number for identifying the buffer entry.

  The buffer 450 holds transaction information. The buffer 450 comprises one or more buffer entries. The number of buffer entries provided in the buffer 450 is greater than or equal to the maximum number of outstanding transactions allowed by the bus system. For example, if the maximum number of outstanding transactions allowed by the bus system is 16, at least 16 buffer entries are provided. Each buffer entry is provided with a valid flag holding area and a transaction information holding area. The validity flag is held in the validity flag holding area. The valid flag is bit information indicating that the data held in the transaction information holding area of the buffer entry is valid. For example, “1” is set in the valid flag when the data is valid, and “0” is set when the data is invalid. Transaction information is held in the transaction information holding area.

  The transaction information writing unit 500 writes transaction information in the buffer 450. Specifically, when the transaction information writing unit 500 receives a request from the interconnection unit 300, the transaction information writing unit 500 refers to the valid flag of each buffer entry of the buffer 450 via the signal line 807. When all the valid flags are valid, the transaction information writing unit 500 issues a buffer full notification and outputs it to the interconnection unit 300. If any of the valid flags is invalid, the transaction information writing unit 500 selects one of the buffer entries for which the valid flag is invalid. The transaction information writing unit 500 generates transaction information based on the request and writes it in the selected buffer entry. The transaction information writing unit 500 validates the validity flag of the buffer entry in which the transaction information is written. The transaction information writing unit 500 outputs the selected buffer entry number and the transaction identifier ID related to the request to the entry number writing unit 550 via the signal line 808 and the signal line 809.

  The entry number writing unit 550 writes the buffer entry number selected by the transaction information writing unit 500 to the FIFO memory corresponding to the transaction identifier ID via the signal line 810.

  The entry number reading unit 600 reads the buffer entry number from the FIFO memory corresponding to the transaction identifier ID. Specifically, when the entry number reading unit 600 receives a response from the interconnection unit 300, the entry number reading unit 600 acquires a transaction identifier ID related to the response. The entry number reading unit 600 reads the buffer entry number from the FIFO memory corresponding to the acquired transaction identifier ID via the signal line 812. Entry number reading unit 600 outputs the read buffer entry number to transaction information reading unit 650 via signal line 813.

  The transaction information reading unit 650 reads transaction information from the buffer entry having the buffer entry number read by the entry number reading unit 600. Specifically, when the entry number reading unit 600 reads the buffer entry number, the transaction information reading unit 650 reads transaction information from the buffer entry of the buffer entry number via the signal line 814. Transaction information reading unit 650 outputs the read transaction information to interconnection unit 300 via signal line 816. When the response is the final data in the burst transfer or the write response, the transaction information reading unit 650 outputs information for invalidating the entry valid flag to the buffer 450 via the signal line 815. If the response is not the final data in the burst transfer, the transaction information reading unit 650 updates the transaction information in the entry. For example, the transaction information reading unit 650 counts up the burst count in the transaction information.

  The FIFO memory according to the above-described embodiment is an example of a first-in first-out memory described in the claims. The entry number writing unit of the above-described embodiment is an example of the region information writing unit described in the claims, and the entry number reading unit is an example of the region information reading unit described in the claims. is there. The buffer entry number in the above-described embodiment is an example of area information described in the claims.

  FIG. 8 is a block diagram illustrating a configuration example of the interconnecting unit 300 according to the first embodiment of the present invention. Interconnect 300 includes conversion information generators 310 and 330.

  The conversion information generator 310 converts the request received from the AXI bus 120 as necessary based on the specifications of the AXI bus 130. Specifically, when the conversion information generator 310 receives a request from the AXI bus 120, the conversion information generator 310 acquires a handshake signal related to the request. If the valid signal and ready signal related to the request are asserted, the conversion information generator 310 outputs the request to the transaction information writing unit 500. When receiving the buffer full notification from the transaction information writing unit 500, the conversion information generator 310 negates the ready signal and outputs it to the AXI bus 120. If the buffer information notification is not received from the transaction information writing unit 500, the conversion information generator 310 converts the request as necessary and outputs the request to the AXI bus 130.

  The conversion information generator 330 converts the response received from the AXI bus 130 as necessary based on the specifications of the AXI bus 120 and transaction information. Specifically, when receiving a response from the AXI bus 130, the conversion information generator 330 acquires a ready signal and a valid signal related to the response. If the valid signal and ready signal related to the response are asserted, conversion information generator 330 outputs the response to entry number reading unit 600 and transaction information reading unit 650. Then, the conversion information generator 330 receives transaction information corresponding to the response from the transaction information reading unit 650. The conversion information generator 330 converts the response as necessary based on the transaction information and outputs the response to the AXI bus 120. For example, the conversion information generator 330 combines or divides the transfer data according to the burst transfer method indicated by the transaction information, the bus width of the transfer destination bus, or the like.

  FIG. 9 is a diagram illustrating a configuration example of the FIFO memory group 400 according to the first embodiment of the present invention. The FIFO memory group 400 is provided with a FIFO memory for each transaction identifier ID. For example, when the transaction identifier ID is 0 to 255, FIFO memories F [0] to [255] are provided corresponding to these identifiers.

  Each FIFO memory includes a data holding area 411, a write pointer holding area 412, and a full flag holding area 413.

  The data holding area 411 is provided with one or more areas (FIFO entries) for holding data. For example, if the maximum number of outstanding transactions allowed by the bus system is 16, at least 16 FIFO entries are provided.

  The write pointer holding area 412 is an area for holding a write pointer. The write pointer is information indicating an area in which data is to be written. An arrow in FIG. 10 indicates an area indicated by the write pointer. The initial value of the write pointer is set to 0. When the last data is held in the i-th FIFO entry from the top, a write pointer indicating the (i + 1) th from the top is set. However, when tail data is held in the tail FIFO entry, a write pointer indicating the tail FIFO entry is set.

  The full flag holding area 413 holds a full flag. The full flag is 1-bit information indicating that data cannot be held in the FIFO memory. For example, when data is held in the last FIFO entry, data “1” is set in the full flag, and when data is not held in the last FIFO entry, “0” is set in the full flag. When the full flag is “0”, it means that the data held in the FIFO entries after the FIFO entry indicated by the write pointer is invalid. It is assumed that the FIFO entry holding invalid data is in an empty state. Therefore, when the full flag is “1”, all data is in a valid state.

  The entry number writing unit 550 of the bus bridge 200 writes the buffer entry number in the area indicated by the write pointer in the FIFO memory corresponding to the transaction identifier ID in the FIFO memory group 400. When the write pointer of the FIFO memory is not the maximum value (for example, 15) at the time of writing, the entry number writing unit 550 increments the write pointer. When the write pointer of the FIFO memory is the maximum value at the time of writing, the entry number writing unit 550 sets “1” in the full flag.

  For example, when the buffer entry number 0 is written in the FIFO memory F [0], the buffer entry number 0 is held in the first FIFO entry, and the write pointer is updated from the initial value 0 to 1. Next, when the buffer entry number 1 is written in the FIFO memory F [0], the buffer entry number 1 is held in the second FIFO entry, and the write pointer is updated from the initial value 1 to 2.

  The entry number reading unit 600 of the bus bridge 200 reads the buffer entry number from the first FIFO entry in the FIFO memory corresponding to the transaction identifier ID in the FIFO memory group 400. When reading from the top is performed, the entry number reading unit 600 sequentially shifts data held in the second and subsequent FIFO entries from the top in the FIFO memory one by one toward the top. As a result, the data held in the first FIFO entry is deleted.

  Specifically, when the full flag is 1, the entry number reading unit 600 writes the data held in the second to last FIFO entries in the FIFO memory to the first to last FIFO entries. Then, the entry number reading unit 600 sets “0” in the full flag. On the other hand, when the full flag is 1, the entry number reading unit 600 sets the value of the write pointer to i, and stores the data held in the FIFO entries from the second to i-1 in the FIFO memory from the head to the i-th. Write to FIFO entry. After shifting each data in this way, the entry number reading unit 600 decrements the write pointer.

  For example, when data is read from the FIFO memory F [0] in which the buffer entry numbers 0 and 1 are written, the buffer entry number 0 is read from the first FIFO entry. Buffer entry number 1 held in the second FIFO entry is written into the first FOFO entry. The write pointer is updated from 2 to 1.

  FIG. 10 is a diagram illustrating an example of a valid flag and transaction information held in each buffer entry of the buffer 450 according to the first embodiment of this invention. The valid flag is held in the valid flag holding area 461, and the transaction information is held in the transaction information holding area 462. The transaction information includes, for example, a packing execution flag p, an address lower bit addr, a burst length len, a burst size size, a burst type btyp, and a burst count bcnt.

  The packing execution flag p is 1-bit information indicating whether or not to perform packing. Packing is a collection of burst target data based on bus specifications. Packing is executed, for example, when data from a bus having a bus width of 32 bits is transferred to a bus having a bus width of 64 bits. The address lower bit addr is 4-bit information for specifying the lower address of the access destination. The burst length len is 4-bit information indicating the number of burst transfer data. The burst size size is 3-bit information indicating the transfer size at each burst transfer. The burst type btyp is 2-bit information indicating the type of burst transfer address calculation. The burst count bcnt is 4-bit information indicating the number of burst transfers.

  FIG. 11 is a diagram illustrating a configuration example of the buffer 450 according to the first embodiment of the present invention. The buffer 450 comprises one or more entries. For example, when the maximum number of outstanding transactions allowed by the bus system is 16, at least 16 entries # 0 to 15 are provided. Each entry is provided with a valid flag holding area 461 and a transaction information holding area 462. The transaction information writing unit 500 and the transaction information reading unit 650 can randomly access the valid flag and transaction information stored in each entry in units of bits. The entry with the valid flag “0” is invalid because the transaction information is invalid. For example, when transaction information A, B, and C are held only in entries # 0, 1, and 15, the valid flags of those entries are set to “1”. “0” is set in the valid flags of the other entries, which are empty.

  FIG. 12 is a block diagram showing a configuration example of the transaction information writing unit 500 according to the first embodiment of the present invention. The transaction information writing unit 500 includes a buffer full determination unit 510, an entry number selection unit 520, and a transaction information generation unit 530.

  The buffer full determination unit 510 determines whether or not data can be held in the buffer 450. Specifically, when the buffer full determination unit 510 receives a request from the interconnection unit 300, the buffer full determination unit 510 refers to each valid flag in the buffer 450. If all the valid flags are valid, the buffer full determination unit 510 issues a buffer full notification and outputs it to the interconnection unit 300.

  The entry number selection unit 520 selects one of buffer entry numbers of vacant buffer entries. Specifically, the entry number selection unit 520 selects one of the buffer entry numbers of the buffer entries for which the valid flag is invalid. For example, the entry number selection unit 520 sets a fixed priority for each buffer entry, and selects the buffer entry number of the buffer entry with the highest priority. Alternatively, the entry number selection unit 520 selects the buffer entry number of the buffer entry that is least frequently used. The entry number selection unit 520 outputs the selected buffer entry number to the transaction information generation unit 530 and the entry number writing unit 550.

  The transaction information generation unit 530 generates transaction information based on the request and writes it in the buffer 450. Specifically, when receiving a request from the interconnecting unit 300, the transaction information generating unit 530 generates transaction information from the request. The transaction information generation unit 530 receives the buffer entry number from the entry number selection unit 520 and writes the transaction information in the buffer entry of the buffer entry number. Further, the transaction information generation unit 530 acquires the transaction identifier ID from the request and outputs it to the entry number writing unit 550.

  FIG. 13 is a diagram illustrating an example of the operation of the transaction information reading unit 650 according to the first embodiment of the present invention. When the response is not the final data in the burst transfer (for example, RLAST = 0), the transaction information reading unit 650 reads the transaction information from the buffer entry of the buffer entry number read by the entry number reading unit 600. Then, the transaction information reading unit 650 updates the burst count of the transaction information. When the response is the final data in the burst transfer (for example, RLAST = 1) or the write response, the transaction information reading unit 650 reads the transaction information from the buffer entry of the read buffer entry number. Then, the transaction information reading unit 650 invalidates the transaction information.

[Bus bridge operation]
Next, the operation of the bus bridge 200 will be described with reference to FIGS. FIG. 14 is a flowchart showing an example of the operation of the bus bridge 200 according to the first embodiment of the present invention. This operation starts when the bus bridge 200 is powered on or when the FIFO memory group 400 and the buffer 450 are initialized.

  The bus bridge 200 initializes each FIFO memory and the buffer 450 in the FIFO memory group 400 (step S905). The bus bridge 200 determines whether a request has been issued (step S910). If the request has been issued (step S910: Yes), the bus bridge 200 executes a transaction information writing process for writing the transaction information into the buffer 450 (step S920). The bus bridge 200 writes the buffer entry number in which the transaction information is written into the FIFO memory corresponding to the transaction identifier ID related to the request (step S930).

  When the request has not been issued (step S910: No), or after step S930, the bus bridge 200 determines whether a response is returned (step S935). If the response is returned (step S935: Yes), the bus bridge 200 reads the buffer entry number from the FIFO memory corresponding to the transaction identifier ID related to the response (step S940). The bus bridge 200 executes a transaction information reading process for reading transaction information from the buffer entry of the read buffer entry number (step S950). If no response is returned (step S935: No), or after step S950, the bus bridge 200 returns to step S910.

  FIG. 15 is a flowchart illustrating an example of the transaction information writing process according to the first embodiment of this invention. The transaction information writing unit 500 determines whether or not there is an empty entry with the valid flag V = 0 in the buffer 450 (step S921). When there is no empty buffer entry (step S921: No), the transaction information writing unit 500 issues a buffer full notification (step S922). When there is an empty buffer entry (step S921: Yes), the transaction information writing unit 500 selects any empty (valid flag V = 0) buffer entry (step S923). The transaction information writing unit 500 generates transaction information based on the request and writes it in the selected buffer entry (step S924). The interconnection unit 300 transfers the request to the slave (step S925). After step S922 or S925, the bus bridge 200 ends the transaction information writing process.

  FIG. 16 is a flowchart showing an example of the transaction information read process according to the first embodiment of the present invention. The transaction information reading unit 650 reads transaction information from the buffer entry of the buffer entry number read by the entry number reading unit 600 (step S951). The transaction information reading unit 650 determines whether or not the response is the final data or write response in burst transfer (step S952).

  If it is the final data or write response (step S952: Yes), the transaction information reading unit 650 invalidates the transaction information in the buffer entry (step S953). When the response is not the final data and is not the write response (step S952: No), the transaction information reading unit 650 updates the burst count in the transaction information in the buffer entry (step S954). After step S953 or S954, the interconnection unit 300 transfers the response to the master based on the transaction information read by the transaction information reading unit 650 (step S955). After step S955, the bus bridge 200 ends the transaction information reading process.

  Next, an example of the operation result of the bus bridge 200 will be described with reference to FIGS. FIG. 17 is a diagram for explaining the operation of the bus bridge 200 when a request is issued according to the first embodiment of this invention. Assume a configuration in which the master 110 including the master # 1 is connected to the AXI bus 120 and the slave 140 including the slave # 2 is connected to the AXI bus 130. It is assumed that master # 1 issues twice a request in which transaction identifier ID is set to “0” to slave # 2. Further, it is assumed that the FIFO memory group 400 and the buffer 450 have been initialized before issuing a request. The bus bridge 200 transfers this request to the slave # 2.

  FIG. 18 is a diagram illustrating an example of the state of the buffer 450 after the request issuance according to the first embodiment of this invention. As illustrated in FIG. 17, when the request is issued twice, the transaction information writing unit 500 generates transaction information A and B based on these requests and writes them in the buffer entries # 0 and # 2. The valid flag of these buffer entries is set to “1”.

  FIG. 19 is a diagram illustrating an example of a state of the FIFO memory after a request is issued according to the first embodiment of this invention. Entry number writing unit 550 receives transaction identifier ID = 0 and buffer entry numbers 0 and 2 of the written buffer entry from transaction information writing unit 500. The entry number writing unit 550 writes the buffer entry numbers 0 and 2 in the first FIFO entry and the second FIFO entry based on the write pointer in the FIFO memory F [0] corresponding to the transaction identifier ID = 0. The write pointer is updated from the initial value 0 to 2.

  FIG. 20 is a diagram for explaining the operation of the bus bridge 200 when a response is returned according to the first embodiment of this invention. Slave # 2 returns a response in which transaction ID = 0 is set to master # 1. This response is assumed to be the final data (RLAST = 1) in the burst transfer.

  FIG. 21 is a diagram for explaining the operation of the bus bridge 200 when a response is returned according to the first embodiment of this invention. When the response is returned as illustrated in FIG. 19, the entry number reading unit 600 reads the buffer entry number 0 from the first FIFO entry of the FIFO memory F [0] corresponding to the transaction identifier ID = 0 of the response. . The buffer entry number 2 held in the second FIFO entry in the FIFO memory F [0] is shifted and written to the first FIFO entry. The write pointer is updated from 2 to 1.

  FIG. 22 is a diagram illustrating an example of the state of the buffer 450 after the response is returned according to the first embodiment of this invention. The transaction information reading unit 650 reads the transaction information A held in the buffer entry with the read buffer entry number 0. The valid flag of the buffer entry with the buffer entry number 0 is set to “0”.

  As described above, in the first embodiment of the present invention, when a request is issued, the transaction information writing unit 500 writes the transaction information in any buffer entry in the buffer 450. The entry number writing unit 550 writes the buffer entry number of the buffer entry in the FIFO memory corresponding to the transaction identifier ID. When the response is returned, the entry number reading unit 600 reads the buffer entry number from the FIFO memory corresponding to the transaction identifier ID. Thereby, the transaction information reading unit 650 can read the transaction information from the buffer entry of the buffer entry number.

  According to this configuration, it is only necessary to provide an area for holding the buffer entry number in each FIFO memory, so that the storage capacity of the FIFO memory is reduced as compared with the case where transaction information is held in the FIFO memory. That is, when increasing the maximum value of the number of transactions, it is only necessary to add a FIFO memory that holds the buffer entry number. Therefore, it is possible to suppress an increase in storage capacity compared to the case of adding a FIFO memory that holds transaction information. it can.

  Note that the bus system of the first embodiment uses the AXI protocol, but a protocol other than the AXI protocol may be used as long as it is a protocol that allows split transactions.

  Further, the present invention can be applied to an interconnect other than a bus bridge as long as it is an interconnect that allows split transactions.

  1 illustrates the configuration in which the master 110 is connected to the AXI bus 120 and the slave 140 is connected to the AXI bus 130, the connection form of the modules is not limited to the configuration illustrated in FIG. For example, a slave may be connected to the AXI bus 120 in addition to the master, or a master may be connected to the AXI bus 130 in addition to the slave.

  Further, although transaction information is illustrated in FIG. 8, if it is information necessary for response transfer control, the buffer 450 may hold information different from the information illustrated in FIG. 8 as transaction information.

  10 illustrates a configuration in which a write pointer and a full flag are provided for each FIFO memory. However, the FIFO memory is not limited to the configuration illustrated in FIG. 10 as long as data is held by a first-in first-out method. For example, it may be a FIFO memory that uses a ring buffer.

<2. Second Embodiment>
[Bus bridge configuration]
Next, a second embodiment of the present invention will be described with reference to FIGS. The bus bridge 201 according to the second embodiment is different from the bus bridge 200 according to the first embodiment in that a FIFO memory is provided for each group identifier instead of a FIFO memory for each transaction identifier ID. The group identifier is an identifier for identifying the group to which the transaction belongs. For example, when the transaction identifier ID is 7 bits, gID which is the upper 5 bits is used as the group identifier.

  The bus bridge 201 includes an interconnecting unit 301, a FIFO memory group 401, a buffer 451, a management information writing unit 501, an entry number writing unit 551, an entry number reading unit 601, and a management information reading unit 651.

  The configuration of the interconnection unit 301 is the same as that of the interconnection unit 300 of the first embodiment, except that the transaction identifier is received and the transaction identifier received in the request and response is set. Specifically, the interconnection unit 301 further receives a transaction identifier ID ′ from the management information writing unit 501 via the signal line 821 when a request is issued. This transaction identifier ID ′ is obtained by setting a predetermined value (for example, a value of “0” in decimal notation) in a bit string other than the group identifier in the transaction identifier ID related to the request. For example, when the upper 5 bits of a 7-bit transaction identifier ID are used as a group identifier, the transaction identifier ID ′ is a value in which the value of “00” is set in the lower 2 bits in binary notation. The interconnection unit 301 sets the transaction identifier ID ′ as a request and transfers it to the slave 140.

  Further, when a response is returned, the interconnection unit 301 further receives a transaction identifier ID from the management information reading unit 651 via the signal line 825. The interconnection unit 301 sets the transaction identifier ID as a response and transfers it to the master 110. As described above, when the transaction identifier ID ′ is set in the request, the transaction identifier ID ′ is similarly set by the slave 140 in the response corresponding to the request. By replacing the transaction identifier ID ′ related to the response with the original transaction identifier ID, the master unit 110 can receive a response corresponding to the request issued by itself.

  The FIFO memory group 401 is provided with a FIFO memory for each group identifier gID. The configuration of each FIFO memory is the same as the configuration of the FIFO memory of the first embodiment.

  The configuration of the buffer 451 is the same as the configuration of the buffer 450 of the first embodiment except that management information is held instead of transaction information. The management information is information including a partial bit string id, which is a bit string obtained by removing gID from the transaction identifier ID, and transaction information.

  The configuration of the management information writing unit 501 is the same as the configuration of the transaction information writing unit 500 of the first embodiment, except that management information is written in the buffer 451 instead of the transaction information. Specifically, when the management information writing unit 501 receives a request from the interconnection unit 301, the management information writing unit 501 acquires gID, which is a high-order bit string of the transaction identifier ID related to the request, as a group identifier. The management information writing unit 501 outputs an identifier ID ′ in which a bit string other than the group identifier is fixed to a predetermined value in the transaction identifier ID to the interconnection unit 301. Hereinafter, such replacement of the transaction identifier is referred to as “rename”. Then, the management information writing unit 501 acquires a partial bit string id obtained by removing gID from the transaction identifier ID. The management information writing unit 501 writes the partial bit string id and transaction information in the buffer 450 as management information. The partial bit string id is output via the signal line 822. Also, the management information writing unit 501 outputs the group identifier gID to the entry number writing unit 551 via the signal line 823 instead of the transaction identifier ID.

  The entry number writing unit 551 writes a buffer entry number in the FIFO memory corresponding to the group identifier gID.

  The entry number reading unit 601 reads the buffer entry number from the FIFO memory corresponding to the group identifier gID related to the response.

  The configuration of the management information reading unit 651 is the same as the configuration of the transaction information reading unit 650 of the first embodiment, except that management information is read from the buffer 451 instead of the transaction information. Specifically, when the response is received from the interconnection unit 301, the management information reading unit 651 reads the management information from the buffer entry of the buffer entry number read by the entry number reading unit 601. The partial bit string id in the management information is read through the signal line 824. The management information reading unit 651 generates a transaction identifier ID by replacing (that is, renaming) a bit string other than the group identifier gID in the transaction identifier ID ′ related to the response with the read partial bit string id. The management information reading unit 651 outputs the generated transaction identifier ID to the interconnection unit 301 via the signal line 825.

  FIG. 24 is a diagram illustrating a configuration example of the FIFO memory group 401 according to the second embodiment of the present invention. The FIFO memory group 401 is provided with a FIFO memory for each group identifier gID. For example, when the group identifier gID is the upper 5 bits of the transaction identifier, 64 FIFO memories F [0] to [63] are provided.

  FIG. 25 is a diagram illustrating an example of a valid flag and management information according to the second embodiment of this invention. Each buffer entry is provided with a valid flag holding area 461 and a management information holding area 463. The validity flag held in the validity flag holding area 461 indicates whether the management information is valid. The management information holding area 463 is an area for holding management information. The management information includes a partial bit string id and transaction information.

  FIG. 26 is a diagram illustrating a configuration example of the buffer 451 according to the second embodiment of the present invention. The management information in the buffer entry whose valid flag is “0” is invalidated, and the management information in the buffer entry whose valid flag is “1” is invalidated. For example, when management information is held only in buffer entries # 0, 1, and 15, the validity flags of those buffer entries are set to “1”, and the validity flags of other buffer entries are set to “0”. Is done.

  FIG. 27 is a flowchart showing an example of the operation of the bus bridge 201 in the second exemplary embodiment of the present invention. This operation is the same as the operation of the bus bridge 200 of the first exemplary embodiment except that steps S960, S931, S941, and S970 are executed instead of steps S920, S930, S940, and S950. .

  When the request is issued (step S910: Yes), the bus bridge 201 executes a management information writing process for writing the management information to any of the buffer entries (step S960). The bus bridge 201 writes the buffer entry number of the buffer entry in which the management information is written into the FIFO memory corresponding to the gID related to the request (step S931).

  When the response is returned (step S935: Yes), the bus bridge 201 reads the buffer entry number from the FIFO memory corresponding to the gID related to the request (step S941). The bus bridge 201 executes management information read processing for reading management information from the buffer entry indicated by the buffer entry number (step S970).

  FIG. 28 is a block diagram illustrating a configuration example of the management information writing process according to the second embodiment of the present invention. This management information writing process is the same as the transaction information writing process in the first embodiment except that steps S961 and S962 are executed instead of step S924.

  The management information writing unit 501 selects one of the empty buffer entries with the valid flag V = 0 (step S923), and writes the management information to the buffer entry (step S961). The management information writing unit 501 renames the transaction identifier ID related to the request to the transaction identifier ID ′. The transaction identifier ID ′ is, for example, a bit string (for example, lower 2 bits) obtained by removing gID from the transaction identifier ID and fixed to a predetermined value (for example, “00” in binary notation) (step S962).

  FIG. 29 is a flowchart showing an example of management information reading processing according to the second embodiment of the present invention. This management information reading process is the same as the transaction information reading process in the first embodiment except that steps S971, S972, and S973 are executed instead of steps S951 and S953.

  The management information reading unit 651 reads management information from the buffer entry having the buffer entry number read by the entry number reading unit 601 (step S971).

  When the response is final data or a write response (step S952), the management information reading unit 651 invalidates the management information in the buffer entry (step S972). After step S972 or S954, the management information reading unit 651 renames the transaction ID ′ related to the response to the ID (step S973).

  As described above, in the second embodiment of the present invention, when a request is issued, the management information writing unit 501 writes the management information in any buffer entry in the buffer 451. The entry number writing unit 551 writes the buffer entry number of the buffer entry in the FIFO memory corresponding to the group identifier gID. When the response is returned, the entry number reading unit 601 reads the buffer entry number from the FIFO memory corresponding to the group identifier gID. Thereby, the management information reading unit 651 can read the management information from the buffer entry of the buffer entry number.

  According to this configuration, since the FIFO memory is provided for each group, the total storage capacity of the FIFO memory is further reduced as compared with the case where the FIFO memory is provided for each transaction identifier.

  Further, the management information writing unit 501 removes the partial bit string id from the transaction identifier ID related to the request. For this reason, the slave 140 receives a request in which the group identifier gID from which the partial bit string id is removed is set. As a result, a plurality of different transaction identifier IDs are replaced with the group identifier gID having the same value. As described above, in the AXI bus protocol, the order is guaranteed between transactions having the same transaction identifier. Therefore, each response to which the same group identifier is assigned by the replacement with the group identifier is returned in the order in which the requests are issued. Therefore, even if the storage capacity of the FIFO memory is reduced, the order is maintained.

  Furthermore, the management information reading unit 651 generates a transaction identifier ID from the partial bit string id and the group identifier gID. Therefore, the master 110 can receive a response corresponding to the request issued by itself.

  Although the group identifier is the upper 5 bits of the transaction identifier, the group identifier is not limited to the upper 5 bits as long as it is a partial bit string of the transaction identifier.

<3. Third Embodiment>
[Bus bridge configuration]
Next, a third embodiment of the present invention will be described with reference to FIGS. The bus bridge 202 of the third embodiment is different from the bus bridge 200 of the first embodiment in that an overflow FIFO memory is further provided by reducing the number of FIFO entries in the FIFO memory. Specifically, the bus bridge 202 replaces the FIFO memory group 400, the entry number writing unit 550, and the entry number reading unit 600 with the FIFO memory group 402, the entry number writing unit 552, and the entry number reading. Part 602.

  The FIFO memory group 402 is provided with a FIFO memory for each transaction identifier ID. The configuration of each FIFO memory is the same as that of the FIFO memory of the first embodiment. However, the number of FIFO entries in each FIFO memory in the FIFO memory group 402 is smaller than the number of FIFO entries in the FIFO memory according to the first embodiment. Specifically, the number of FIFO entries in each FIFO memory is a number that is half or more of the maximum number of unresolved transactions. For example, when the maximum number of unresolved transactions is 16, the number of FIFO entries in the FIFO memory is at least 8. In order to minimize the storage capacity of each FIFO memory, the number of FIFO entries in the FIFO memory is preferably half of the maximum number of unresolved transactions.

  If the number of FIFO entries in each FIFO memory is less than half the maximum value of the number of unresolved transactions, a state in which data overflowing from two or more FIFO memories is held in the overflow FIFO memory may occur. For example, if the maximum number of unresolved transactions is 16 and the number of FIFO entries in each FIFO memory is 7, 8 buffer entry numbers related to unresolved transactions may be written in two FIFO memories. . In this case, data overflowing from each of these FIFO memories is held in the overflow FIFO memory. However, the overflow FIFO does not hold the transaction identifier ID corresponding to the FIFO memory. This makes it impossible for the entry number reading unit 602 to determine which FIFO memory the stored data is overflowing from. On the other hand, if the number of FIFO entries in each FIFO memory is set to more than half of the maximum number of unresolved transactions, data overflowing from two or more FIFO memories is not held in the overflow FIFO memory. Therefore, even if there are a plurality of FIFO memories, only one overflow FIFO memory is required.

  The FIFO memory group 402 is provided with an overflow FIFO memory. The overflow FIFO memory holds data overflowed from the FIFO memory provided for each transaction identifier. The number of FIFO entries in the overflow FIFO memory is the difference between the maximum number of unresolved transactions and the number of FIFO entries in the FIFO memory. For example, when the maximum number of unresolved transactions is 16 and the number of FIFO entries in the FIFO memory is 8, the number of FIFO entries in the overflow FIFO memory is 8. This overflow FIFO is provided with an area for holding an empty flag indicating that data is not held in the overflow FIFO. For example, “1” is set in the empty flag when data is not held in the overflow FIFO, and “0” is set when one or more data is held.

  The configuration of the entry number writing unit 552 is the same as that of the entry number writing unit 550 of the first embodiment except that data is written to the overflow FIFO memory when data overflows from the FIFO memory. Specifically, if the FIFO full flag corresponding to the transaction identifier ID is “1”, the entry number writing unit 552 writes the buffer entry number in the overflow FIFO memory.

  The configuration of the entry number reading unit 602 is the same as that of the entry number reading unit 600 of the first embodiment except that the buffer entry number is read from the FIFO or overflow FIFO. Specifically, when the FIFO full flag corresponding to the transaction identifier ID is “1” and the empty flag is “0”, the buffer entry number is read from the entry number reading unit 602 overflow FIFO. When the full flag of the FIFO corresponding to the transaction identifier ID is “0” or the empty flag is “1”, the buffer entry number is read from the FIFO corresponding to the transaction identifier ID.

  FIG. 31 is a diagram showing a configuration example of the FIFO memory group 402 in the third embodiment of the present invention. The FIFO memory group 402 is provided with a FIFO memory for each transaction identifier. In addition, an overflow FIFO memory OvF1 is provided.

  The overflow FIFO memory OvF1 includes a data holding area 421, a tail pointer holding area 422, and an empty flag holding area 423. The data holding area 421 is the same as the data holding area 411 of the FIFO memory for each transaction. The tail pointer holding area 422 is an area for holding the tail pointer. The tail pointer is information indicating a FIFO entry in which tail data is held. The empty flag holding area 423 holds an empty flag.

  If the empty flag is “1” at the time of writing, the entry number writing unit 552 sets “0” to the empty flag and writes the buffer entry number in the first FIFO entry. When the empty flag is “0” at the time of writing, the entry number writing unit 552 writes the buffer entry number to the FIFO entry immediately before the tail pointer, and increments the tail pointer.

  The entry number reading unit 602 reads the buffer entry number from the first FIFO entry in the overflow FIFO. The entry number reading unit 602 shifts each data held in the second and subsequent FIFO entries in the FIFO memory one by one to the head. If the tail pointer is not the minimum value at the time of reading, the entry number reading unit 602 decrements the tail pointer. When the end pointer is the minimum value at the time of reading, the entry number reading unit 602 sets “1” in the empty flag.

  The overflow FIFO memory OvF1 described above is an example of an overflow first-in first-out memory described in the claims.

[Bus bridge operation]
Next, the operation of the bus bridge 202 will be described with reference to FIGS. This operation is the same as the operation of the bus bridge 200 of the first embodiment except that steps S980 and S990 are executed instead of steps S930 and S940.

  When the request is issued (step S910: Yes), the bus bridge 202 executes transaction information writing processing (step S920), and executes entry number writing processing for writing the buffer entry number into the FIFO memory (step S920). Step S980).

  When the response is returned (step S935: Yes), the bus bridge 202 executes entry number write processing for reading the buffer entry number from the FIFO memory (step S990), and executes transaction information read processing (step S990). S950).

  FIG. 33 is a flowchart showing an example of entry number writing processing according to the third embodiment of the present invention. The entry number writing unit 552 determines whether or not the FIFO memory full flag corresponding to the transaction identifier ID is “0” (step S981). When the full flag is “0” (step S981: Yes), the entry number writing unit 552 writes the buffer entry number in the FIFO memory (step S982). The entry number writing unit 552 refers to the write pointer and determines whether or not the FIFO memory is full (step S983). If it is full (step S983: Yes), the entry number writing unit 552 sets the full flag of the FIFO memory to “1” (step S984).

  When the full flag of the FIFO memory corresponding to the transaction identifier ID is “1” (step S981: No), the entry number writing unit 552 determines whether the empty flag of the overflow FIFO memory is “1”. (Step S985). If the empty flag is “1” (step S985: Yes), the entry number writing unit 552 sets “0” to the empty flag (step S986). When the empty flag is “0” (step S985: No) or after step S986, the entry number writing unit 552 writes the buffer entry number in the overflow FIFO memory (step S987).

  If the FIFO memory corresponding to the transaction identifier ID is not full (step S983: No), or after step S984 or step S987, the entry number writing unit 552 ends the entry number writing process.

  FIG. 34 is a flowchart showing an example of entry number reading processing in the third embodiment of the present invention. The entry number reading unit 602 determines whether the full flag of the FIFO memory corresponding to the transaction identifier ID is “0” (step S991). If the full flag is “0” (step S991: Yes), the entry number reading unit 602 reads the buffer entry number from the FIFO memory (step S992).

  When the full flag is “1” (step S991: No), the entry number reading unit 602 determines whether the empty flag of the overflow FIFO memory is “0” (step S993). When the empty flag is “1” (step S993: No), the entry number reading unit 602 reads the buffer entry number from the FIFO memory corresponding to the transaction identifier ID (step S994). Then, the entry number reading unit 602 sets “0” to the full flag of the FIFO memory (step S995).

  If the empty flag is “0” (step S993: Yes), the entry number reading unit 602 reads the buffer entry number from the overflow FIFO memory (step S996). The entry number reading unit 602 refers to the end pointer and determines whether or not the overflow FIFO memory has become empty (step S997). If the overflow FIFO memory has become empty (step S997: Yes), the entry number reading unit 602 sets the empty flag to “1” (step S998).

  If the overflow FIFO memory is not emptied (step S997: No), or after steps S992, S995, or S998, the entry number reading unit 602 ends the entry number reading process.

  As described above, according to the third embodiment of the present invention, the bus bridge 202 further reduces the storage capacity of the FIFO memory by holding the data in the overflow FIFO memory when the data overflows from the FIFO memory. be able to. Specifically, the number of FIFO entries in each FIFO memory can be reduced by the number of FIFO entries in the overflow FIFO memory.

  In addition, since the bus bridge 202 sets a full flag in each FIFO memory, it is possible to easily determine whether or not data overflows from the FIFO memory by referring to the full flag.

  Since the bus bridge 202 sets an empty flag in the overflow FIFO memory, it is easy to determine whether or not the buffer entry number related to the response is held in the overflow FIFO memory by referring to the empty flag. be able to.

  Furthermore, the number of FIFO entries in the FIFO memory is at least half of the maximum value of the maximum number of unresolved transactions. For this reason, data overflowing from two or more FIFO memories is not held in the overflow FIFO memory. Therefore, even if there are a plurality of FIFO memories, only one overflow FIFO memory is required.

  The embodiment of the present invention shows an example for embodying the present invention. As clearly shown in the embodiment of the present invention, the matters in the embodiment of the present invention and the claims Each invention-specific matter in the scope has a corresponding relationship. Similarly, the matters specifying the invention in the claims and the matters in the embodiment of the present invention having the same names as the claims have a corresponding relationship. However, the present invention is not limited to the embodiments, and can be embodied by making various modifications to the embodiments without departing from the gist of the present invention.

110 Master 120, 130 AXI bus 140 Slave 200, 201, 202 Bus bridge 300, 301 Interconnection unit 310, 330 Conversion information generator 400, 401, 402 FIFO memory group 411, 421 Data holding area 412 Write pointer holding area 413 Full flag Holding area 422 Trailing pointer holding area 423 Empty flag holding area 450, 451 Buffer 461 Valid flag holding area 462 Transaction information holding area 463 Management information holding area 500 Transaction information writing section 501 Management information writing section 510 Buffer full judgment section 520 entry Number selection unit 530 Transaction information generation unit 550, 551, 552 Entry number writing unit 600, 601, 602 Entry number reading unit 650 Transaction Down information reading section 651 management information reading unit

Claims (7)

A plurality of first-in first-out memories provided for each transaction identifier with respect to a transaction identifier that is an identifier for identifying a transaction process including a request transfer process and a response transfer process corresponding to the request;
A buffer comprising a plurality of transaction information writing areas for writing transaction information, which is information for controlling the response transfer process;
A transaction information writing unit that writes the transaction information to one of the transaction information writing areas based on the request each time the request is issued;
An area information writing unit for writing area information indicating the transaction information writing area in which the transaction information is written to the first-in first-out memory corresponding to the transaction identifier related to the request each time the transaction information is written;
An area information reading unit that reads the area information from the first-in first-out memory corresponding to the transaction identifier related to the response each time the response is returned;
A transaction information reading unit that reads the transaction information from the transaction information writing area indicated by the area information each time the area information is read;
The request is transferred to the slave when the request is issued from the master, and the response is transferred to the master based on the transaction information read when the response is returned from the slave. An interconnection device comprising a connection unit. An overflow first-in first-out memory holding the area information overflowing from the plurality of first-in first-out memories;
The region information writing unit writes the region information to the first-in first-out memory when the region information does not overflow from the first-in first-out memory related to the request, and the region information writing unit Write the area information into the overflow first-in first-out memory,
The area information reading unit reads the area information from the overflow first in first out memory when the area information related to the response is written in the overflow first in first out memory, and the area information is not written in the overflow first in first out memory. 2. The interconnection device according to claim 1, wherein the area information is read from the first-in first-out memory. A full flag indicating that the first-in first-out memory cannot hold the area information is further provided for each first-in first-out memory;
3. The interconnection apparatus according to claim 2, wherein the area information writing unit determines whether or not the area information overflows from the first-in first-out memory based on the full flag. An empty flag indicating that the overflow first-in first-out memory is empty;
The interconnection apparatus according to claim 2, wherein the area information reading unit determines whether or not the area information is written in the overflow first-in first-out memory based on the empty flag. The first-in first-out memory and the overflow first-in first-out memory include one or more entries that are areas for holding the area information,
The number of entries in the first-in first-out memory is more than half of the maximum number of unresolved transaction processes,
The interconnection apparatus according to claim 2, wherein the number of entries in the overflow first-in first-out memory is a difference between the maximum value and the number of entries in the first-in first-out memory. A plurality of first-in first-out memories provided for each group identifier with respect to a group identifier that is an identifier for identifying a group to which a transaction process including a request transfer process and a response transfer process corresponding to the request belongs;
A plurality of management information for writing, as management information, transaction information which is information for controlling the transfer process of the response and a partial bit string which is information obtained by removing the group identifier from the transaction identifier for identifying the transaction process A buffer with a writing area;
A management information writing unit that writes the management information to any of the transaction information writing areas based on the request each time the request is issued;
An area information writing unit for writing area information indicating the transaction information writing area in which the management information is written to the first-in first-out memory corresponding to the group identifier related to the request each time the management information is written;
An area information reading unit that reads the area information from the first-in first-out memory corresponding to the group identifier related to the response each time the response is returned;
A transaction information reading unit that reads the transaction information from the transaction information writing area indicated by the area information each time the area information is read;
The request is transferred to the slave when the request is issued from the master, and the response is transferred to the master based on the transaction information read when the response is returned from the slave. An interconnection device comprising a connection unit. The management information writing unit
A management information write processing unit that writes the management information in any of the transaction information write areas based on the request; a first identifier processing unit that removes the partial bit string from the transaction identifier in the request;
With
The management information reading unit
A management information read processing unit that reads the transaction information from the transaction information writing area indicated by the area information;
The interconnection apparatus according to claim 6, further comprising: a second identifier processing unit that generates the transaction identifier from the partial bit string and the group identifier included in the management information read in the response.

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