JPH08235232A - Method and device for verificating layout - Google Patents

Abstract

PURPOSE: To verify a masking pattern for correcting a pseudo design rule error by outputting a rectangle before being divided by a cut line which generates a spacing error and the position of the rectangle. CONSTITUTION: The masking pattern constituted of the rectangles is constituted of the wirings LH1-LH3 and LV2 of a first wiring layer, the wirings LV1 and LV3 of a second wiring layer and the contacts VIA1 and VIA2 of the first wiring layer and the second wiring layer. The cut lines or slits for dividing the rectangle along the horizontal or vertical direction of the rectangle extended for minimum spacing or all the rectangles for which a spacing rule is defined are set in a masking layout constituted of the rectangles. Then, whether or not a distance between the adjacent rectangles present between the adjacent cut lines keeps a design rule is checked. Then, the rectangle before being divided by the cut line which generates the spacing error and the position of the rectangle are outputted.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to verification and correction of a design rule error of a mask pattern composed of a rectangle such as a semiconductor VLSI.

[0002]

2. Description of the Related Art As a method for verifying and correcting a design rule error of a mask pattern composed of a rectangle such as a semiconductor VLSI, the shortest distance between two rectangles is checked, and a notch or a slit is formed between two rectangles of equal potential. If a pseudo design rule error has occurred, there was a method of filling the area in which the pseudo design rule error occurred with a rectangle of the same wiring layer (Reference: IPSJ 36th National Convention “Layout verification in automatic layout system”). Method ”3Y-11 P2027-2028).

[0003]

In the prior art, since the design rule error is determined by the shortest distance between the two rectangles, the verification of the design rule error and the notch or slit can be performed very quickly and efficiently. You can fix the pseudo design rule error called.

However, as shown in FIG. 4, VIA1 and LV
The area Area2 in which the pseudo design rule error has occurred between the two areas is automatically or manually VI as shown in FIG.
Two rectangles VIA even after the pseudo design rule error is filled in by filling the rectangle R1 of the same potential as A1 and LV2 in the same layer
Since the design rule error is determined by the shortest distance between 1 and LV2, R1 is not considered and VIA1 and LV are always considered.
It is determined that a pseudo design rule error has occurred between the two.

In view of the above problems, it is an object of the present invention to enable correction of a pseudo design rule error and verification of a mask pattern in which the pseudo design rule error is corrected.

[0006]

SUMMARY OF THE INVENTION The present invention is a mask layout composed of rectangles such as VLSI, in which all rectangles (or rectangles extended by a minimum spacing) for which a spacing rule is defined are horizontal (or Setting a cut line (slit) that divides the rectangle along the (vertical) direction, checking whether the distance between adjacent rectangles existing between adjacent cut lines observes the design rule, and spacing. Is making an error,
Correct the minimum spacing error by outputting the rectangle and the position of the rectangle before being divided by the cut line and filling the area where the minimum spacing error occurs between the rectangles of the same wiring layer with the same potential with the rectangle. And a step of storing the area where the error is corrected, expanding the area by a minimum spacing, and extracting a rectangle of the expanded area.

[0007]

Operation: In a mask layout consisting of rectangles, set cut lines or slits that divide the rectangles along the horizontal or vertical direction of all rectangles with spacing rules defined or rectangles expanded by the minimum spacing. , Check whether the distance between the adjacent rectangles existing between the adjacent cut lines complies with the design rule, and output the spacing error-caused rectangle and the position of the rectangle before division. , The minimum spacing error is corrected by filling the area where the minimum spacing error occurs between the rectangles of the same wiring layer at the same potential with the rectangle, and the area where the error is corrected is stored, and the above-mentioned area is reduced to the minimum spacing. Only, and the rectangle of the expanded area is extracted.

As a result, it becomes possible to correct the pseudo design rule error and verify the mask pattern in which the pseudo design rule error has been corrected.

[0009]

Embodiments of the present invention will be described below with reference to the drawings.

(Embodiment 1) The layout verification method of the first embodiment will be described with reference to the flow chart shown in FIG. 1 by taking the mask pattern composed of rectangles shown in FIG. 2 as an example.

It is assumed that each rectangle shown in FIG. 2 has information on the coordinate values of the lower left end point and the upper right end point, the wiring layer, and the net number (the rectangles having the same potential have the same net number). . LH1 to LH3 and LV2 are wirings in the first wiring layer, LV1 and LV3 are wirings in the second wiring layer, and VIA1 and VA.
IA2 is a contact between the first wiring layer and the second wiring layer.
LH1, LH2, LV1, LV2, and VIA1 are net 1
And LH3, LV3, and VIA2 form a net 2. Each of VIA1 and VIA2 is composed of a rectangle of the first wiring layer and a rectangle of the second wiring layer and a contact window for connecting them. It is assumed that the design rule is individually defined for each of the first wiring layer, the second wiring layer, and the wiring layer of the contact window. The minimum spacing of the first wiring layer is LM1, the wiring width of the first wiring layer is W1, and VIA1
The rectangle of the first wiring layer is WV1 both vertically and horizontally.

This embodiment will be described by taking the first wiring layer as an example among the mask patterns shown in FIG. Data input step 1
1 reads the mask pattern and design rule.

Next, in a mask pattern classification step 12,
Mask pattern data files for the first wiring layer, the second wiring layer, and the contact window, in which rectangles of the first wiring layer, the second wiring layer, and the contact window are extracted and sorted by the coordinate value of the lower left corner of each rectangle. For all mask pattern data of each mask pattern data file in which design rules are defined, design rule error determination step 14, pseudo design rule error determination and end condition determination step 15, pseudo design rule error correction step 16, The step 17 for rechecking the corrected portion of the pseudo design rule error is executed.

Taking the rectangle of the first wiring layer as an example, the above 14, 15,
The processing of each of steps 16 and 17 will be described. The rectangle shown in FIG. 3 is a part of the mask pattern of the first wiring layer, and a portion between the rectangle of the first wiring layer of VIA1 (hereinafter referred to as VIA1) and LV2 causes a pseudo design rule error called a notch. It is an enlarged version.

Design rule error search step 13
Then, the mask pattern data file of the first wiring layer is called, and the processing is performed in order from the lower left rectangle.

As shown in FIG. 3, VIA1 is enlarged by the minimum spacing LM1 of the first wiring layer to form Area1.
Since Area1 is VIA1 enlarged by the minimum spacing of the first wiring layer, it is determined that the rectangle overlapping Area1 may be a design rule error.

At the design rule determination step 14, LH
Since 1, LH2, LV2, and VIA1 are rectangles of the same potential forming the net 1, it is determined that no design rule error has occurred, and this information is sent to the pseudo design rule error determination and end condition determination step 15. If there is a design rule error, the rectangle information (coordinate value, wiring layer, net number, etc.) causing the design rule error is sent to and stored in the pseudo design rule error determination and end condition determination step 15.

Next, in the pseudo design rule error judgment and end condition judgment step 15, the pseudo design rule error judgment, the processing end condition judgment and the design rule error holding are carried out.

The processing end condition is that the pseudo design rule error determination is completed for all rectangles and the pseudo design rule error is eliminated. However, if the pseudo design rule error correction step 16 is performed even once and the same pseudo design rule error is not eliminated, it is determined as a design rule error, and the rectangular information (coordinate value, wiring layer) causing the design rule error is determined. , Net number, etc.). When the processing is completed, the held rectangular information (coordinate value, wiring layer, net number) causing the design rule error is sent to the data output step 18.

As shown in FIG. 3, rectangles that overlap Area1 are LH1, LH2, and LV2 are each VIA1, and it is determined whether a pseudo design rule error has occurred. Here, WE is the distance between VIA1 and LV2.

Since LH1 is connected to VIA1, no pseudo design rule error has occurred. LH2 is V
Since it is not directly connected to IA1, it is determined that LH2 and VIA1 have a pseudo design rule error. Similarly, LV2 and VIA1 are also determined to have a pseudo design rule error.

Next, in the pseudo design rule error correction step 16, as shown in FIGS. 4 and 5, the area Area2, which is the area in which the pseudo design rule error is generated, between VIA1 and LV2 is in the same layer as VIA1 and LV2. Fill with the potential rectangle R1.

Here, the coordinate values of the lower left corner and the lower right corner of R1 can be easily calculated from the coordinate values of the lower left corner and the upper right corner of VIA1 and LV2. The coordinates of the lower left corner of VIA1 are (x
1, y1) the coordinates of the upper right corner are (x2, y2), the coordinates of the lower left corner of LV2 are (x3, y3) the coordinates of the upper right corner are (x
4, y4), the coordinates of the lower left corner of R1 is (x2,
y1) The coordinates of the upper right end point are (x3, y4). The result of the pseudo design rule error correction step 16 is shown in FIG. 5 (in FIG. 5, the LH
1 and LH2 are omitted. ).

A pseudo design rule error correction file is created from the rectangle information in which the pseudo design rule error is corrected.

In the step 17 of re-verifying the corrected portion of the pseudo design rule error, the area Area3 obtained by expanding the area R1 in which the pseudo design rule error is generated as shown in FIG. 6 is expanded by the minimum spacing LM1 defined by the design rule. Rectangle VIA1, LH1, which has an overlap with
Extract LH2, LV2, and R1.

Each rectangle V extracted as shown in FIG.
Rectangles VIA110 and LH11 obtained by expanding IA1, LH1, LH2, LV2, and R1 by the minimum spacing LM1.
The cut lines L1 to L6 are set along each side of the horizontal direction of 0, LH120, LV120, and R110, and each rectangle is divided.

However, instead of actually dividing the rectangle, the rectangle existing between L1 and L2 is the VIA 110, L.
The rectangles existing between H110, LV120, L2 and L3 are VIA110, LH110, LH120, LV12.
The rectangle existing between 0, R110, L3 and L4 is VIA.
110, LH110, LH120, LV120, R11
0, the rectangle existing between L4 and L5 is VIA110, L
The rectangles existing between H110, LV120, R110, L5 and L6 are VIA110, LH110, LV120,
It should be understood that it is R110.

For each of the divided rectangles, it is possible to refer to the information of the rectangle before division and the information of the rectangle before expansion.

The conditions under which two rectangles of the same potential for which the spacing rule is defined do not cause a spacing error are:
As shown in FIG. 7, when two rectangles overlap or are in contact with each other, and when these two rectangles are expanded by LM1, the LM of the spacing rule is set in the horizontal or vertical direction.
Overlaps with a length more than twice the length of 1 are possible. When two rectangles of different potentials for which the spacing rule is defined overlap or are in contact with each other, the wiring is short-circuited, resulting in a spacing error (more accurately, a connection error).

As shown in FIG. 8, the distance between the two rectangles is the spacing, as shown in FIG. 8, under the condition that two rectangles of different potentials or two rectangles of the same potential for which the spacing rule is defined do not cause a spacing error. If the two rectangles are expanded by LM1 when the rule is LM1 or more, the LM of the spacing rule is set in the horizontal or vertical direction.
Overlap of 1 or less, or no overlap at all.

Therefore, as a condition for causing a spacing rule error between two rectangles expanded by LM1, the overlap between the two rectangles is set to L or L in the horizontal or vertical direction.
This is the case where it is larger than M1 and smaller than twice LM1.

Since the error determination condition differs depending on the length (or distance) of the extended rectangle, it is necessary to set the error determination condition that matches the length (or distance) of the extended rectangle.

Rectangles VIA110 and R11 existing between L2 and L3 that cause the pseudo design rule error
The error check processing of the pseudo design rule error reverification step 17 in the horizontal direction will be described by taking 0, LV120, and LH120 as an example.

VIA110, R110, LV120, L
H120 is divided by cut lines L2 and L3, respectively.
The divided rectangles of the VIA 110 are set as VIA 111 and R11.
The divided rectangle of 0 is R111, the divided rectangle of LV120 is LV122, and the divided rectangle of LH120 is L.
H122.

As shown in FIG. 10, the VIA 111 and the adjacent R111 perform error checking. VIA1 and R1
Since VIA111 and R111 adjacent to each other are overlapped with each other twice as much as LM1, the pseudo design rule error does not occur. Merge VIA111 and R111 to V
Make IA111_R111.

As shown in FIG. 11, VIA111_R11
An error check is performed between 1 and the adjacent LV 122. R
Since 1 and LV2 were in contact with each other, the overlap of VIA111_R111 and LV122 was twice that of LM1, and a pseudo design rule error did not occur. VIA111_R1
11 and LV122 are merged and VIA111_R111L
Make V122.

VIA111_R11 as shown in FIG.
An error check is performed between the 1_LV 122 and the adjacent LH 122. R1 and LH2 are in contact with each other, and LV2 and L
H2 was connected, so VIA111_R111_
LV122 and LV122 overlap twice as much as LM1 and LV2
Nohabara W1 is added, which is 2 × LM1 + W
1> 2 × LM1 and no pseudo design rule error has occurred.

Therefore, VIA1 and LV2, VIA1
It can be confirmed that the pseudo design rule error between LH2 and LH2 has been corrected by R1.

In the vertical direction, each extracted rectangle VI
Rectangles VIA110, LH110, which are obtained by expanding A1, LH1, LH2, LV2, R1 by the minimum spacing LM1.
A cut line is set along each side of the LH120, LV120, and R110 in the vertical direction, and the pseudo design rule error is reverified by the same method.

It is also shown that the pseudo design rule error correction location re-verification step 17 can check the pseudo design rule error of the mask pattern shown in FIG.

As shown in FIG. 13, each of the extracted rectangles VIA1, LH1, LH2, LV2 is extended by a minimum spacing LM1 to obtain a rectangle VIA110, LH110, L.
Cut lines L1 to L6 are set along each horizontal side of H120 and LV120, and each rectangle is divided.

Rectangle VIA111, LV122, LH12 existing between L2 and L3 which caused the pseudo design rule error.
2, the LV122 and LH122 that are adjacent to the VIA111
Then, each pseudo design rule error check is performed.

As shown in FIG. 14, the VIA 111 and the LV
The overlap of 122 is 2 × LM1-WE <2 × LM1, and it can be seen that a pseudo design rule error has occurred.

Similarly, as shown in FIG.
And LH122 overlap is 2 × LM1-WE <2 × LM1
Therefore, it can be seen that a pseudo design rule error has occurred.

If a pseudo design rule error is found in the step 17 for re-verifying the correction portion of the pseudo design rule error, the pseudo design rule error correction step 16 is returned to the pseudo design rule error correction step 16 in the pseudo design rule error judgment step 15 and the end condition judgment step 15. The rule error is corrected, and the pseudo design rule error corrected portion is checked at the pseudo design rule error corrected portion re-verification step 17.

If the pseudo design rule error disappears,
Finally, in the data output step 18, a file of mask pattern data in which the pseudo design rule error is corrected is created and output from the pseudo design rule error correction file and the mask pattern input in the data input step 11. Further, when the design rule error remains, in order to correct the design rule error, information such as coordinates, wiring layer, net number, etc. regarding the area and rectangle in which the design rule error has occurred is output.

When the data amount of the mask pattern is very large, the mask pattern area is divided into several parts,
If the mask patterns of the divided areas are assigned to a plurality of computers and processors and parallel processing is performed, extremely high speed processing is possible.

(Embodiment 2) FIG. 16 shows a data flow in the layout verification apparatus according to the second embodiment of the present invention. FIG. 17 shows a hardware configuration for performing the above processing.

The data input device 111 performs the process of the data input step 11 shown in FIG. The mask pattern data and the design rule are transferred from another system using the network bus 209 and written to the external storage device 207 through the interface 210 or input from the input device 208 and written to the external storage device 207. Be done.

The mask pattern data classification and storage device 112 performs the mask pattern data classification step 12 shown in FIG. 1 and holds the mask pattern data file of each wiring layer. At this time, the mask pattern data file of each wiring layer is written in the external storage device 207.

In the design rule error search device 113,
The design rule error searching step 13 is performed.

In the design rule error judgment device 114,
The design rule error determination step 14 shown in FIG. 1 is performed.

Pseudo-design rule error judgment and design rule error storage and processing end judgment device 115
Then, the process of the pseudo design rule error determination step 15 is performed. It is written in the external storage device 207 as design rule error information such as the coordinate value of the rectangle causing the design rule error, the wiring layer, and the net number.

Pseudo-design rule error correction device 116
Then, the pseudo design rule error correction step 16 in FIG.
Is processed. The pseudo design rule error correction information of the rectangular coordinate value, wiring layer, and net number in which the pseudo design rule error is corrected is written in the external storage device 207. Further, the input mask pattern data and the pseudo design rule error correction information are merged to newly create mask pattern data in which the pseudo design rule error is corrected, and the mask pattern data is written in the external storage device 207.

The pseudo design rule error correction point re-check device 117 performs the processing of the pseudo design rule error correction point re-check step 17 in FIG.

The data output device 118 outputs the design rule error information and the pseudo design rule error correction information written in the external storage device 207 such as a magnetic disk by the output device 206 or the graphic display 2
01 is displayed.

In the mask pattern display device 119, the data output device 118 is used as an external storage device 207 such as a magnetic disk.
The input mask pattern data, the mask pattern data in which the pseudo design rule error is corrected, the necessary data in the rectangle, the area, etc. in which the design rule error has been written, are displayed on the graphic display 201, or the graphic information is output by the output device. Etc. are output.

When the design rule error remains, the mask pattern editing device 119 displays the design pattern error information and the mask pattern data in which the pseudo design rule error is corrected on the graphic display 201 on the mask pattern display device 118, While referring to the rule error information, the design rule error of the mask pattern data in which the pseudo design rule error is corrected is interactively corrected using the keyboard 203 and the mouse 202.

[0059]

As described above, according to the present invention, it is possible to modify a pseudo design rule and verify a mask pattern modified by the pseudo design rule.

[Brief description of drawings]

FIG. 1 is a flowchart showing processing of a layout verification method according to a first embodiment of the present invention.

FIG. 2 is a diagram showing a mask pattern used in the layout verification method of the first embodiment.

FIG. 3 is a diagram showing a part of a first wiring layer in the mask pattern of FIG.

FIG. 4 is a diagram showing an example of an area in which a pseudo design rule error has occurred.

FIG. 5 is a diagram showing an example of a mask layout in which a pseudo design rule error is corrected.

FIG. 6 is a diagram for explaining a re-verification step of a pseudo design rule error correction location.

FIG. 7 is a diagram illustrating a condition for preventing a spacing error between two rectangles having the same potential and having a spacing rule.

FIG. 8 is a diagram illustrating a condition in which two rectangles having different potentials or two rectangles having the same potential with a spacing rule do not cause a spacing error.

FIG. 9 is a diagram illustrating division of a rectangle extracted in a pseudo design error correction location reverification step.

FIG. 10 is a diagram for explaining error checking between VIA111 and R111.

FIG. 11 is a diagram illustrating error checking between VIA111_R111 and LV122.

FIG. 12: VIA111_R111_LV122 and LH
The figure explaining the error check with 122.

FIG. 13 is a diagram for explaining the step of re-verifying the pseudo design rule error correction portion.

FIG. 14 is a diagram for explaining an error check for overlapping VIA111 and LV122.

FIG. 15 is a diagram for explaining an error check for overlapping VIA111 and LH122.

FIG. 16 is a diagram showing a data flow in the layout verification apparatus according to the second embodiment of the present invention.

FIG. 17 is a diagram showing a hardware configuration of a second embodiment.

[Explanation of symbols]

11 data input step 12 mask pattern classification step 13 design rule error search step 14 design rule error judgment step 15 pseudo design rule error judgment and end condition judgment step 16 pseudo design rule error correction step 17 pseudo design rule error correction recheck step 18 Data output step 111 Data input device 112 Mask pattern classification and storage device 113 Design rule error search device 114 Design rule error judgment device 115 Pseudo design rule error judgment and design rule error storage and processing end judgment device 116 Pseudo design rule error correction device 117 Pseudo-design rule error rechecking device 118 Data output device 119 Error display device 120 Mask pattern editing device

Claims (6)

[Claims] 1. A cut for dividing a rectangle along a horizontal or vertical direction in a mask layout composed of rectangles such as VLSI, of all rectangles for which a spacing rule is defined or a rectangle extended by a minimum spacing. Setting a line or slit, checking whether the distance between adjacent rectangles existing between adjacent cut lines adheres to the design rules, and causing a spacing error. A method of verifying a layout, comprising the step of storing and outputting the previous rectangle information. 2. The method of verifying a layout according to claim 1, further comprising the step of correcting the minimum spacing error by filling a region having a minimum spacing error between the rectangles of the same wiring layer at the same potential with a rectangle. Layout verification method with. 3. The layout verification method according to claim 2, further comprising the step of storing an area in which an error is corrected, expanding the area by a minimum spacing, and extracting a rectangle of the expanded area. Layout verification method. 4. A cut for dividing a rectangle along a horizontal or vertical direction in a mask layout composed of rectangles such as VLSI, of all rectangles for which a spacing rule is defined or a rectangle extended by a minimum spacing. A means to set a line or a slit, a means to check whether the distance between the adjacent rectangles existing between the adjacent cut lines complies with the design rule, and a spacing error is caused, and it is divided by the cut line. A layout verification device comprising means for storing and outputting the previous rectangle information. 5. The layout verifying device according to claim 4, further comprising means for correcting a minimum spacing error by filling a region having a minimum spacing error between rectangles of the same wiring layer at the same potential with a rectangle. Layout verification device equipped with. 6. The layout verification apparatus according to claim 5, further comprising means for storing an area where an error is corrected, expanding the area by a minimum spacing, and extracting a rectangle of the expanded area. Layout verification device.