JP3498674B2 - Semiconductor integrated circuit device, clock wiring method, and recording medium - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a semiconductor integrated circuit device having a plurality of circuits that require a clock signal represented by a processor or the like, and a clock for improving clock skew of a clock signal supplied to the plurality of circuits. The present invention relates to a wiring method and a recording medium for executing the clock wiring method.

[0002]

Synchronous integrated circuits use clock signals to control the timing of the entire system.
This clock signal must be transmitted to various functional blocks such as flip-flops and latches arranged over the entire area of the integrated circuit, memories and interface blocks using the clock signal. If the functional blocks controlled by the same clock are arranged at different distances from the clock driver, the time for receiving the clock signal will be different. This variation in the arrival time of the clock signal is called clock skew.

The cause of the clock skew is caused by the delay caused by the clock buffer used for distributing the clock, the clock wiring resistance (R) and the capacitance (C). This clock skew can be minimized by equally distributing all clock buffers and wiring lengths that carry clock signals.

However, even if the clock signal is wired in equal length, the capacity of the clock wiring is determined by the environment of other signal wiring adjacent to and intersecting with the clock wiring, so that the capacity of the clock wiring is not uniform. The area for drawing out the clock branch wiring between the long distance clock wiring and the signal wiring is greatly affected by the degree of congestion of the signal wiring layer. That is, in order to minimize the clock skew, it is necessary to make the capacitance (C) around the clock wiring uniform in addition to the wiring resistance (R).

A conventional clock wiring method will be briefly described. FIG. 5 shows a processing procedure of a conventional clock wiring method. Further, FIG. 6A and FIG. 6B are a plan view and a cross-sectional view as an example, which schematically show the arrangement relationship of the respective constituent elements of the conventional semiconductor integrated circuit device. The design of the wiring pattern is realized by an information processing device having a recording medium in which a predetermined program is recorded.

First, a block library and a netlist are input (step S61). Next, wiring of the long-distance clock trunk lines 212, 212a to 212c and wiring of the power supply line are performed (step S62). When the wiring is completed, each block (memory 204, functional block 205,
An I / O buffer or the like) is provided (step S63). Then, the clock branch lines 213a to 213c are wired (step S64), and when the clock branch line wiring is completed, the general signal line is wired (step S65).
6A, a pulse generator is indicated by 207, a clock driver is indicated by 208 to 211, a clock input terminal is indicated by 214a to 214c, and a shield is indicated by 215. Wiring.

[0007]

However, in the prior art, the wiring capacity of the clock trunk line and the clock branch line is obtained, and the load capacity is manually adjusted to a clock wiring position having a small capacity to reduce the capacity of the clock wiring. Work to make them uniform is necessary. Further, even if the clock skew is suppressed by providing the shield wiring (see 215 in FIG. 6) to the clock wiring, there are places where sufficient effects cannot be obtained due to structural restrictions. There was a problem.

The present invention has been made in view of the above problems, and an object of the present invention is to provide a semiconductor integrated circuit provided with clock wiring capable of suppressing clock skew more efficiently and effectively. An object is to provide an apparatus, a clock wiring method, and a recording medium that executes the wiring method.

[0009]

The present invention has the following constitution in order to solve the above problems. The gist of the invention according to claim 1 is a semiconductor integrated circuit device having a plurality of circuits that require a clock signal, wherein a clock main line from a pulse generator and a clock driver, a power supply and a ground line, and the clock main line. The shield branch wiring and the plurality of circuits are arranged, and the clock branch line is determined according to the determination result obtained by determining whether or not the arrangement relationship of each of the constituent elements of the device satisfies a predetermined rule. And a shield wiring for a clock branch line are arranged, and in order to fix the shield wiring for the clock branch line and either one of the power supply line or the ground line, there is a connecting means for connecting a region where the two intersect. Furthermore, the shield wiring for the clock main line includes a plurality of designated areas for wiring of the clock branch line, and each of the constituent elements of the device. When it is determined that the arrangement relationship does not satisfy the predetermined rule, it is obtained by deleting predetermined ones of the plurality of designated areas for wiring of the clock branch line included in the shield wiring for the clock trunk line. The semiconductor integrated circuit device is characterized in that the clock branch line and the shield wiring for the clock branch line are arranged for the region. Summary of the Invention described in claim 2, claim 1, wherein the respective shapes of a plurality of designated regions for wiring of the clock branch included in the shield wiring for the clock trunk line has a rectangular Existing in the semiconductor integrated circuit device. According to a third aspect of the present invention, there is provided a semiconductor integrated circuit device having a plurality of circuits requiring a clock signal, the clock main line from a pulse generator and a clock driver,
Power supply and ground lines, the shield wiring for the clock main line, and the plurality of circuits are arranged, and it is obtained by determining whether or not the respective arrangement relationships of the components of the device satisfy a predetermined rule. According to the determination result, a clock branch line and a shield wiring for the clock branch line are arranged, and the two cross each other in order to fix the shield wiring for the clock branch line and either one of the power supply line or the ground line. Various data for arranging the clock branch line when connection means for connecting the regions is arranged, and further, when it is determined that the arrangement relation of each of the constituent elements of the device does not satisfy the predetermined rule. The clock branch line and the shield wire for the clock branch line are arranged in an area obtained by deleting a predetermined area of the shield wire for the clock trunk line based on And that resides in a semiconductor integrated circuit device according to claim is. The gist of the invention according to claim 4 is that the shape of the region of the shield wiring for the clock main line that is deleted when the arrangement relationship of each of the constituent elements of the device is determined not to satisfy the predetermined rule. A semiconductor integrated circuit device according to claim 3 , wherein the semiconductor integrated circuit device has a rectangular shape. Summary of the Invention of claim 5, wherein the any of claims 1-4, characterized in that the two shield lines for clock branch Te following are arranged at predetermined intervals in parallel around the clock branch In the semiconductor integrated circuit device described in 1. According to a sixth aspect of the present invention, there is provided a clock wiring method in a semiconductor integrated circuit device having a plurality of circuits that require a clock signal, the first step including arranging a clock main line from a pulse generator and a clock driver. A second step of arranging power and ground lines and shield wiring for the clock main line, a third step of arranging the plurality of circuits, and each of the first, second and third steps. And a fourth step of arranging the clock branch line and the shield wiring for the clock branch line according to the determination result of the determination step. In order to fix the shield wiring for the clock branch line and either one of the power supply line and the ground line, there is provided a connecting means for connecting a region where the both intersect. Further, the shield wiring for the clock main line in the second step includes a plurality of designated areas for wiring of the clock branch line, and the predetermined rule is not satisfied in the determining step. If it is determined that the predetermined area of the plurality of designated areas for wiring of the clock branch line included in the shield wiring for the clock main line is deleted in the fourth step, the obtained area is The clock branch line and the shield wiring for the clock branch line. According to a seventh aspect of the present invention, each of the plurality of designated regions for wiring of the clock branch line included in the shield wiring for the clock main line in the second step has a rectangular shape. The clock wiring method according to item 6 exists. Claim
The gist of the invention described in 8 is a clock wiring method in a semiconductor integrated circuit device having a plurality of circuits that require clock signals, the first step of arranging a clock main line from a pulse generator and a clock driver, and a power supply. And a second step of arranging the ground line and the shield wiring for the clock main line, and a third step of arranging the plurality of circuits.
A step of determining whether or not the placement result performed in each of the first, second, and third steps satisfies a predetermined rule, and a clock branch line and a clock branch line according to the determination result of the determining step. A fourth step of arranging a shield wire for the clock, and a shield wire for the clock branch line,
A fifth step of arranging a connecting means for connecting a region where the power source and the ground line intersect with each other in order to fix the power source or the ground line. , The step of inputting various data for arranging the clock branch line, and when it is determined in the determining step that the predetermined rule is not satisfied, the input is performed in the fourth step. A predetermined area of the shield wiring for the clock trunk line is deleted based on various data obtained by the process, and the clock branch line and the shield wiring for the clock branch line are arranged in the obtained area. It depends on the clock wiring method. The gist of the invention according to claim 9 is that the shape of the area of the shield wiring for the clock trunk line deleted in the fourth step when it is determined that the predetermined rule is not satisfied in the determining step is 9. The clock wiring method according to claim 8 , wherein the clock wiring method has a rectangular shape. The gist of the invention according to claim 10 is that, in the fourth step, two shield wires for the clock branch lines are arranged in parallel with the clock branch line as a center at a predetermined interval. The clock wiring method according to any one of items 6 to 9 . The gist of the invention according to claim 11 resides in a recording medium characterized in that a program capable of executing the clock wiring method according to any one of claims 6 to 10 is recorded.

[0010]

BEST MODE FOR CARRYING OUT THE INVENTION Embodiments of the present invention will be described in detail below with reference to the drawings.

(First Embodiment) FIG. 1A is a plan view schematically showing the arrangement relationship of the respective constituent elements of the first embodiment of the present invention. 1B is a cross-sectional view taken along the chain line AA ′ in FIG. 1A. Figure 1A
1B, 101 shows the whole semiconductor integrated circuit device. As shown in FIG. 1, a semiconductor integrated circuit device 101 according to the first embodiment has a memory 104, a functional block 105, and an I / O as a plurality of circuits requiring a clock signal.
It has a buffer and so on. Further, a pulse generator is shown by 107 in FIGS. 1A and 1B,
Clock drivers are shown by 108 to 111, and clock input terminals are shown by 114a to 114c. In the following description, the memory 104 will be used for convenience.
Also, the description will be focused on the periphery of the functional block 105, but other parts are also configured in the same manner although they are omitted in the drawing.

As shown in FIG. 1, a semiconductor integrated circuit device 10
In FIG. 1, after deleting the rectangular figure data 117a and 117b for shield wiring in the layer below the clock trunk line 112, the clock branch lines 113a and 113b with shield wiring are deleted.
Is drawn out and connected to the clock input terminals 114a and 114b of the memory 104 and the functional block 105.

The clock signal output from the pulse generator 107 is provided with a long-distance clock main line 112 via each of the clock drivers 108 to 111 arranged equidistantly at the branch points in order to suppress delay variation, that is, clock skew. Be transmitted to. The long-distance clock trunk line 112 is provided with a shield wiring 115 connected to a power source or a ground under the clock wiring in order to suppress variations in wiring capacitance.

A signal wiring layer 118 is formed below the shield wiring 115. In the above-described conventional semiconductor integrated circuit device, since there is a gap between the clock wiring and the signal wiring (see FIG. 6B), the capacity of the clock wiring is affected by the congestion degree of the general signal wiring. In the semiconductor integrated circuit device 101 according to the present invention, since the shield wiring is provided over the entire area between the long-distance clock trunk line 112 and the signal wiring layer 118, the wiring capacitance of the clock wiring is the congestion of the general signal wiring. The clock delay remains almost constant in any region without affecting the frequency.

Below the signal wiring layer 118 is a transistor arrangement region, in which an internal region 102 and an interface region 103 are provided. The internal area 102 has a memory 104 having a clock input terminal 114a.
In addition, the functional block 105 (clock buffer, FF, latch, etc.) is also provided in the interface area 103.
The interface block 106 having the clock input terminal 114c is arranged at an arbitrary place.

In order to prevent the clock signal transmitted to the clock main line 112 of the semiconductor integrated circuit device 101 having the above-described structure from being affected by the capacitance variation in the subsequent wiring paths, shield wiring is provided. The attached clock branch lines 113a and 113b are arranged.

Specifically, from the clock input terminals 114a and 114b of the memory 104 and the functional block 105,
The clock branch lines 113a and 113b with shield wiring are drawn out toward the coordinate positions 112a and 112b of the clock trunk line where the closest clock branch line can be drawn out. At this time, if a short error or a spacing error occurs, rectangular graphic data 117 for shield wiring that is created in advance to satisfy the design rule.
a and 117b are deleted, and clock branch lines 113a and 113b with shield wiring are drawn out to the obtained area. An automatically generated power supply wiring via is arranged in a region where the shield wiring for the clock branch line and the power supply or ground line intersect. Therefore, from the long-distance clock main line 112 to the clock input terminal 114a of each block.
Up to 114c, variations in capacitance with other signal wirings are made substantially uniform, and clock skew is minimized.

2A and 2B are an enlarged plan view and a sectional view of a region B in FIG. 1A after the functional blocks are arranged, showing a state before the clock branch line 113b with the shield wiring is drawn. 2C and 2D
2A is also an enlarged plan view and a sectional view of a region B in FIG. 1A, showing a state in which a clock branch line 113b with a shield wiring is drawn. The first embodiment will be further described with reference to FIGS. 2A to 2D.

In the state shown in FIGS. 2A and 2B, in order to suppress variations in the wiring capacity of the long-distance clock main line 112, a power supply or ground shield wiring 115 is provided below the long-distance clock main line 112. It is provided. The lower side of the shield wiring 115 is a general signal wiring layer 1
It is supposed to be 18, and the general signal wiring is passing,
The shield wiring 115 is disposed between the long-distance clock trunk line 112 and the signal wiring layer 118 and is completely separated, and there is no influence of the capacitance with the signal wiring.
In this state, when a via for clock wiring is generated in the shield wiring 115 at the coordinate position of the intersection of the clock main line 112 and the clock branch line from which the wiring can be drawn,
A plurality of rectangular graphic data to be deleted areas that do not violate a design rule or a short circuit are created in advance.

Then, as shown in FIGS. 2C and 2D, at the clock input terminal position 114b of the functional block 105,
The clock branch line 113b with the shield wiring (115b) is drawn. That is, for the functional block 105 having the clock input terminal 114b, the rectangular graphic data 117b corresponding to the wiring drawing position is deleted to generate the via 123b for the clock wiring, and the clock branch line 113b with the shield wiring (115b) is drawn. . Therefore, even after the clock branch line is drawn out to the clock terminal of each block, only the predetermined graphic data 117b of the plurality of rectangular graphic data created in advance at the wiring drawing position is deleted. The wiring capacity of the clock wiring is minimized. The shield wiring 115b for the clock branch line is provided with a via 125b for power supply wiring in a region intersecting with the same power supply or ground. As shown in FIG. 2C, the two shield wirings 115b for the clock branch lines are arranged in parallel with the clock branch line 113b as a center at predetermined intervals according to the design rule.

FIG. 3 is a flow chart showing the processing procedure of the clock wiring method according to the first embodiment. In FIG. 3, step S1 to step S
Reference numerals up to 8 are attached. Further, the actual wiring pattern design has a recording medium in which a predetermined program corresponding to the processing procedure shown in FIG. 3 is recorded, and the predetermined information is read from the recording medium as necessary to execute a specific process. It is realized by an information processing device capable of processing.

First, in step 1, a block library and a net list are input. Then, in step 2, the long-distance clock main line 112 and the power supply line including the shield wiring 115 including the rectangular graphic data for deletion (see 117b in FIG. 2A) are arranged. Next, in step 3, the memory 104, the functional block 105, the I / O buffer, etc. are arranged, and when the arrangement is completed, the process moves to the wiring of the clock branch line with the shield wiring (step 4 to step 7).

In the wiring of the clock branch line with the shield wiring, first, in step 4, it is judged whether or not there is a short circuit or a portion that does not satisfy the design rule. If it is determined that the above condition is satisfied, the process proceeds to step 6 and the clock branch line is directly arranged. On the other hand, when it is determined in step 4 that there is a short-circuited portion or a portion that does not satisfy the design rule, the process proceeds to step 5 and a predetermined position that is previously included in the coordinate position of the shield wiring is determined. Rectangular figure data (see 117b in FIG. 2A) is deleted. When the figure data is deleted and the wiring area is secured, step 6
At, a clock branch is placed. Then, in order to prevent the shield wiring (see 115b in FIG. 2C) of the arranged clock branch line with shield wiring from becoming a floating wiring, in step 7, a via for power supply wiring (FIG. 2C is formed in a region intersecting with the power supply or ground wiring). 125b) is generated. When the wiring of the clock branch line with the shield wiring is completed in this way, the wiring of the general signal line is performed in step 8.

In the above description of the first embodiment, a via for clock wiring is generated at the coordinate position of the intersection of the clock trunk line 112 of the shield wiring 115 and the clock branch line from which the wiring can be drawn. Also, the case where a plurality of rectangular graphic data to be deleted areas that do not violate a design rule or a short circuit has been created in advance has been described, but graphic data having a line-symmetrical shape other than a rectangle may be created. .

As described above, according to the first embodiment, the following effects can be obtained. The effect is that the long-distance clock trunk line is shielded from other general signal wiring by shield wiring, and further, when wiring from the long-distance clock trunk line to each clock terminal, shield according to the design standard Since the clock branch line with the shield wiring is drawn to the area obtained by deleting the predetermined one of the predetermined figure data of the wiring, it is possible to further suppress the influence of the delay due to the difference in the capacitance with the signal wiring. Become. Therefore, the clock wiring can minimize a variation error in capacitance delay with other signal wirings, that is, a clock skew.

(Second Embodiment) FIG. 4 is a flowchart showing a processing procedure of a clock wiring method according to a second embodiment of the present invention. The clock wiring method according to the second embodiment differs from the clock wiring method according to the first embodiment in that the rectangular graphic data for deletion is not created in advance in the shield wiring 115, but the first data described above by the coordinate data is used. A clock branch line with shield wiring having the same effect as that of the clock wiring method according to the embodiment is arranged. Note that, with respect to the step of performing the same processing as the clock wiring method according to the above-described first embodiment, the same reference numerals are given to corresponding portions, and the description of the portions will be omitted.

First, in step 1, a block library and a netlist are input. Then, in step 42, the long-distance clock main line and the power supply line including the shield wiring are arranged. Next, in step 3, each block is arranged, and in step 43, various data necessary for wiring the clock branch line is input. Specifically, the starting point coordinate position of the clock main line connectable to the clock terminals of the functional block, the memory, and the interface block, the number of repetitions and intervals in the X-axis and Y-axis directions, and the power supply for drawing out the clock branch line. Alternatively, a clock wiring lead-out position description file that specifies a layer in which wiring is deleted when the ground line needs to be deleted and an area width in the X-axis and Y-axis directions in which wiring is deleted is created and input in advance. When the input of various data necessary for the wiring of the clock branch line is completed, the process moves to the wiring of the clock branch line with shield wiring (step 44, step 46, step 6, step 7).

When shifting to the wiring of the clock branch line with shield wiring, first, at step 44, based on the data of the description file describing the extraction position of the clock branch line, the coordinate position of the file closest to the clock input terminal position of each block. Then, when drawing out the clock branch line wiring, it is determined whether or not a spacing or a short circuit error will occur according to the design rules. If it is determined that an error does not occur, go to step 6,
A clock branch line is drawn from each coordinate position of the nearest file to each clock terminal. On the other hand, if it is determined in step 44 that the design rule has an error and the shield wiring needs to be deleted, the process proceeds to step 46, and the X of the layer specified in the clock wiring lead-out position description file is written.
The shield wiring in a region having a predetermined width in the axis and Y axis directions is deleted. Then, in step 6, the clock branch line is arranged. Then, in step 7, a via for power supply wiring is generated in a region intersecting the power supply or ground wiring so that the shield wiring of the arranged clock branch line with shield wiring does not become a floating wiring. When wiring of the clock branch line with shield wiring is completed in this way, step 8
In, general signal lines are wired.

As described above, according to the clock wiring method of the second embodiment, it is possible to provide the semiconductor integrated circuit device having the same effect as that of the first embodiment. In addition, since the clock wiring lead-out position description file is created and input in advance, the load on the software of the information processing device can be reduced.

It should be noted that the present invention is not limited to the above-described embodiments, and it is apparent that the embodiments can be modified appropriately within the scope of the technical idea of the present invention. Further, the number, position, shape, etc. of the above-mentioned constituent members are not limited to those in the above-mentioned embodiment, and the number, position, shape, etc. suitable for carrying out the present invention can be adopted. Further, in each drawing, the same components are designated by the same reference numerals.

[0031]

Since the present invention is configured as described above, it has the following effects. The effect is that the long-distance clock trunk line is shielded from other general signal wiring by shield wiring, and further, when wiring from the long-distance clock trunk line to each clock terminal, shield according to the design standard Delete the shield wiring of the area obtained by deleting the predetermined one of the predetermined figure data of the wiring or the area of the predetermined width in the X-axis and Y-axis directions of the layer specified in the clock wiring drawing position description file. Since the clock branch line with the shield wiring is drawn out from the obtained area, it is possible to further suppress the influence of delay due to the difference in capacitance with the signal wiring. Therefore, the clock wiring can minimize a variation error in capacitance delay with other signal wirings, that is, a clock skew.

[Brief description of drawings]

1A and 1B are a plan view and a cross-sectional view showing an arrangement relationship of constituent elements according to a first embodiment of the present invention.

2 is an enlarged plan view and cross-sectional view of a region B in FIG.

FIG. 3 is a flowchart showing a processing procedure of a clock wiring method according to the first embodiment of the present invention.

FIG. 4 is a flowchart showing a processing procedure of a clock wiring method according to the second embodiment of the present invention.

FIG. 5 is a flowchart showing a processing procedure of a conventional clock wiring method.

6A and 6B are a plan view and a cross-sectional view showing an arrangement relationship of components of a conventional semiconductor integrated circuit device.

[Explanation of symbols]

101 ... Semiconductor integrated circuit device 102 ... Internal area 103 ... Interface area 104 ... Memory 105 ... Functional block 106 ... Interface block 107 ... Pulse generators 108-111 ... Clock Driver 112 ... Clock trunks 112a, 112b for long distances ... Coordinate positions 113a, 113b of clock trunks ... Clock branch lines 114a to 114c with shield wiring ... Clock input terminal 115 ... Shield wiring 115b. ..Shield wirings 117a and 117b for clock branch lines ... Rectangular graphic data 118 ... Signal wiring layer 123b ... Vias 125b for clock wiring ... Vias for power supply wiring

─────────────────────────────────────────────────── ─── Continuation of front page (51) Int.Cl. ⁷ identification code FI H01L 27/04 H (58) Fields investigated (Int.Cl. ⁷ , DB name) H01L 21/82 H01L 21/822 H01L 27 / 04 G06F 17/50

Claims (11)

(57) [Claims] 1. A semiconductor integrated circuit device having a plurality of circuits that require a clock signal, comprising: a clock main line from a pulse generator and a clock driver; a power supply and a ground line; and a shield wiring for the clock main line. , The plurality of circuits are arranged, the clock branch line and the clock branch line for the clock branch line according to the determination result obtained by determining whether the arrangement relationship of each of the constituent elements of the device satisfies a predetermined rule. Shield wiring is arranged, in order to fix the shield wiring for the clock branch line and either one of the power supply or the ground line, connecting means for connecting regions where the two intersect, are arranged, The shield wiring for the clock main line includes a plurality of designated areas for wiring the clock branch lines, and the respective layout relationships of the components of the device are When it is determined that the predetermined rule is not satisfied, a predetermined area of the plurality of designated areas for wiring of the clock branch line included in the shield wiring for the clock main line is deleted from the area obtained. The semiconductor integrated circuit device, wherein the clock branch line and the shield wiring for the clock branch line are arranged. 2. The semiconductor integrated circuit device according to claim 1 , wherein each of the plurality of designated regions for wiring of the clock branch line included in the shield wiring for the clock main line has a rectangular shape. . 3. A semiconductor integrated circuit device having a plurality of circuits that require a clock signal, the clock main line from a pulse generator and a clock driver, a power supply and a ground line, and a shield wiring for the clock main line. , The plurality of circuits are arranged, the clock branch line and the clock branch line for the clock branch line according to the determination result obtained by determining whether the arrangement relationship of each of the constituent elements of the device satisfies a predetermined rule. Shield wiring is arranged, in order to fix the shield wiring for the clock branch line and either one of the power supply or the ground line, connecting means for connecting regions where the two intersect, are arranged, Various data for arranging the clock branch line when it is determined that the respective arrangement relationships of the constituent elements of the device do not satisfy the predetermined rule. The semiconductor integrated circuit device, wherein the clock branch and the shield wiring for the clock branch is arranged with respect to the clock trunk line area obtained by removing a predetermined area of the shield wiring based. 4. The shape of the area of the shield wiring for the clock main line, which is deleted when it is determined that the arrangement relationship of each component of the device does not satisfy the predetermined rule, is a rectangle. 4. The semiconductor integrated circuit device according to claim 3 , wherein: 5. A semiconductor according to any of claims 1 to 4, characterized in that the shield lines for clock branch two Te than in parallel with a predetermined interval around the clock branch is arranged Integrated circuit device. 6. A clock wiring method in a semiconductor integrated circuit device having a plurality of circuits requiring a clock signal, comprising: a first step of arranging a clock main line from a pulse generator and a clock driver; and a power supply and ground line. And a second step of arranging the shield wiring for the clock trunk line, a third step of arranging the plurality of circuits, and an arrangement result obtained in each of the first, second, and third steps. Determines whether or not the predetermined rule is satisfied, a fourth step of arranging a clock branch line and a shield wiring for the clock branch line according to the determination result of the determination step, and the clock branch line And a fifth step of arranging a connecting means for connecting a region where the shield wiring and the power supply line or the ground line intersect with each other in order to fix the shield wiring. Further, when the shield wiring for the clock main line in the second step includes a plurality of designated areas for wiring of the clock branch line, and it is determined in the determining step that the predetermined rule is not satisfied. In the fourth step, predetermined ones of a plurality of designated areas for wiring of the clock branch line included in the shield wiring for the clock trunk line are deleted, and the clock branch line is added to the obtained area. And a shield wiring for the clock branch line. 7. The clock according to claim 6 , wherein each of the plurality of designated regions for wiring of the clock branch line included in the shield wiring for the clock main line in the second step has a rectangular shape. Wiring method. 8. A clock wiring method in a semiconductor integrated circuit device having a plurality of circuits that require clock signals, the first step of arranging a clock main line from a pulse generator and a clock driver, and a power supply and ground line. And a second step of arranging the shield wiring for the clock trunk line, a third step of arranging the plurality of circuits, and an arrangement result obtained in each of the first, second, and third steps. Determines whether or not the predetermined rule is satisfied, a fourth step of arranging a clock branch line and a shield wiring for the clock branch line according to the determination result of the determination step, and the clock branch line And a fifth step of arranging a connecting means for connecting a region where the shield wiring and the power supply line or the ground line intersect each other in order to fix the shield wiring. In addition, in the case where it is determined that the predetermined rule is not satisfied in the determining step, the method further includes the step of inputting various data for arranging the clock branch line before the determining step. In the fourth step, a predetermined area of the shield wiring for the clock main line is deleted based on various data obtained in the input step, and the clock branch line and the clock are added to the obtained area. A clock wiring method characterized by arranging shield wiring for branch lines. 9. The shape of the region of the shield wiring for the clock main line that is deleted in the fourth step when it is determined in the determining step that the predetermined rule is not satisfied is rectangular. 9. The clock wiring method according to claim 8, which is characterized in that. In wherein said fourth step, the claims 6-9, characterized in that disposed parallel to the shield wire of the two clock branch Te than at predetermined intervals around the clock branch The clock wiring method according to any one. 11. A recording medium on which a program capable of executing the clock wiring method according to claim 6 is recorded.