JP2000150659A - Method for designing layout of semiconductor integrated circuit device - Google Patents

Abstract

PROBLEM TO BE SOLVED: To provide a method for designing a layout of semiconductor integrated circuit device by which changing of layout is easy, a return of design is small, and a change of circuit is highly possible by a repair cell. SOLUTION: In this method for designing a layout, a timing analysis is conducted on the basis of the length of virtual wiring which is estimated according to the result of arrangement or schematic wiring, and the net list is changed among a passage not satisfying the timing limit, a passage of signal transmission time close to the timing limit, and a passage of signal transmission time close to the signal hold time for flipflop assuming that every passage violates. A difference between nets after and before changed is used as a repair cell, and it is arranged adjacent to a cell belonging to the net before changed.

Description

DETAILED DESCRIPTION OF THE INVENTION

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a layout design method for a semiconductor integrated circuit device, and more particularly to a layout design method for a semiconductor integrated circuit device in which layout design and its change are easy.

[0002]

2. Description of the Related Art In recent years, miniaturization and high integration of semiconductor integrated circuits have progressed, and the signal transmission time of wiring has become dominant over the signal transmission time inherent in standard cells.

For this reason, in the wiring process in the layout design, the wiring laid according to the netlist becomes longer than the wiring length predicted when the netlist is generated, and may violate the timing constraint of the required specification.

In order to solve such a timing violation, a layout design method for a semiconductor integrated circuit device, which is generally widely known as an ECO (Engineering Change Order), has been proposed.

Hereinafter, an example of a conventional layout design method for a semiconductor integrated circuit device using an ECO will be described with reference to the drawings. FIG. 2 is a flowchart showing a conventional layout design method of a semiconductor integrated circuit device using ECO. Here, the netlist generation step 201
, A netlist is generated using the wiring length predicted based on the wiring length information of the past layout. Then, a layout of the semiconductor integrated circuit device is generated by performing the placement step 202 and the wiring step 203 according to the generated netlist. Next, the timing analysis step 20
In 4, the timing analysis is performed by extracting the load capacitance of each signal wiring from the result of the wiring step 203.

When there is no violation of the timing constraint, a mask forming step 205 for generating a mask of the semiconductor integrated circuit device
Proceeding to the subsequent processing, a semiconductor integrated circuit device is generated. If there is a timing constraint violation, an ECO process is performed in the ECO step 206. More specifically, in the netlist change step 207, the drive capability, net shape, and load capacity driven by the standard cell belonging to the path in which the timing constraint violation has occurred are evaluated, and the timing constraint is determined based on the evaluation result. Change to a netlist that can be satisfied. And layout modification process 2
In step 08, while maintaining the layout shape before the change of the netlist as much as possible, only the difference between the net before the change and the net after the change is corrected in the arrangement and the wiring. Then, the timing analysis is performed again in the timing analysis step 204, and if there is a timing constraint violation, the ECO step 206 is repeated.

In this way, with a small design rework,
A layout in which the driving capability of each cell and the wiring are balanced is obtained.

However, the ECO cannot correct a circuit change after the mask is formed in the semiconductor integrated circuit device.

To cope with this point, the following layout design method for a semiconductor integrated circuit device has been proposed. That is, in order to correct timing constraint violations, design changes, etc. found after the start of layout design or during the formation of a diffusion layer mask of a semiconductor integrated circuit device, a circuit change that may occur later is predicted at the circuit design stage. Then, spare standard cells required for circuit correction are inserted into the layout in the placement step. When the circuit needs to be modified, the circuit is modified only by the inserted spare standard cells and wiring.

[0010] The spare standard cells are generally called repair cells or bonus cells. Hereinafter, in this specification, this spare standard cell is referred to as a repair cell.

An example of a layout method of a conventional semiconductor integrated circuit device using a repair cell will be described below with reference to the drawings. In a conventional layout method of a semiconductor integrated circuit device using a repair cell, the repair cell does not have connection information with any net existing in the net list. For this reason, it is difficult for the automatic placement algorithm to determine the optimal placement position of the repair cell. Therefore,
As shown in FIG. 3A, the repair cells are arranged on both right and left ends of the layout, and as shown in FIG. 3B, the repair cells are arranged randomly and arranged in the entire layout.

[0012] By inserting the repair cell, the circuit can be changed only by the wiring, so that the rework of the design can be reduced. Further, since the design can be changed up to the stage before forming the mask of the wiring layer of the semiconductor integrated circuit device, the verification process and the wiring correction process of the designed circuit are performed by forming the mask of the diffusion layer of the semiconductor integrated circuit device. This can be performed in parallel with the process, and the design time can be reduced.

Further, even if a circuit change occurs after all the masks of the semiconductor integrated circuit device are formed, the circuit can be corrected only by forming the mask of the wiring layer again, so that the cost loss of mask formation can be suppressed. .

[0014]

However, the ECO
Then, as shown in FIG. 4, a new standard cell is added due to a circuit change, or a standard cell having a larger area than the standard cell before the change is used.
The arrangement position of the standard cell around the path or net whose circuit has been changed by the CO is moved. For this reason, it is necessary to correct the wiring of the net having a connection with the standard cell whose arrangement position has been moved and the wiring around the net.

In recent large-scale and highly-integrated semiconductor integrated circuit devices, a large number of standard cells are moved due to a circuit change, thereby increasing the number of wiring correction man-hours or performing wiring without all wiring corrections. In some cases, significant design rework such as returning to the process and making layout corrections may be required. In addition, a path that did not cause a timing constraint violation before the circuit change causes a timing constraint violation due to a change in the arrangement position of the standard cell or the wiring path after the wiring is corrected by the ECO, and the repetition of the ECO increases, In some cases, it may become out of control as the process is repeated, and it may be necessary to go back to the circuit design and make a change.

In a conventional layout design method for a semiconductor integrated circuit device using repair cells, there is no dependency between the path or net and the arrangement of the repair cells. There is a case where the circuit cannot be changed even though the repair cell is not located at a necessary place and a repair cell is inserted. The layout design method using repair cells not only increases the TAT due to significant design rework, but also causes a cost loss when the design rework is performed in parallel with the formation of the mask of the semiconductor integrated circuit device. growing. In this regard, by inserting a large number of repair cells having various functions, the possibility of circuit correction can be improved, but in that case, the area of the semiconductor integrated circuit device increases.

In a conventional layout design method of a semiconductor integrated circuit device using repair cells, a net before change and a net after change are manually compared to find a repair cell necessary for circuit change from the layout and change the repair cell. There must be.

The present invention has been made in view of the above problems, and provides a layout design method for a semiconductor integrated circuit device in which a layout change is easy, a design rework is small, and a circuit is likely to be changed by a repair cell. .

[0019]

In order to solve the above problems, a layout design method for a semiconductor integrated circuit device according to the present invention performs a timing analysis based on a virtual wiring length predicted from an arrangement or a schematic wiring result. Extracting, from the result of the timing analysis, at least one of a path that does not satisfy the timing constraint, a path having a signal transmission time close to the timing constraint, and a path having a signal transmission time close to the signal holding time of the flip-flop. Analyze the cause of the violation for the extracted path, and change the netlist assuming that each extracted path causes a timing constraint violation and a flip-flop signal retention time violation. The step of generating a repair cell from the difference between the standard cell and the net of the Characterized in that it comprises a step of disposing in the vicinity of the cell belonging to Tsu and.

In this way, cells required for circuit correction are arranged at required locations, so that layout change is easy, design rework is small, and the possibility of circuit correction by repair cells can be improved. become.

[0021]

According to the first aspect of the present invention, a timing analysis is performed based on a virtual wiring length predicted from a result of placement or schematic wiring, and a path not satisfying a timing constraint is determined from the result of the timing analysis. Extracting at least one of a signal transmission time path close to the timing constraint and a signal transmission time path close to the flip-flop signal holding time; analyzing a cause of a violation of the extracted path; Generating a repair cell from a difference between standard nets of a net after change and a net before change, assuming that each of the specified paths causes a timing constraint violation and a signal retention time violation of a flip-flop, respectively. And arranging the generated repair cells near cells belonging to the net before the change.

In this way, cells required for circuit correction are arranged at required locations, so that layout change is easy, design rework is small, and the possibility of circuit correction by repair cells can be improved. become.

According to a second aspect of the present invention, in the step of generating a repair cell, for a circuit change that cannot be predicted from a netlist, such as a design change that may occur later, the circuit change that may occur later To generate repair cell information required for circuit change.

In this way, repair cells can be prepared not only for paths having problems due to timing constraints, but also for circuit changes that cannot be predicted from the netlist.

According to a third aspect of the present invention, in the step of generating a repair cell, if there is a candidate for a net in which a circuit change that cannot be predicted from a net list may be performed later, the net is changed. The information of the repair cell is generated based on the difference between the net after the change and the net before the change.

In this case, repair cells can be prepared not only for paths having problems due to timing constraints, but also for circuit changes that cannot be predicted from the netlist.

According to a fourth aspect of the present invention, for a net whose circuit change cannot be predicted from the net list, the repair cells are arranged at the end of the circuit layout or arranged so as to be uniformly distributed over the entire circuit. Things.

By doing so, it is possible to appropriately arrange repair cells that are difficult to determine the optimal arrangement position because they correspond to circuit changes that cannot be predicted from the netlist.

An embodiment of the present invention will be described with reference to the drawings. FIG. 1 is a flowchart of a layout design method for a semiconductor integrated circuit device according to an embodiment of the present invention.

In the net list generation step 101,
Similar to the conventional netlist generation step, a netlist is generated using the wiring length predicted based on the wiring length information of the past layout. In the next placement step 102, as in the conventional placement step, the netlist generation step 1
The arrangement is performed according to the netlist generated in step S01.

In the subsequent timing analysis step 103 using virtual wiring, based on the placement result of the placement step 102 and the netlist, the wiring length can be accurately determined from the placement result of a generally known “Stainer tree model” or the like. The virtual wiring length of each net is obtained by including a margin in consideration of wiring expansion such as the movement of a standard cell due to the insertion of a repair cell, to the virtual wiring length obtained from the algorithm for estimating. Then, timing analysis is performed using the obtained virtual wiring length, and a path that does not satisfy the timing constraint, a path that has a signal transmission time that is close to the timing constraint, and a path that has a signal transmission time that is close to the signal holding time of the flip-flop are extracted.

In the subsequent repair cell generation step 104, the cause of the violation may be determined because each path extracted in the timing analysis step 103 using virtual wiring does not satisfy the timing constraint or does not satisfy the signal holding time of the flip-flop. Is analyzed. Then, the nets are changed so that each extracted path can improve the timing constraint violation and the flip-flop signal holding time violation, and the standard cell difference between the net after the change and the net before the change is repair cell of each net. To generate repair cell information.

At the stage of the repair cell generation step 104, a circuit change such as a design change that cannot be predicted from the netlist occurs later, similarly to the conventional layout design method of a semiconductor integrated circuit device using repair cells. By predicting a possible circuit change, information on a repair cell required for the circuit change is generated.

At the stage of the repair cell generation step 104, if there is a candidate for a net in which a circuit change that cannot be predicted from the net list may be made later, the net is changed, and the net after the change and the net before the change are changed. May be used as a repair cell for each net to generate repair cell information.

In the next repair cell arrangement step 105,
For a net whose circuit change can be predicted from the net list at the stage of the repair cell generation step 104, the repair cell generated in the repair cell generation step 104 is placed in or near a region having the maximum and minimum coordinates of the standard cell belonging to the net before the change. Deploy.

At the stage of the repair cell generation step 104, a net whose circuit change cannot be predicted from the net list is placed at the end of the circuit layout in the same manner as in the conventional layout design method of a semiconductor integrated circuit device using repair cells. Or evenly distributed throughout the circuit.

If a repair cell is generated in the repair cell generation step 104 to divide the fan-out number of a net having a large fan-out number, the repair cell is arranged near the standard cell to be divided, and the driving capacity is reduced. When a repair cell that replaces a higher standard cell is generated, the repair cell is placed near the standard cell to be replaced, and the number of fanouts is small but the placement of standard cells belonging to the net is dispersed. If a repair cell that divides the wiring is generated because the wiring of the net predicted from the placement result is too long, the repair cell is placed near the center of the area having the maximum and minimum coordinates of the standard cell belonging to the net before change If the placement position of the repair cell is further limited, for example, by placing The wire fixes in positive step 109 can be performed easily.

In the subsequent wiring step 106, wiring is performed according to the net list generated in the net list generating step 101, as in the conventional wiring step.

After completion of the wiring step 106, a mask forming step 107 of the semiconductor integrated circuit device and a timing analysis step 108 based on the result of the wiring step 106 are performed in parallel. If there is no path that causes a timing violation in the timing analysis step 108, the process proceeds to the mask formation step 107. If there is a path that causes a timing violation, a repair cell generation step 1
The information of the repair cell inserted in 04 and the arrangement information of the repair cell arranged in the repair cell arranging step 105 are extracted, and the process proceeds to the wiring correcting step 109.

In the wiring correction step 109, the layout is corrected only by the wiring using the extracted repair cell information necessary for the circuit change and the repair cell arrangement information. Then, the process returns to the timing analysis step 108.

As for a circuit change that cannot be predicted from the netlist, such as a design change, a repair cell required for the circuit change is manually searched for and changed in the same manner as in a conventional layout design method of a semiconductor integrated circuit device using a repair cell. A repair cell inserted corresponding to a circuit change that can be predicted from the netlist and not used for the circuit change may be used for a circuit change that cannot be predicted from the netlist.

In the present embodiment, the timing analysis step 103 using virtual wiring is performed after the placement step 102. However, this may be performed after general wiring is performed. Then, by performing the rough wiring, the timing analysis can be performed using the virtual wiring length closer to the wiring length of the actual wiring process 106 than the wiring length estimated from the placement result, so that more optimal functions and driving capabilities are provided. Repair cells can be inserted.

[0043]

As described above, according to the present invention, a timing analysis is performed based on a virtual wiring length predicted from a result of placement or schematic wiring, and a path that does not satisfy the timing constraint and a signal transmission close to the timing constraint are performed. For the time path and the signal transmission time path close to the signal holding time of the flip-flop, the netlist is changed assuming that each path causes a violation, and the net after the change and the net before the change are changed. By placing the difference as a repair cell in the vicinity of the cell belonging to the net before the change, the cell necessary for circuit correction can be placed at a necessary place, and therefore, the layout can be easily changed and the design can be easily changed. Rework can be reduced, and the possibility of circuit repair by a repair cell can be improved. Also, you can place as many cells as you need for timing correction where you need them,
The number of repair cells inserted into the circuit can be reduced.

[Brief description of the drawings]

FIG. 1 is a flowchart of a layout design method for a semiconductor integrated circuit device according to an embodiment of the present invention.

FIG. 2 is a flowchart of a conventional layout design method for a semiconductor integrated circuit device using an ECO.

FIG. 3 is a diagram for explaining a conventional repair cell arrangement method.

FIG. 4 is a diagram for explaining a problem of a layout design of a conventional semiconductor integrated circuit device using an ECO.

Claims (4)

[Claims] 1. A layout design method for a semiconductor integrated circuit device, comprising: performing a timing analysis based on a virtual wiring length predicted from an arrangement or a schematic wiring result; and determining a path not satisfying a timing constraint from the result of the timing analysis. And extracting at least one of a signal transmission time path close to the timing constraint and a signal transmission time path close to the flip-flop signal holding time. Analyzing the cause of the violation of the extracted path and extracting Generating a repair cell from a difference between standard nets of a net after change and a net before change, assuming that each of the specified paths causes a timing constraint violation and a signal retention time violation of a flip-flop, respectively. And arranging the generated repair cells near cells belonging to the net before the change. A layout design method for a semiconductor integrated circuit device. 2. A circuit change that cannot be predicted from a netlist, such as a design change that may occur later, in the step of generating a repair cell. 2. The layout design method for a semiconductor integrated circuit device according to claim 1, wherein information on a required repair cell is generated. 3. In the step of generating a repair cell, if there is a candidate for a net in which a circuit change that cannot be predicted from a net list may be made later, the net is changed, and the net after the change and the net before the change are changed. 2. The layout design method for a semiconductor integrated circuit device according to claim 1, wherein the repair cell information is generated based on a difference from the net. 4. The repair cell for a net whose circuit change cannot be predicted from the net list is arranged at an end of a circuit layout or arranged so as to be uniformly distributed throughout the circuit. Or a layout design method for a semiconductor integrated circuit device according to item 3.