JPH07120296B2 - Error control method in hot standby system - Google Patents

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to an error control system in a hot standby system composed of a plurality of multiprocessor systems.

[0002]

2. Description of the Related Art In the conventional error control system of this kind, when a failure in which an instruction can be retried occurs, an error is avoided by a processor relief function of a multiprocessor system, and continuous operation is possible as it is. In this way, the failed processor is disconnected from the system.

[0003]

In the error control method in the above-mentioned conventional hot standby system, a failure occurs which is a target of system switching in the active system, system switching is performed, and the standby system becomes the active system. Even if the system is operating, if a failure that can be retried by an instruction occurs, the processor relief function disconnects the failed logical unit. There is a problem in that they may be in an equivalent state, which significantly reduces the reliability of the system.

[0004]

The error control method of the present invention is an error control method in a hot standby system in which a plurality of multiprocessor systems are mutually connected and each is operated as an active system or a standby system.
Each processor constituting the multiprocessor system holds a system mode holding means for holding information indicating whether it is an active system or a standby system, and transfers the contents of the processor to another normal processor when an instruction retryable error occurs. In the case where an instruction retryable error has occurred in one of the processors, including the means for taking over the processing, if the content of the system mode holding means is "standby system mode", the error has occurred. The processor retries the instruction, and "in the active mode, the contents of the processor in which the error has occurred are transferred to another normal processor to continue the processing.

[0005]

DESCRIPTION OF THE PREFERRED EMBODIMENTS Next, the present invention will be described with reference to the drawings.

Referring to FIG. 1 showing a first embodiment of the present invention, the present embodiment shows a two multiprocessor system 1
2 are connected by an inter-system connection path 3, and the multiprocessor system 1 is a hot standby system in which the multiprocessor system 1 is operated as an active system and the multiprocessor system 2 is operated as a standby system.

Each of the multiprocessor systems 1 and 2 is composed of two logical units (hereinafter referred to as CPU), and in the active multiprocessor system 1, the CPU 1
In the multiprocessor system 2 of 0 and 11, the standby system, the CPU 20 and 21 are included. Also, 12
And 22 are OSs that control the entire system, 13 and 23 are CPs of the CPUs 10 and 11 and the CPUs 20 and 21, respectively.
It is a U-to-U connection path.

The CPU 20 has an arithmetic unit 200 for controlling the entire arithmetic operation, an error detection 203 for detecting an error, an error control unit 201 for judging the contents of the error and performing a processor relief function which is a well-known technique, and an OS at the time of startup. The system mode holding means 204 holds the information about the set "active system" or "standby system". Other CP
U10, 11 and 21 have the same configuration. Therefore, regarding the operation in the multiprocessor system,
The operations of both the active system and the standby system will be described using the CPUs 20 and 21.

Although not shown in the figure, I / O system devices which the system normally has are provided with file devices, line devices, etc., some of which are commonly used as a hot standby system. ing.

The error control in this embodiment is performed as follows.

When an error occurs in the CPU 20, it is detected by the error detection unit 203 and then the error control unit 201.
Will be notified to that effect. The error control unit 201 determines whether the notified error is an instruction retry, and reads the system mode from the system mode holding unit 202.

The system mode holding means 202 holds information indicating "active system mode" or "standby system mode" when the system is started up. If the read result is the "current system mode", the processor relief function causes the CP
The information required via the U-to-U connection path 23 is one CPU
The data is read from the CPU 20 to the other CPU 21, the processing of the previous CPU 20 is taken over as it is, and the operation is continued as it is. However, in the case of the “standby system mode”, the error control unit 201 does not use the processor relief function, but instructs the arithmetic unit 200 to retry the instruction and controls to continue the operation. .

Next, when a failure that is the target of system switching occurs in the active multiprocessor system 1, a down notification is sent to the OS 22 of the standby multiprocessor system 2 via the intersystem coupling path 3. Done. O
In S22, the resources shared with the multiprocessor system 1 are incorporated, recovery processing is performed, the processing of the multiprocessor system 1 is taken over, and the system operation is resumed as the active system. At this time, the OS 22 notifies the error control units 201 and 211 that the active system is down.

When the multiprocessor system 2 is operated in this state and an error occurs in the CPU 20, the error processing in the multiprocessor system as described above is performed. Now, since the "standby system mode" is set in the system mode holding means 202, the error control unit 201 does not use the processor relief function but instructs the arithmetic unit 200 to retry the instruction.

Referring to FIG. 2 showing a second embodiment of the present invention, the present embodiment is different from the first embodiment in that timer circuits 207 and 217 for clocking and outputting a signal at fixed time intervals are provided. Error number counting means 204, 214 for counting the number of errors within a fixed time, and threshold value holding means 2 for holding a threshold value for the number of errors within a fixed time
05, 215 and error number counting means 204, 21
4 and threshold value holding means 205, 215 and monitoring means 206, 216 for judging the magnitude of the contents are added.

In the present embodiment, error control is performed when an active system failure occurs in the active multiprocessor system 1 and the standby multiprocessor system 2 is operated as the active system. Different from the first embodiment.

That is, the CPU of the active system (standby system 0)
If an error occurs in 20, the error detection unit 2
When an error is detected by 03, the error control unit 201
Is notified to that effect, the error control unit 201 determines whether the error is an instruction retry, and further, the system mode holding unit 20.
Read the contents of 2. Since the content of the system mode holding means is the "standby system mode", error control is performed as follows.

First, the error control unit 201 includes the monitoring means 2
It is checked whether or not there is a notification from 06. The monitoring means 206 reads the contents of the threshold value holding means 205 and the error number counting means 204 and compares the contents. If the content of the error number counting means 204 is larger, errors frequently occur. It is determined that the error is present and the error control unit 201 is notified of that fact.

If there is no notification from the monitoring means 206, the error control unit 201 determines that an error does not occur frequently, instructs the operation unit 200 to retry the instruction, and the CPU 20 directly. Continue processing. But,
When notified by the monitoring unit 206, the processor relief function causes the CPU 21 to continue the operation of the CPU 20.

According to the present embodiment, even when the standby system is operated as the active system, even if an error that can be retried occurs, the error is not immediately corrected by the processor as error control, but the error is recovered. As a hot standby system operation, there is an effect that a system with higher performance and higher reliability can be realized.

[0021]

As described above, according to the present invention, in a hot standby system in which the system load is heavy in operation, the active system goes down and the standby system is operated as the active system, and the When a trialable error occurs, the processor in which the error has occurred performs the instruction retry, so that there is an effect that a high-performance and highly reliable system can be realized.

[Brief description of drawings]

FIG. 1 is a system configuration diagram of a first embodiment of the present invention.

FIG. 2 is a system configuration diagram of a second embodiment of the present invention.

[Explanation of symbols]

 1, 2 multiprocessor system 3 system coupling path 10, 11, 20, 21 CPU 13, 23 CPU coupling path 12, 22 operating system 200, 210 arithmetic unit 201, 211 error control unit 202, 212 system mode holding means 203 , 213 Error detection section 204, 214 Error number counting means 205, 215 Threshold value holding means 206, 216 Monitoring means 207, 217 Timer circuit

Claims (2)

[Claims] 1. An error control method in a hot standby system in which a plurality of multiprocessor systems are connected to each other and each is operated as an active system or a standby system, wherein each processor forming the multiprocessor system is an active system. One of the processors includes a system mode holding means for holding information indicating a standby system, and a means for transferring the contents of the processor to another normal processor when an error in which an instruction can be retried occurs and taking over the processing. If an error that can be retried by an instruction occurs, and the content of the system mode holding means is "standby system mode", the processor in which the error has occurred retries the instruction and In this case, transfer the contents of the processor in which the error occurred to another normal processor and continue the processing. Error control method in hot standby system to butterflies. 2. A timer circuit for each processor of the multiprocessor system, an error number counting means for counting the number of error occurrences output by the timer circuit at a constant time, and an upper limit of the number of error occurrences within the constant time. A threshold value holding means for holding a value, and a monitoring means for comparing the contents of the error number counting means and the threshold value holding means are added, and in one of the processors, an instruction retryable error occurs. When the error occurs, the processor in which the error has occurred only when the content of the system mode holding means is the "standby system mode" and the content of the error number counting means is smaller than the content of the threshold value holding means. And retry the instruction.In other cases, the contents of the processor in which the error has occurred are returned to the other normal process. Transferred to processor, the error control method in hot standby system of claim 1 wherein characterized in that to continue processing.