JPS6143739B2 - - Google Patents

Description

DETAILED DESCRIPTION OF THE INVENTION The present invention relates to a logical device in an information processing system, and more particularly to a multiplexed logical device system.

Logic devices with traditional instruction retry functionality (hereinafter referred to as
When an error occurs while executing an instruction, the CPU itself determines whether or not the instruction can be retried, and if it is possible to retry the instruction, it retries the instruction. Error recovery has been attempted. However, this method has the disadvantage that if an error occurs due to a fixed failure, it cannot be recovered even if it can be retried.

A configuration for solving this problem in a system with a multiple CPU configuration is disclosed in ``Japanese Patent Laid-Open No. 55-87251.'' According to this suggestion an error occurred
A third processing device separate from the CPU transfers CPU instruction retry status information as is to a normal CPU where no error has occurred, and the processing on the CPU where the error has occurred is carried out by the normal CPU. This solves the problem mentioned above. However, this system requires a third processing device separate from the CPU, and in order to guarantee the continuity of processing on the normal CPU, it is not possible to take over instantly at any point. The drawback was that it required processing to wait for the takeover until the state was reached.

An object of the present invention is to provide a multi-CPU system with the above configuration, in which a normal CPU performs instruction retry control and status information readout control for an error CPU, thereby eliminating the need for a third processing device.
In order to guarantee the continuity of processing on the CPU, it is possible to process each instruction with very simple control (for example, a dispatcher implemented as a normal function), and to wait for processing to take over. It is an object of the present invention to provide a multiple logic device which solves the drawbacks of conventional systems and can completely recover from errors if instructions can be retried.

In order to achieve the above object, a multiple logical device system according to the present invention includes a plurality of logical devices and at least one storage device shared by these logical devices. an instruction execution control circuit, an error detection circuit that detects an error occurring in the execution control circuit, and stops the operation of the execution control circuit when detected; and an error detection circuit that detects the error detected by the error detection circuit, and a notification circuit that notifies a logic device; and a readout that controls the other logic device to read and write the internal state of the stopped execution control circuit;
It consists of a write control circuit and a receiving circuit that receives an error notification from the notification circuit of another logic device, and when an error occurs in a logic device, the normal In response to the receiving circuit output of the logic device, the instruction execution control circuit of the normal logic device controls the instruction retry of the logic device in which the error has occurred, and as a result, if the instruction retry is unsuccessful, an error is generated. The control information necessary for resuming the interrupted processing of the normal logical device is written into the storage device from the state information of the logical device that has been suspended.

According to the above configuration, the conventional third processing device can be omitted, the continuity of processing on a normal CPU can be guaranteed by simple control, and queuing processing is no longer necessary, and the object of the present invention is completely achieved. will be achieved.

Hereinafter, the present invention will be explained in more detail with reference to the drawings.

FIG. 1 is a diagram showing an embodiment of the present invention. In FIG. 1, the configuration of the present invention is a main storage device 50.
It is composed of two CPUs 10 and 20 having exactly the same structure. The CPU 10 includes an instruction execution control circuit 11 and a main memory access circuit 12 for carrying out normal processing, as well as an error detection circuit 13 for detecting errors that occur in the control circuit 11 and the access circuit 12. normal CPU when
Error notification circuit 14 for notifying error to 20
, all state information of the CPU 10 is transferred to the data path 112.
It consists of a read/write control circuit 15 that performs write/read control for the normal CPU 20 through the read/write control circuit 15. The CPU 20 also has the same configuration as the CPU 10. The main storage device 50 also has an interface 10 that can write and read between the CPU 10 and the CPU 20.
5,205, and stores control information for the minimum processing unit (hereinafter referred to as a task) processed by the CPU.

FIG. 2 is a diagram showing the structure of this task control information. In FIG. 2, the control information consists of a valid display bit V indicating the validity of the task, a task identification name storage area ID, and a CPU status control information area S, and is divided into n pieces at consecutive addresses starting from a fixed address B. area is secured. This control information is generated every time a task is generated or interrupted, and is sequentially stored toward higher addresses in the area in the order of generation. This order control is performed using pointer information stored at fixed address A. The pointer information indicates the storage address of the task control information that will be generated next.
The CPU 10 or CPU 20 reads it to know the storage location of the task control information. The CPU 10 or CPU 20 also performs update control of this pointer information. The update is performed by adding a fixed value L (V bit length + task identification name length +
This is done by adding the CPU state control information length) and re-storing it. This read and restorage process
Conflict may occur between CPU 10 and CPU 20, and exclusive control logic is used to avoid conflict. The CPU that controls the execution of the task has an area _C1 for CPU10 and an area C1 for CPU20 at the start of execution.
Register the name of the task to start execution in the running task display area consisting of area _C2 .

In a normal state, the CPU 10 and the CPU 20 perform a process _P1 in which task control information is registered in a queue, and a process _P2 in which the registered queues are sequentially retrieved and tasks are executed based on the retrieved control information. , Process P ₁ and Process P ₂ are mutually independent processes, so the task control information registered by CPU 10 is transferred to CPU 2.
0 can retrieve and execute it, or the CPU 10 itself can retrieve and execute it. either
When a CPU makes an error, other normal CPUs register task control information. Again, the CPU
10 or CPU 20, whichever is normal, can read and process the task control information.

In FIG. 1, when a failure occurs in the CPU 10, the error detection circuit 13 detects the failure and stops the instruction execution control circuit 11. Furthermore, detection circuit 1
3 activates the error notification circuit 14 and reports the normal CPU 20 via the error notification interface 102.
Report an error to . When the error receiving circuit 26 of the normal CPU 20 receives this report, it activates the instruction execution control circuit 21 and instructs the CPU 10 to start error processing. After the normal CPU 20 temporarily suspends the task it is executing, it reads the state information of the CPU 10 through the read/write control circuits 25 and 15 and stores this information in the main storage device 50. Next, the normal CPU 20 analyzes the status information of the CPU 10 stored in the main storage device 50 and determines whether the instruction can be retried. If the instruction can be retried, control information for retrying the instruction is generated from this status information, and the generated control information is set in the CPU 10 via the read and write control circuits 15 and 25. The normal CPU 20 controls the CPU startup interface 122 to start the CPU 10.
Here, processing is restarted from the instruction that was being executed when the error occurred in the CPU 10.
If the command retry is successful here, processing continues as is. Conversely, if the command retry is unsuccessful,
The error detection circuit 13 of the CPU 10 detects the error again, and the instruction execution control circuit 2
1 is notified of the error. A normal CPU20 is
Immediately after starting the CPU 10 from the CPU startup interface 122, you will receive an error notification again.
The command retry is determined to be unsuccessful. At this time, normal
CPU20 is the CPU1 that was read when the error occurred first.
Processes the state information of 0 and generates CPU state control information. Status control information is CPU during normal operation.
It is exactly the same type as that generated by CPU 10 and CPU 20. Furthermore, the normal CPU 20 accesses the main memory 50 and reads the identification name of the task that the CPU 10 was executing at the time of the error from the fixed address C1 shown in FIG. ₂ , and the pointer information from the fixed address A. Next, the normal CPU20 generated
Task control information obtained by adding the CPU state control information and the read task identification name with the valid display bit set to 1 is written to the main memory address indicated by the pointer information. Thereafter, the task control information length L is added to the pointer information and the result is stored again at the same address A. If the address resulting from adding L exceeds the task control information area, the initial value B is stored. The registered task control information is retrieved and processed by the normal CPU 20 in accordance with the order of the queue, in the same way as the tasks previously executed by the normal CPU 20.
When CPU10 has an error, CPU20 is normal.
If it is determined that the instruction cannot be retried, the normal
The CPU 20 accesses the main storage device 50 and
The identification name of the task that the CPU 10 was executing at the time of the error is read from the fixed address _C1 shown in the figure, and the pointer information is read from the fixed address A shown in the figure. Next, set the valid display bit to 0.
It is added to the task identification name read and written to the main memory address indicated by the pointer information. Unlike the case where the instruction retry is unsuccessful, CPU state control information is not written. The procedure for updating pointer information thereafter is the same in the case of an unsuccessful instruction retry.
When the normal CPU 20 reads the control information in which the valid display bit V is 0, it performs processing to abandon the task recorded in the task identification name ID.

In this embodiment, the case where the CPU 10 fails has been described, but it is obvious that the same process is performed even when the normal CPU 20 fails. Furthermore, although this example shows a configuration with two CPUs, the currently running task display area in the main memory
By expanding by the number of CPUs, a configuration with three or more CPUs can be easily realized.

As explained in detail above, the present invention allows other normal CPUs to transfer the status information of a CPU that has generated an unrecoverable error to the main memory, and when processing resumes, the CPU recovers while maintaining processing continuity. It has the effect of being able to do the following.

[Brief explanation of the drawing]

FIG. 1 is a block diagram showing an embodiment of a multiplexed logical device system according to the present invention, and FIG. 2 is a logical configuration diagram of information stored in the main storage device 50 shown in FIG. 10, 20... central processing unit (CPU), 11,
21... Instruction execution control circuit, 12, 22... Main memory access circuit, 13, 23... Error detection circuit, 14, 24... Error notification circuit, 15, 2
5... Read/write control circuit, 16, 26... Error receiving circuit, 50... Main storage device, 102, 202
...Error notification interface, 105,205
...Main memory access interface, 122...
CPU startup interface, 112...Data path, A...Task control information pointer storage address, B...Task control information storage start address,
C ₁ ...CPU10 running task name storage address, _C2 ...CPU20 running task name storage address, ID...task identification name storage field,
S...CPU status control information storage field, V...
...Task valid display bit.

Claims (1)

[Claims] 1. In a multiple logic device system comprising a plurality of logic devices and at least one storage device shared by these logic devices, each of the logic devices is connected to an instruction execution control circuit and the execution control circuit. an error detection circuit that detects an error that occurs and stops the operation of the execution control circuit when detected; a notification circuit that notifies the other logic device of the error detected by the error detection circuit; and the execution control circuit that has stopped. A certain logic device comprises a read/write control circuit that controls the internal state of the circuit so that it can be read and written from the other logic device, and a receiving circuit that receives error notification from the notification circuit of the other logic device. When an error occurs in the logic device, the instruction execution control circuit of the normal logic device responds to the receiving circuit output of the normal logic device that received the error notification from the notification circuit of the logic device, and the logic device in which the error occurred. As a result, if the instruction retry is unsuccessful, based on the status information of the logical unit where the error occurred,
A multiple logical device system, characterized in that control information necessary for resuming interrupted processing of the normal logical device is written in the storage device.