JP3033586B2 - Information processing system - Google Patents

Description

Description: TECHNICAL FIELD The present invention relates to an information processing system configured by combining a plurality of information processing devices.

[Conventional technology]

In recent years, the role of information processing systems has become more and more important, and the suspension of information processing systems has a great social impact.

Against this background, social demands on the reliability and fault tolerance of information processing systems have been strong, and 24-hour non-stop systems and fault-tolerant systems have been required.

In order to improve the reliability of an information processing system, various methods have been studied. One of the methods is to construct a system by combining a plurality of information processing devices, and when one information processing device fails. An information processing system has been constructed which continues the operation of the entire system by substituting the processing with another information processing apparatus.

FIG. 7 is a diagram showing an example of the configuration of a conventional information processing system of this type. In the system shown in FIG. 7, two information processing apparatuses 3 and 4 are connected by a communication transmission line. Each of the information processing devices 3 and 4 includes an arithmetic and control unit 20, 21, a storage unit 30, 31, a bus management unit 40, 41, an information communication unit 7, 8, and a bus 100 connecting these units. ing. The two information processing devices 3 and 4 are information communication mechanisms 7 and 8
In this information processing system, the information processing apparatus 3 and the information processing apparatus 4 usually independently perform individual processing. In the information processing device 3, the arithmetic and control unit 20 reads the control program stored in the storage unit 30, executes various processes in accordance with the procedure specified by the control program, and executes various kinds of control information in the storage unit 30 and updates. Manipulating information.

The arithmetic control processing mechanism 20 performs processing in one unit,
When the operation of the update information in the storage mechanism 30 is completed, a command is issued to the information communication mechanism 7 in order to secure the update information, and the update information in the storage mechanism 30 is transmitted to the information processing device 4 using the communication transmission path.
To the storage mechanism 31. This process is similarly performed in the information processing device 4. In this information processing system, when the information processing device 3 is stopped due to a failure, the information processing device 4 uses the information transferred from the information processing device 3 to perform the process executed by the information processing device 3 instead. ing.

FIG. 8 shows a configuration example of the information communication mechanisms 7, 8.
Referring to FIG. 8, the bus control unit 11 is connected to the bus 100, transfers information between the information communication mechanism and the arithmetic control processing mechanism or the storage mechanism, and the command control unit 71 controls the arithmetic processing mechanisms 20 and 21.
The control operation of the entire information communication mechanism is performed based on the instruction, and the information transfer control section 72 performs data transfer with the storage mechanisms 30 and 31. The control storage unit 73 includes a command control unit 71
Is a control storage circuit for storing a control procedure executed by the or a variety of work information. The connection control unit 74 is a transmission / reception circuit that performs interface control with another information processing device. FIG. 9 shows an example of a memory configuration in the storage units 30 and 31. In this example, the control unit includes a control program area, a control information area, an information area of the information processing apparatus 3, and an information area of the information processing apparatus 4. Have been. In the control program area, a control program that defines a processing procedure for the arithmetic and control processing devices 20 and 21 to perform processing is stored,
The control information area stores various types of control information that are referred to or generated when the arithmetic control processors 20 and 21 execute the control program. A command 300 indicating a command issued to the information communication mechanisms 7 and 8, a list 301, and the like are stored in the control information area. The information area of the information processing apparatus 3 is an area for storing update information to be processed by the arithmetic control processing mechanism 20, and the information in this area is also transferred to the storage mechanism 31 of the other information processing apparatus 4 for security. It is supposed to be. For example, update information 401, 402, 403, etc. generated or updated according to the processing procedure of the control program are located in this area. The information area of the information processing device 4 is used when the information processing device 4 fails.
Reference numeral 20 denotes information used when acting on behalf of the processing of the information processing apparatus 4, and is an area in which information in the storage mechanism 31 of the information processing apparatus 4 is transferred and maintained.

The arithmetic and control unit 20 performs processing based on the control program, and updates the update information 401, 402, and 403 of the information processing apparatus 3. The address information and the information amount of the updated update information 401, 402, 403 are generated as list information 301. The relationship with the storage location of the list is displayed in the command information 300.

FIG. 10 shows a command format issued to the information communication mechanisms 7 and 8 by the arithmetic control processing mechanisms 20 and 21. The device identifier is
It is used as recognition information of an arithmetic control processing mechanism that transmits the command and an information communication mechanism that receives the command and operates.
The command code and the additional information indicate an operation instruction to the information communication mechanisms 7 and 8 and the amount of information in the list. The list information indicates an address in the storage mechanism where the list is stored.

The contents of the list are composed of the information amount and the address information, and indicate the positions of the updated update information 401, 402, 403 in the storage mechanism. When the command control unit 71 of the information communication mechanism 7 receives the above-described command from the arithmetic and control processing mechanism 20, it analyzes the contents of the list, reads out updated information from the storage mechanism 30,
The information is transferred to the information processing device 4 of another system.

In the information processing device 4, the information communication mechanism 8 starts processing according to the instruction from the information communication mechanism 7, and writes the transferred transport information to the information area of the device 3 in the storage mechanism 31.

[Problems to be solved by the invention]

Although the conventional information processing system described above achieves the purpose of improving the fault tolerance of the system for the time being, it executes processing according to input / output commands as shown in FIG. 10 to control the information communication mechanism. However, there is a disadvantage that the amount of control program increases due to the complexity of the input / output command control, and that the processing performance is greatly reduced due to the definition of the communication interface for executing the input / output control.

Further, there is a danger that the information in the storage mechanism will be damaged if the address information specified by the input / output command is incorrect due to the failure of the information communication mechanism.

SUMMARY OF THE INVENTION The present invention has been made to solve the above-mentioned drawbacks, and an object of the present invention is to make it possible to easily and more efficiently maintain the storage information of a storage mechanism without deteriorating high reliability. It is to provide a processing system.

[Means for solving the problem]

In the information processing system according to the present invention, the information transfer mechanism stores the transfer information from the storage unit of the information processing device when detecting a memory transfer or a start request executed by the arithmetic control processing unit of the information processing device. Address setting means for setting an address area of the transfer information; and address determining means for determining whether or not to transfer the transfer information stored in the information storage means into the area set by the address setting means. The transfer information is transferred to the set address area when the address determination means detects that the transfer is to the memory area.

[Action]

When transferring the contents of the storage means updated in a series of processing units of one information processing device to the storage means of the other information processing device via the information transfer mechanism, the information transfer mechanism should be transferred. Since the address area of the storage means of the information processing apparatus, that is, the save area is set, and the transfer is performed only when the memory is transferred into this address area,
The transfer can be performed without disturbing the information stored in the storage means.

〔Example〕

Hereinafter, an embodiment of the present invention will be described with reference to the drawings.

FIG. 1 is a block diagram showing an information processing system according to one embodiment of the present invention. Referring to FIG. 1, the information processing system of this embodiment has two information processing devices 5 and 6. Each of the information processing devices 5 and 6 has an arithmetic control processing mechanism 20,
21, storage units 30, 31, bus management units 40, 41, information transfer unit
1 and 2, and each of these mechanisms is connected by a bus 100 in the information processing apparatus. Two information processing devices
Reference numerals 5 and 6 are connected to each other via information transfer mechanisms 1 and 2.

FIG. 2 is a diagram showing a configuration example of the storage mechanisms 30 and 31,
The storage areas of the storage mechanisms 30 and 31 are divided into six areas. Among the storage areas, the control program area, the control information area, and the information areas of the devices 5 and 6 have basically the same functions as the corresponding areas of the above-described conventional information processing system. In the example information processing system, start information 302 and reply information 3 are provided in the control information area as information transmission means between the arithmetic control processing mechanisms 20 and 21 and the information transfer mechanisms 1 and 2.
03, status information 304 and area setting information 305, 306, 307, 3
08 is newly set. Further, a save area for the devices 5 and 6 is newly set in the storage area. This save area is the update information 401, 402, 403, 404, 40 in the information area.
This area stores copy information 501 to 505 or save information 601 to 605 of No. 5 and is used to secure data integrity of update information.

FIG. 3 is a configuration diagram of the information transfer mechanisms 1 and 2, and the information transfer mechanisms 1 and 2 have the same configuration. The information transfer mechanism 1 will be described below for simplicity.

The information transfer mechanism 1 is connected to an internal bus 100 in the information processing device via a bus control unit 11. Bus control unit 11
Is configured to transfer information with the arithmetic control processing mechanism 20 or the storage mechanism 30 via the bus 100. The operation of the entire information transfer mechanism 1 is controlled by the processing control unit 12. When the processing control unit 12 detects a memory transfer or activation request executed by the arithmetic control processing unit 20 based on a signal from the bus control unit 11, the processing control unit 12 executes Necessary information in the information is stored in the read address / data storage units 19a, 19b, and 19c.
The processing control unit 12 drives the output transfer control unit 14 according to the prescribed procedure, selects the information selection control unit 17, and stores the data stored in the address / data storage units 19a, 19b, and 19c to another system. The information is transmitted to the information transfer mechanism 2.

The transfer information transmitted from the information transfer mechanism 2 of the other system is received by the input transfer control unit 15 via the transmission path and is stored in the information storage unit.
When the input transfer control unit 15 receives an instruction from the information transfer mechanism 2 of another system, the processing control unit 12
The transport information stored in the address data storage unit
19d, and via the information selection control unit 17, the bus control unit 1
Send to one. The bus control unit 11 controls the bus 100 according to the address information, and performs a write operation to a save area in the storage mechanism. Address setting units 18a, 18b, 18
c and 18d are register circuits for storing area information, address setting sections 18a and 18b indicate address areas where the bus control section 11 receives information from the bus 100, and the address setting section 18a is the minimum address address and the address setting section. 18b stores the maximum address. The address information stored in the address / data storage unit 19a is compared with the address values of the address setting units 18a and 18b by the address discriminating unit 16, and the comparison result is notified to the processing control unit 12.
The output control is performed by the comparison result notification signal from 16. Similarly, the address setting units 18c and 18d indicate an address area when the information transfer mechanism writes to the storage mechanism,
The address setting section 18c stores the minimum address, and the address setting section 18d stores the maximum address. Information storage unit 1
When the address information is read from 3 to the address / data storage unit 19d, the address values of the address setting units 18c and 18d are compared by the address discrimination unit 16, and the comparison result is obtained by the processing control unit 12.
, And the process control unit 12 performs input control based on a comparison notification signal from the address determination unit 16.

FIG. 4 shows that the two information processing devices 5 and 6 have the information transfer mechanisms 1 and 2
FIG. 6 is a block diagram showing a connection relationship when the connection is made by using.

Referring to FIG. 4, the output transfer control section 14 of the information transfer mechanism 1 is connected to the input transfer control section 15 of the information transfer mechanism 2 via a transmission line 200, and similarly, the output transfer control section 14 of the information transfer mechanism 2 Reference numeral 14 is connected to the input transfer control unit 15 of the information transfer mechanism 1 via the transmission line 210.

Next, the operation of the information processing system having such a configuration will be described in the fifth.
This will be described with reference to FIGS.

FIG. 5 is a conceptual diagram showing the correlation of the storage information between the storage mechanism 30 and the storage mechanism 31, and FIG.
4 is a flowchart showing the operations of 20, 21 and information transfer mechanisms 1 and 2. First, referring to FIG. 5, the arithmetic and control unit 20 executes the control program of the storage mechanism 30, and updates the update information 401, 402, 403 in the information area. Arithmetic control processor 20
Verifies the status information 304, and if the information transfer mechanisms 1 and 2 are available, performs at least one memory transfer operation and copies the contents of the update information 401, 402 and 403 to the copy information 501, 502 and 503.
Transfer to The setting of the evacuation area is defined in advance by the control program, and in FIG.
Indicates the start address of the save area of the device 5 and the area information 702, 70
6 indicates the end address of the save area of the device 5. Similarly, the area information 703, 707 indicates the start address of the save area of the device 6, and the area information 704, 708 indicates the end address of the save area of the apparatus 6. These area information 701 to 704 or area information 705 to 708 are set in advance in the area setting information 305 to 308 in the control information area of FIG. Is notified that the operation control processing mechanisms 20 and 21 write the activation information 302. In FIG. 5, when the memory transfer operation is performed, the information transfer mechanism 1
Verify whether or not the writing is to the save area defined by the area information 701 and the area information 702. If the memory transfer is to an out-of-specification area, the information transfer mechanism stops without performing any processing. When the memory is to be transferred into the prescribed area, the information transfer mechanism 1 updates the update information 401, 402, 403 with the copy information 501, 50.
The transfer information is extracted from the bus 100 when the data is transferred to the memory 2,503. After that, upon activation from the arithmetic control processing mechanism 1, it is verified that the area information 705 and the area information 706 of the storage mechanism 31 have been transferred into the save area, and the transfer is made again to the save information 601 to 603. Similarly, the update information 404, 405 in the storage mechanism 31 is transferred to the copy information 504, 505 and the save information 604, 605. In this manner, the update information in the storage information 30 and the update information in the storage mechanism 31 are mutually held as save information of another storage mechanism. For this reason, even if one of the information processing apparatuses, for example, the information processing apparatus 5 fails, the arithmetic control processing mechanism 21 of the information processing apparatus 6 performs the processing in the information processing apparatus 5 using the evacuation information 601, 602, and 603 of the apparatus 5 in the storage mechanism 31. It becomes possible to replace the processing that has been performed.

Next, referring to FIG. 6, the arithmetic and control unit 20 stores, in the area setting information 305, 306, 307, 308, area information 701, 702, 703, 70 indicating the start address and end address of the save area, respectively.
4 is set (step S1), the instruction information is written into the startup information 302 (step S2), and the information transfer mechanism 1 is notified. When the information transfer mechanism 1 detects the activation (step S3), the area information 701, 702, 703, 704 is read from the area setting information 305, 306, 307, 308 and registered in the address setting units 18a to 18d (step S3).
Four). Thereafter, reply information 303 is generated (step S
5), the completion of the processing is notified to the arithmetic control processing mechanism 20, and the information transfer mechanism 1 waits for the next activation. The arithmetic control processing mechanism 20 detects the completion of the processing from the reply information 303 (step S
6) After generating the update information 401, 402, 403 (step S
7) Investigate the status information 304 (step S8).

If the information transfer mechanism 1 is available in the status information 304, the arithmetic and control unit 21 transfers the update information 401, 402 and 403 to the copy information 501, 502 and 503 by memory (step S9). The information transfer mechanism 1 detects the memory transfer operation via the bus 100 (step S10), and sets the preset area information 701, 702.
(Step S1)
1) If the information is within the area, the transfer information is automatically extracted from the bus 100 and transferred to the information transfer mechanism 2 of the information processing device 6 (step S12). The transferred transport information is temporarily stored in the information storage unit 13 of the information processing device 6 (step S1).
3). When completing the memory transfer (step S14), the arithmetic and control unit 20 writes the instruction information in the activation information 302 (step S15). This write operation is detected by the information transfer mechanism 1 (step S16), and reply information 303 is generated (step S17). Upon receiving the reply information 303 (step S18), the arithmetic and control unit 20 completes one process and starts the next process (step S19).
Is executing the next process, the information transfer mechanism 1 instructs the information transfer mechanism 2 to read the transport information stored in the information storage unit 13 (Step S20). After verifying that the information is the transfer information to the area defined by the area information 706, 706 (step S21), the information transfer mechanism 2 writes the information into the save area of the storage mechanism 31 and saves the save information 601, 602, 60.
3 is generated (step S22). After detecting the completion of the processing in the information transfer mechanism 2 (step S23), the information transfer mechanism 1
The status information 304 is generated (step S24), and the process returns to step S10 to wait for the next activation from the arithmetic and control unit 20.

By performing the processing in this manner, the input / output command used for the information communication mechanism by the conventional arithmetic control processing mechanism is not required, and the processing is speeded up.

In other words, in the case of input / output instruction processing, many control program procedures and management information for executing instructions are required,
Although the overhead was large for the arithmetic and control unit, the adoption of this method allows the arithmetic and control unit to use the information transfer mechanism with a simple procedure such as memory transfer to the storage unit and writing of start-up information. Becomes

〔The invention's effect〕

As described above, according to the present invention, when a memory transfer is performed from one information processing device to another information processing device, the transfer is performed only when the memory transfer is within a predetermined address area. Is provided in the information transfer mechanism, so that even if one of the information processing devices fails, the storage information in the storage means can be better protected and reliability can be improved as compared with the case where the input / output instruction is used. In addition, there is an effect that maintenance of stored information can be achieved more easily and faster than in the case of using input / output instructions.

[Brief description of the drawings]

FIG. 1 is a block diagram of an information processing system according to an embodiment of the present invention, FIG. 2 is a diagram showing a configuration example of a storage mechanism shown in FIG. 1, and FIG. 3 is an information transfer mechanism shown in FIG. FIG. 4 is a block diagram showing a connection relationship between the two information transfer mechanisms shown in FIG. 1, FIG. 5 is a conceptual diagram showing a correlation of storage information between a storage mechanism 30 and a storage mechanism 31, and FIG. FIG. 6 is a flowchart showing the processing flow of the information processing system of FIG. 1, FIG. 7 is a block diagram of a conventional information processing system, FIG. 8 is a block diagram of a conventional information communication mechanism, and FIG. 2 shown in the figure
FIG. 10 is a diagram showing an example of a memory configuration of one storage mechanism. FIG. 10 is a diagram showing a format of an input / output command issued in a conventional information processing system. In the figure, 1,2... Information transfer mechanism, 3,4,5,6... Information processing device, 7,8... Information communication mechanism, 11.
... Processing control unit, 13 information storage unit, 14 output transfer control unit, 15 input transfer control unit, 16 address discrimination unit,
17 Information selection control unit, 18a, 18b, 18c, 18d Address setting unit, 19a, 19b, 19c, 19d Address / data storage unit, 20, 21 Operation control processing mechanism, 30, 31 … Memory,
40, 41: Bus management mechanism, 71: Command control unit, 72: Memory transfer control unit, 73: Control storage unit, 74: Connection control unit, 100: Bus, 200, 210: Transmission path , 300 ... command information, 301 ... list information, 302 ... start information, 303 ... reply information, 304 ... status information, 305, 306, 307, 308
... area setting information, 401, 402, 403, 404, 405 ... update information, 501, 502, 503, 504, 505 ... copy information, 601, 602, 603, 6
04,605... Evacuation information, 701,702,703,704... Area information.

 ──────────────────────────────────────────────────続 き Continuation of front page (72) Inventor Shinichi Nomiyama 4-760, Kinuyama, Matsuyama-shi, Ehime Shikoku NEC Software Corporation (56) References JP-A-53-39029 (JP, A) JP-A-62 -113252 (JP, A) JP-A-56-143046 (JP, A)

Claims (1)

(57) [Claims] A plurality of information processing devices connected to each other by an information transfer mechanism provided corresponding to each of the plurality of information processing devices;
In an information processing system including the information transfer mechanism, and a connection unit that connects the arithmetic control processing unit, the storage unit, and the information transfer unit, the information transfer unit includes an information storage unit, an address setting unit, and an address determination unit. And a processing control unit, wherein the processing control unit sets, in the address setting unit, area information of a preset save area of the storage unit in response to a start request issued by the arithmetic control processing unit, When the arithmetic and control unit transfers the update information to the memory via the connection unit, the address determination unit determines whether or not the memory transfer is for the save area by the address setting unit. If it is determined that the memory transfer is to the inside of the save area, the processing control unit extracts transfer information from the connection unit and performs the information transfer. The transfer information is transferred to an information storage unit of another information processing apparatus coupled by a transmission mechanism, and information of the other information processing apparatus is stored in a save area set in a storage unit of the other information processing apparatus in advance. An information processing system in which save information is written by a transfer mechanism.