JPH05224964A - Bus abnormality information system - Google Patents

Abstract

PURPOSE:To inform the relative processor units in detail and at a high speed of the information of the bus abnormality occurred on a common bus with no load applied to software in a bus abnormality information system of a multiprocessor system. CONSTITUTION:A common bus 3 functions to transfer data between the processor units 1-1 to 1-N and the I/O units 2-1-1 to 2-N-z, and a bus abnormality informing line 5 is provided in parallel to the bus 3 for communication of the serial data carried out between those processor and I/O units. Each of units 2-1-1 to 2-N-z has a bus abnormality detecting part 21 which detects the bus abnormality and sends the bus abnormality information including the IDs of the units 1-1 to 1-N which control their own units to the line 5 as the serial data. Meanwhile, each of units 1-1 to 1-N has a bus abnormality recording register 12 which gives an interruption to a CPU 11 when the receiving/recording information on the bus abnormality information is addressed to its own processor unit.

Description

Detailed Description of the Invention

[0001]

BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a bus error notification system in a multiprocessor system having a plurality of processors.

In a computer system of a control system, a multiprocessor system which can achieve parallel processing and redundancy by providing a plurality of processors in response to the demands for high speed, high volume, high reliability (non-stop) of processing. It is spreading.

[0003]

2. Description of the Related Art First, a bus abnormality notification system in a single processor system will be described. As shown in FIG. 4, in a single processor system in which a processor unit 1 and a plurality of I / O units 2-1 to 2-N operating under the control of the processor are connected by a common bus 3, A bus controller unit 4 for monitoring the bus 2 and one bus abnormality notification line 5 are provided between the bus controller unit 4 and the processor unit 1. The bus controller unit 4 has a bus abnormality detection unit 41 and a bus abnormality information register 42, and when a bus abnormality occurs when the processor 1 or an I / O device operating in DMA accesses the common bus 3,
The bus abnormality detection unit 41 detects the bus abnormality,
The address parity / data parity error, etc.) and the bus status (whether the bus access when an error occurs is address or data, etc.) are recorded in the bus error register 42, and are also sent to the CPU 11 in the processor 1 via the bus error notification line 5. On the other hand, a non-maskable interrupt (NMI) is used to notify the occurrence of a bus abnormality. When the processor 1 receives this notification, the controller unit 4 through the common bus 3 by interrupt processing.
Access the bus abnormality information register 42 of
The detailed information on the bus error stored in is read, and this is analyzed to execute recovery processing and retry processing.

FIG. 5 is a block diagram of a multiprocessor system to which the present invention is applied. In a multiprocessor type control computer system, as shown in FIG. 5, a large number of I / O units 2-1-1 to 2-1-n, 2 are provided under the respective processor units 1-1 to 1-N. -2-1 to 2-2-
m, ... 2-N-1 to 2-Nq are subordinate. The dotted frame in the figure
The management area of each processor unit is shown. Further, a common memory unit 6 for storing communication data between processor units and data shared by all processor groups is provided. Here, the I / O unit is the FD
A recording unit such as D and HDD, a line corresponding unit such as HDL and LAN, and a peripheral I / O unit such as digital input / output and analog input / output. These all I / O units are processors that manage their own units. It is accessed from the unit via the common bus 3. Also, some I / O units have a DMA function of directly accessing the common memory 6 and transferring data without the need for the processor. (Hereinafter, this common memory unit is also regarded as a broadly defined I / O unit in the present specification.) Then, the I / O unit that performs bus operation by the processor unit or the I / O unit that performs the DMA operation is the common memory unit. Bus error (address parity error, data parity error, ECC error, memory parity error, etc.) that occurs when the bus is accessed must be notified to the processor that manages its own unit.

[0005]

However, if the bus abnormality notification method by the bus controller adopted in the single processor system is also adopted in the multiprocessor system shown in FIG. 5, there are the following problems.

If a bus abnormality occurs when the processor unit 1-1, which is the bus master after acquiring the right to use the bus, accesses the bus, the bus controller 4 detects the abnormality and sends an NMI to the bus abnormality notification line. But that N
The MI notification is sent to all the processors, and each processor reads the bus abnormality information from the register by software and analyzes the abnormality information before it knows whether its own processor is related to the bus abnormality. Therefore, even a processor irrelevant to the bus abnormality is subjected to interrupt processing, causing the software to perform useless processing.

When different processors continuously generate bus abnormalities, in order to record all the bus abnormality information, the bus abnormality information register in the bus controller 4 is required.
The number of 41 is the same as the number of processors, and when there are many processors, it is difficult to realize because many registers are needed.

Even when a bus error occurs when the I / O unit that performs DMA becomes a bus master, the bus controller notifies all processors of the bus error occurrence. The bus abnormality occurred in which DMA-I / O managed by itself.
It is impossible to distinguish between units and other prostheses, and the same problem occurs.

The present invention has been made in view of the above problems, and provides detailed and high-speed information about a bus abnormality that has occurred on a common bus of a multiprocessor system, without imposing a load on software. The purpose is to be able to notify the unit.

[0010]

FIG. 1 is a block diagram of a bus abnormality notifying system according to the present invention. In order to solve the above problems, the bus abnormality notification method of the present invention uses a plurality of processor units 1-1 to 1-N each managing a plurality of I / O units.
And the plurality of managed I / O units 2-1-1 to 2-Nz
And a common bus 5 connecting all the units 1-1 to 1-N and 2-1-1 to 2-Nz, the method of notifying a bus abnormality in a multiprocessor system comprising: A bus abnormality notification line 5 for serial data communication is provided in parallel with the common bus 5 for data transmission / reception, and a bus abnormality that occurs when accessed is detected, and includes the ID of the processor unit that manages its own unit. A bus abnormality detection unit 21 for converting the bus abnormality information into serial data and transmitting it to the bus abnormality notification line 5 is provided for each I / O unit.
Each bus abnormality recording register 12 receives bus abnormality information from the bus abnormality notification line 5, judges whether the information is addressed to its own processor unit, and if it is addressed to its own processor unit, sends an interrupt notification to the CPU 11. The I / O unit provided in each processor unit and detecting the bus abnormality notifies the bus abnormality information to the bus abnormality recording registers of all the processor units via the bus abnormality notification line in the access bus cycle, and the I / O unit It is configured such that only the processor unit that manages the O unit causes a CPU interrupt, and that the I / O unit that operates in DMA serves as the bus master and the I / O unit that serves as the bus slave is not managed by any processor unit. In the case of the memory unit 6, the common memory 6 that has detected the bus abnormality has its own ID. Is sent to the bus error notification line, and the I / O unit operating in DMA subsequently sends the ID of the processor unit managing its own I / O to the bus error notification line 5. is there.

[0011]

When the bus abnormality detection unit of all I / O units detects a bus abnormality when the self unit is accessed via the common bus, the detailed abnormality information is immediately converted to serial data within the same bus cycle and the bus abnormality is notified. Send to all processor units via line. Therefore, the bus abnormality information register for holding the bus abnormality information becomes unnecessary. Further, since the NMI interrupt notification to the CPU of the processor unit is performed only by the processor unit that has caused the bus abnormality, the processor unit irrelevant to the bus abnormality does not perform wasteful interrupt processing and loads the software. Disappears.

If the accessed I / O unit is a common memory, it does not have the ID of the processor unit that manages its own unit, so the accessed DMA-
The I / O unit subsequently sends out the ID of the processor unit that manages itself. As a result, only the CPU of the related processor is notified of the interrupt, and the recovery process / retry process is performed.

[0013]

Embodiments of the present invention will be described below with reference to the accompanying drawings. FIG. 1 is a block diagram of a bus abnormality notification system of the present invention, FIG.
FIG. 3 is a diagram showing an operation sequence. Note that the same reference numerals denote the same objects throughout the drawings.

In FIG. 1, 1-1 to 1-N are a plurality of individual processor units constituting a multiprocessor system, and each processor is a plurality of I / O units 2-.
1-1 to 2-1-n, ..., 2-N-1 to 2-N-z are managed. 6
Is a common memory unit for each processor unit and D
It is commonly accessed from I / O units capable of MA operation. A common bus 3 is composed of a data line, an address line, a control line, etc., and connects all units.

Reference numeral 5 denotes one bus abnormality notification line which connects all the units in parallel with the common bus 3. Each of the I / O units 2-1-1 to 2-1-n, ... 2-N-1 to 2-N-z and the common memory 6 includes a bus abnormality detection unit 21, a bus control unit 22, and a bus interface. It has a face unit 23 and a plurality of registers 24.

When the bus abnormality detector 21 monitors the data received via the common bus 3 and detects a bus abnormality, it immediately sends all information related to the bus abnormality to serial data and sends it to the bus abnormality notification line 5. To do.

The bus control unit 22 controls the connection to the common bus, and when the bus abnormality detection unit 21 receives a bus abnormality occurrence notification while being accessed from the managing processor unit, the bus control unit 22 acknowledges the data reception (acknowledgement). ) Is stopped, and the bus cycle is delayed until the transmission of the abnormality information from the bus abnormality detection unit 21 is completed.

The bus interface unit 23 controls the interface with the common bus, and the register 24 temporarily stores the data to be transmitted and received. Each processor unit 1-1 to 1-N is CP
It has a U chip 11 and a bus error recording register 12. The bus abnormality register 12 receives and records the serial data of the bus abnormality information from the bus abnormality notification line 5, and when the processor unit ID in the abnormality information matches its own ID, masks it on the CPU chip via the interrupt line 14. Impossible interrupt NMI
Has a function of notifying. Based on this interrupt notification, the software on the CPU 11 recognizes that a bus error has occurred during access to the I / O unit it manages, and activates the interrupt processing program to start the bus error recording register.
Bus error information is read from 12 through the internal bus 13 and recovery / retry processing is performed.

Next, the sequence of bus abnormality notification will be described with reference to FIG. FIG. 3 shows an example in which the bus master that acquires the right to use the common bus is the processor unit and the bus slave to be accessed is the I / O unit.

FIG. 3A shows the data exchange between the master and the slave in a normal state where no bus abnormality has occurred. When the slave I / O unit normally receives the data from the bus master processor unit, it returns an acknowledge (ACK) and ends the bus cycle.

When a bus abnormality occurs in the diagram (b), the bus abnormality detection unit of the I / O unit that has become a bus slave receives the data from the bus interface unit via the common bus when its own unit is accessed by the bus master. When received, the data is monitored to detect a bus error. When the bus abnormality is detected, the return of the acknowledge is suspended and the bus abnormality information is sent to the bus abnormality notification line. This bus error information includes the address of the register being accessed at that time, the contents of the data in which the error occurred, the bus error data such as the error type of address parity error or data parity error, and the like.
It consists of ID information of the ID of the processor unit managing the own unit and the management number for the own unit under the processor unit. These data are converted into serial data and sent to the bus abnormality notification line. Since the bus does not acknowledge that the data has been normally received, the bus is in a state of being exclusively used by the two units, thus extending the bus cycle and sending all the information. The bus is released when the transmission is completed.

In all the processor units, the bus abnormality record register receives the bus abnormality information sent from the bus slave I / O unit which has detected the bus abnormality via the bus abnormality notification line. Up to this point, the processing is performed by hardware regardless of the task being processed by the CPU. Then, only in the processor unit in which the processor ID included in the received bus abnormality information matches its own ID, the non-maskable interrupt NMI is applied to the CPU from the bus abnormality recording register, and error analysis processing is performed by software. At this time, since all the information about the bus abnormality is held in the bus abnormality recording register, it is not necessary to newly acquire the common bus and receive the transfer.

Next, the operation when the bus master is the I / O unit for performing the DMA operation and the I / O unit serving as the bus slave is the common memory will be described with reference to FIG. Since the common memory unit is equally accessed by all the processor units, it does not have the ID of the processor that manages its own unit. And, in this common memory, DM
The I / O unit having the A function can be directly accessed by the instruction of the controlling processor.

When the common memory unit detects a bus abnormality when accessed from the DMA-I / O unit, it sends bus abnormality information not including the processor ID to the bus abnormality notification line, and when this transmission is completed, it continues. The DMA-I / O unit which is the bus master sends the ID information including the ID of the processor unit that manages itself and the management number under the processor unit to the bus abnormality notification line.

All processor units receive the data sent from the common memory unit (bus slave) and the DMA-I / O unit (bus master) in the bus abnormality recording register. Then, only in the processor unit in which the processor ID written in the DMA-I / O matches its own ID, the bus error recording register is set to C
An interrupt is generated for the PU to notify the software of the occurrence of an abnormality.

As a result, the CPU of the processor unit
Since software is notified only when there is a bus error related to the I / O unit under its control, the software load on other processors does not increase. In addition, all processor units receive all bus fault information within the same bus cycle as the faulty bus access cycle, so even if bus faults occur continuously, all faults can be detected and notified. Becomes

As described above, according to the present invention, in a multiprocessor system, a bus abnormality occurring on a common bus can be notified to a CPU at the same time as the occurrence, and even if consecutive occurrences occur, all related CPUs are notified. Therefore, it is advantageous that each CPU system can independently perform the abnormal recovery process.

[0028]

As described above, according to the present invention, in the multiprocessor system, the CP of the processor which manages the bus abnormality occurring on the common bus at the same time as the occurrence of the bus abnormality occurs.
Since only U can be notified, there is an effect that bus load can be efficiently detected without increasing the load of software.

[Brief description of drawings]

FIG. 1 is a configuration diagram of a bus abnormality notification system of the present invention.

FIG. 2 is a diagram showing an operation sequence (No. 1)

FIG. 3 is a diagram showing an operation sequence (No. 2)

FIG. 4 Bus Abnormality Notification Method in Single Processor System

FIG. 5 is a block diagram of a multiprocessor system targeted by the present invention.

[Explanation of symbols]

1-1 to 1-N ... Multiprocessor, 11 ... CPU, 12 ... Bus error recording register, 2-1-1 to 2-Nz ... I / O unit,
21 ... Bus abnormality detection unit, 22 ... Bus control unit, 3 ... Common bus,
5: Bus error notification line

 ─────────────────────────────────────────────────── ─── Continuation of the front page (72) Inventor Yukio Kanagawa 1015 Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited (72) Inventor Takao Nara, 1015, Kamiodanaka, Nakahara-ku, Kawasaki City, Kanagawa Prefecture, Fujitsu Limited

Claims (2)

[Claims] 1. A plurality of processor units (1-1 to 1-N), each managing a plurality of I / O units, and a plurality of the managed I / O units (2-1-1 to 2-). Nz) and one common bus (5) that connects all the units (1-1 to 1-N, 2-1-1 to 2-Nz) with each other. There is a bus error notification line (5) that performs serial data communication in parallel with the common bus (5) that transmits and receives data between the units.
The bus error notification line (5) is provided, which detects a bus error that occurs when accessed, and converts the bus error information including the ID of the processor unit that manages its own unit into serial data.
A bus abnormality detection unit (21) for sending to each I / O unit, receives bus abnormality information from the bus abnormality notification line (5), judges whether the information is addressed to its own processor unit, and determines its own processor unit. In the case of addressing, a bus error recording register (12) for notifying the CPU (11) of an interrupt is provided in each processor unit, and the I / O unit that has detected the bus error receives the bus error in the access bus cycle. Bus error characterized by notifying the bus error information to the bus error recording registers of all processor units via the notification line (5) so that only the processor unit managing the I / O unit causes a CPU interrupt. Notification method. 2. The common memory unit (6) according to claim 1, wherein the I / O unit that operates in DMA serves as a bus master, and the I / O unit that serves as a bus slave is not managed by any processor unit.
In this case, the common memory (6) sends bus abnormality information including its own ID to the bus abnormality notification line (5), and the I / O unit operating in the DMA subsequently manages its own I / O. A bus error notification system characterized in that the ID of the processor unit is sent to the bus error notification line (5).