JPH0637145A - Connecting method for circuit board - Google Patents
Connecting method for circuit boardInfo
- Publication number
- JPH0637145A JPH0637145A JP4186650A JP18665092A JPH0637145A JP H0637145 A JPH0637145 A JP H0637145A JP 4186650 A JP4186650 A JP 4186650A JP 18665092 A JP18665092 A JP 18665092A JP H0637145 A JPH0637145 A JP H0637145A
- Authority
- JP
- Japan
- Prior art keywords
- wiring board
- bump
- semiconductor chip
- chip
- bumps
- Prior art date
- Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
- Granted
Links
Classifications
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/10—Bump connectors; Manufacturing methods related thereto
- H01L2224/15—Structure, shape, material or disposition of the bump connectors after the connecting process
- H01L2224/16—Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2224/00—Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
- H01L2224/01—Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
- H01L2224/42—Wire connectors; Manufacturing methods related thereto
- H01L2224/44—Structure, shape, material or disposition of the wire connectors prior to the connecting process
- H01L2224/45—Structure, shape, material or disposition of the wire connectors prior to the connecting process of an individual wire connector
- H01L2224/45001—Core members of the connector
- H01L2224/45099—Material
- H01L2224/451—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof
- H01L2224/45138—Material with a principal constituent of the material being a metal or a metalloid, e.g. boron (B), silicon (Si), germanium (Ge), arsenic (As), antimony (Sb), tellurium (Te) and polonium (Po), and alloys thereof the principal constituent melting at a temperature of greater than or equal to 950°C and less than 1550°C
- H01L2224/45144—Gold (Au) as principal constituent
-
- H—ELECTRICITY
- H01—ELECTRIC ELEMENTS
- H01L—SEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
- H01L2924/00—Indexing scheme for arrangements or methods for connecting or disconnecting semiconductor or solid-state bodies as covered by H01L24/00
- H01L2924/01—Chemical elements
- H01L2924/01087—Francium [Fr]
Abstract
Description
【０００１】[0001]
【産業上の利用分野】本発明は配線基板上に半導体チッ
プをバンプを介して接続する配線基板の接続方法に関す
る。BACKGROUND OF THE INVENTION 1. Field of the Invention The present invention relates to a wiring board connecting method for connecting a semiconductor chip on a wiring board via bumps.
【０００２】[0002]
【従来の技術】従来配線基板に半導体チップを接続する
方法としては、半導体チップを樹脂パッケージ内に封止
して構成したＩＣの端子をプリント配線基板に接続する
という方法が一般的であった。しかし、プリント配線基
板の配線パターンがファインピッチ化してくると、この
方法では、実装密度が上がらないという問題がある。そ
こで、現在では、直接、この半導体チップをプリント配
線基板に接続することにより実装密度を向上させるよう
にしている。2. Description of the Related Art Conventionally, as a method of connecting a semiconductor chip to a wiring board, a method of connecting the terminals of an IC formed by encapsulating the semiconductor chip in a resin package to a printed wiring board has been generally used. However, when the wiring pattern of the printed wiring board has a fine pitch, this method has a problem that the mounting density cannot be increased. Therefore, at present, the mounting density is improved by directly connecting the semiconductor chip to the printed wiring board.
【０００３】この半導体チップを直接に配線基板に接続
する方法としては、金線を使用したワイヤボンディング
法や配線基板あるいは半導体チップに、はんだ、インジ
ウム等のバンプを設け、このバンプを介して配線基板に
半導体チップを直接接続するフリップチップ実装法があ
る。前者のワイヤボンディング法は、後者のフリップチ
ップ実装法に比べて作業性及び実装密度が劣ることか
ら、今日ではこのフリップチップ実装法が実装密度を上
げる技術として注目されている。As a method of directly connecting the semiconductor chip to the wiring board, a wire bonding method using a gold wire or a bump of solder, indium or the like is provided on the wiring board or the semiconductor chip, and the wiring board is provided through the bump. There is a flip chip mounting method in which the semiconductor chip is directly connected to. The former wire bonding method is inferior in workability and mounting density to the latter flip chip mounting method, and therefore, this flip chip mounting method is now drawing attention as a technique for increasing the mounting density.
【０００４】[0004]
【発明が解決しようとする課題】ところで、このフリッ
プチップ実装法により、図９に示す如く半導体チップ１
を配線基板２にバンプ３を介して直接接続したときに
は、リペアが非常に困難であり、この半導体チップ１を
配線基板２より機械的にはがす方法も考えられるが、こ
の場合、配線基板２のパッド等もはがれ修理が不能とな
る問題があるので、一般的にはバンプ３を加熱により溶
かし、半導体チップ１を配線基板２よりはがすようにし
ていた。By the way, as shown in FIG. 9, the semiconductor chip 1 is manufactured by this flip chip mounting method.
Is very difficult to connect directly to the wiring board 2 via the bumps 3, and a method of mechanically peeling off the semiconductor chip 1 from the wiring board 2 is conceivable. In this case, the pads of the wiring board 2 Since there is a problem in that the peeling and the like make it impossible to repair, the bump 3 is generally melted by heating and the semiconductor chip 1 is peeled off from the wiring board 2.
【０００５】この半導体チップ１を加熱により、はがし
たときには、図１０に示す如く配線基板２側に不均一に
このバンプ３の残渣３ａが残り、この配線基板２に再び
新しい半導体チップ１を実装するときに、この配線基板
２をリフローして、このバンプ３の残渣３ａを平坦化し
ても、この残渣３ａの高さにバラツキが大きくあり、図
１１に示す如くこの新しい半導体チップ１のバンプ３が
配線基板２の所定位置に接触しない部分が発生し、接続
不良となる問題を生じる不都合があった。When the semiconductor chip 1 is peeled off by heating, residues 3a of the bumps 3 are unevenly left on the wiring board 2 side as shown in FIG. 10, and a new semiconductor chip 1 is mounted on the wiring board 2 again. At this time, even if the wiring substrate 2 is reflowed and the residue 3a of the bump 3 is flattened, the height of the residue 3a greatly varies, and as shown in FIG. 11, the bump 3 of the new semiconductor chip 1 is formed. However, there is a problem in that a portion that does not come into contact with a predetermined position of the wiring board 2 is generated, resulting in poor connection.
【０００６】本発明は斯る点に鑑みリペア時に接続不良
を生ずることがないようにすることを目的とする。The present invention has been made in view of the above problems, and an object thereof is to prevent a connection failure from occurring during repair.
【０００７】[0007]
【課題を解決するための手段】本発明配線基板の接続方
法は配線基板２に半導体チップ１をバンプを介して接続
する配線基板の接続方法において、リペアする際に、最
初に実装したバンプ３より高いバンプ４により接続する
ようにしたものである。The wiring board connecting method of the present invention is a wiring board connecting method for connecting a semiconductor chip 1 to a wiring board 2 via bumps. The high bumps 4 are used for connection.
【０００８】本発明配線基板の接続方法は配線基板２に
半導体チップ１をバンプ３を介して接続する配線基板の
接続方法において、リペアする際に、この半導体チップ
１を取った後、この配線基板２側に残るバンプ３の残渣
３ａを毛細管現象を利用して除去し、その後この配線基
板２に半導体チップ１をバンプ３を介して接続するよう
にしたものである。The wiring board connecting method of the present invention is a wiring board connecting method in which the semiconductor chip 1 is connected to the wiring board 2 through the bumps 3. In repairing, the semiconductor chip 1 is removed and then the wiring board is connected. The residue 3a of the bump 3 remaining on the second side is removed by utilizing a capillary phenomenon, and then the semiconductor chip 1 is connected to the wiring board 2 via the bump 3.
【０００９】また本発明配線基板の接続方法は配線基板
２に半導体チップ１をバンプ３を介して接続する配線基
板の接続方法において、リペアする際に、この半導体チ
ップ１を取った後、この配線基板２側に残るバンプ３の
残渣３ａをポーラスな金属又は中空構造を持つ繊維によ
り毛細管現象を利用して除去し、その後この配線基板２
に半導体チップ１をバンプ３を介して接続するようにし
たものである。The wiring board connecting method of the present invention is a wiring board connecting method in which the semiconductor chip 1 is connected to the wiring board 2 via the bumps 3. In repairing, the semiconductor chip 1 is removed and then the wiring is formed. The residue 3a of the bump 3 remaining on the substrate 2 side is removed by using a capillary phenomenon using a porous metal or a fiber having a hollow structure, and then the wiring substrate 2
The semiconductor chip 1 is connected via the bumps 3.
【００１０】[0010]
【作用】本発明によればリペアする際に最初に実装した
バンプ３より高いバンプ４により接続するようにしたの
で、半導体チップ１を取ったときに配線基板２に残るバ
ンプ３の残渣３ａの高さが、この高いバンプ４の誤差範
囲内となり、加熱加圧によりこの半導体チップ１ａを配
線基板２に良好に接合できる。According to the present invention, when repairing, the bumps 4 higher than the first mounted bumps 3 are connected to each other. Therefore, when the semiconductor chip 1 is taken, the residue 3a of the bumps 3 remaining on the wiring board 2 is high. However, the semiconductor chip 1a can be satisfactorily bonded to the wiring board 2 by heating and pressing.
【００１１】また本発明によれば、この半導体チップ１
を取った後に、この配線基板２側に残るバンプ３の残渣
３ａを加熱し、ポーラスな金属又は中空構造を持つ繊維
により毛細管現象で吸い取り、きれいにした状態でフリ
ップチップ実装するので、新しい半導体チップ１を配線
基板２に良好に接合することができる。Further, according to the present invention, this semiconductor chip 1
After the removal, the residue 3a of the bump 3 remaining on the side of the wiring board 2 is heated and absorbed by a capillary phenomenon by a porous metal or a fiber having a hollow structure, and flip chip mounting is performed in a clean state. Can be satisfactorily joined to the wiring board 2.
【００１２】[0012]
【実施例】以下図面を参照して本発明配線基板の接続方
法の一実施例につき説明しよう。図１は本発明に使用さ
れるフリップチップボンダの例を示し、この図１におい
て、５は加熱、加圧のできる真空チャックを備えたツー
ルであり、このツール５は前後、左右及び上下に高精度
で移動することができるようになされている。DETAILED DESCRIPTION OF THE PREFERRED EMBODIMENTS An embodiment of the wiring board connecting method of the present invention will be described below with reference to the drawings. FIG. 1 shows an example of a flip chip bonder used in the present invention. In FIG. 1, 5 is a tool equipped with a vacuum chuck capable of heating and pressurizing. It is designed to be able to move with precision.
【００１３】本例においては例えば５μｍの高さのバン
プ３が所定位置に付された半導体チップ１と例えば５０
μｍの高さのバンプ４が所定位置に付された半導体チッ
プ１ａを所定位置に用意する。この場合、半導体チップ
１及び１ａは実質的に同一回路構成のものとする。In this example, a semiconductor chip 1 having bumps 3 with a height of, for example, 5 μm attached at predetermined positions and, for example, 50
A semiconductor chip 1a having bumps 4 having a height of μm attached at predetermined positions is prepared at predetermined positions. In this case, the semiconductor chips 1 and 1a have substantially the same circuit configuration.
【００１４】本例においては最初は例えば５μｍの高さ
のバンプ３が付された半導体チップ１をこのツール５に
より吸着して、所定位置に配置された配線基板２上のパ
ッド６へ移動し、この半導体チップ１を配線基板２に加
熱、加圧により図２に示す如く接合する如くする。In this example, first, the semiconductor chip 1 having the bumps 3 with a height of, for example, 5 μm is adsorbed by the tool 5 and moved to the pad 6 on the wiring board 2 arranged at a predetermined position. The semiconductor chip 1 is bonded to the wiring board 2 by heating and pressing as shown in FIG.
【００１５】この場合において、図２の右側に示す如く
接続不良が生じ、リペアする際は、加熱によりバンプ３
を溶かし、この配線基板２より半導体チップ１を取った
ときは例えば図３に示す如く、この配線基板２にバンプ
３の残渣３ａが残ることとなる。In this case, a connection failure occurs as shown on the right side of FIG. 2, and when repairing, the bump 3 is heated.
When the semiconductor chips 1 are melted and the semiconductor chip 1 is taken from the wiring board 2, the residues 3a of the bumps 3 are left on the wiring board 2 as shown in FIG. 3, for example.
【００１６】この場合バンプ３の残渣３ａの高さｈはこ
のバンプ３の高さ５μｍより低くなる。In this case, the height h of the residue 3a of the bump 3 is lower than the height 5 μm of the bump 3.
【００１７】その後、この半導体チップ１をはがした部
分に新しい半導体チップをフリップチップ実装するとき
にはツール５により、例えば５０μｍの高さのバンプ４
が付された半導体チップ１ａを吸着して、そのはがした
部分に移動して配する。After that, when a new semiconductor chip is flip-chip mounted on the portion from which the semiconductor chip 1 has been peeled off, a bump 5 having a height of, for example, 50 .mu.m is formed by a tool 5.
The semiconductor chip 1a marked with is adsorbed and moved to the peeled portion to be arranged.
【００１８】この場合は残渣３ａの無い部分及び少ない
部分には空隙が生じるが、この空隙は例えば５μｍ以下
なので例えば５０μｍの高さのバンプ４に比べては非常
に小さく誤差範囲内でありツール５により加熱、加圧す
ることにより図５に示す如く良好な接合が得られる。In this case, a void is formed in the portion where the residue 3a is absent and in a small portion, but since this void is, for example, 5 μm or less, it is much smaller than the bump 4 having a height of 50 μm, which is within the error range, and the tool 5 is used. By applying heat and pressure, good bonding can be obtained as shown in FIG.
【００１９】以上述べた如く上述例によればリペアする
際に、最初に実装した例えば５μｍの高さのバンプ３よ
り高い例えば５０μｍの高さのバンプ４により接続する
ので、半導体チップ１を取ったときに配線基板２に残る
バンプ３の残渣３ａの高さが、この例えば５０μｍの高
さのバンプ４の誤差範囲内となり、加熱、加圧により、
この半導体チップ１ａを配線基板２に良好に接合できる
利益がある。As described above, according to the above-mentioned example, since the bumps 4 having a height of, for example, 50 μm, which are higher than the bumps 3 having a height of, for example, 5 μm, which are initially mounted, are used for connection, the semiconductor chip 1 is taken. At this time, the height of the residue 3a of the bump 3 remaining on the wiring board 2 falls within the error range of the bump 4 having a height of, for example, 50 μm.
There is an advantage that the semiconductor chip 1a can be satisfactorily bonded to the wiring board 2.
【００２０】次に本例の他の実施例につき説明するに、
配線基板２に半導体チップ１をバンプ３を介して接続す
る配線基板の接続方法において、図２の右側に示す如
く、接続不良が生じ、リペアする際は、加熱により、バ
ンプ３を溶かし、この配線基板２より半導体チップ１を
取ったときは例えば図３に示す如く、この配線基板２に
バンプ３の残渣３ａが残ることとなる。Next, another embodiment of this embodiment will be described.
In the wiring board connecting method of connecting the semiconductor chip 1 to the wiring board 2 via the bumps 3, as shown on the right side of FIG. 2, when the repair is performed, the bumps 3 are melted by heating to repair the wiring. When the semiconductor chip 1 is taken from the substrate 2, the residue 3a of the bump 3 remains on the wiring substrate 2 as shown in FIG. 3, for example.
【００２１】本例にこの配線基板２に残ったバンプ３の
残渣３ａを毛細管現象により吸い取るリペアチップ７に
より除去する如くする。In this embodiment, the residue 3a of the bump 3 remaining on the wiring board 2 is removed by the repair chip 7 which absorbs by a capillary phenomenon.
【００２２】このリペアチップ７は例えば図６に示す如
く半導体チップ１と略同じ大きさの熱伝導性の良い金属
よりなるベース７ａに所定のメッキ条件で電解メッキに
より金、銅等の金属７ｂをポーラスに付着したものであ
る。For example, as shown in FIG. 6, the repair chip 7 has a base 7a made of a metal having substantially the same size as the semiconductor chip 1 and good thermal conductivity, and a metal 7b such as gold or copper is electrolytically plated under a predetermined plating condition. It is attached to the porous.
【００２３】このリペアの際に、本例においては図１に
示す如きフリップチップボンダを図７に示す如く作動さ
せる如くする。すなわちステップＳ1 及びＳ2 で半導体
チップ１が良品であるかどうかを判断し、これが不良の
ときはリペアの動作に移行する。At the time of this repair, in this embodiment, the flip chip bonder as shown in FIG. 1 is operated as shown in FIG. That is, in steps S 1 and S 2 , it is determined whether the semiconductor chip 1 is a non-defective product, and if it is defective, the operation of repair is started.
【００２４】このときはまずツール５により不良の半導
体チップ１を加熱（２３０℃）し取り去る（ステップＳ
3 ）。その後、ツール５の真空チャックによりこのリペ
アチップ７のベース７ａ側を吸着固定し（ステップ
Ｓ4 ）、このリペアチップ７を約２３０℃に加熱した状
態で配線基板２のバンプ３の残渣３ａ部にこのリペアチ
ップ７を例えば５秒間押しつけて加圧（２００ｇ）し、
このリペアチップ７のポーラスな金属７ｂにより、バン
プ３の残渣３ｂを毛細管現象により吸い取る（ステップ
Ｓ5 ）。In this case, first, the defective semiconductor chip 1 is heated (230 ° C.) by the tool 5 and removed (step S).
3 ). Thereafter, the vacuum chuck tools 5 adsorbs secure the base 7a side of the repair chip 7 (Step S 4), the residue 3a of the bump 3 of the wiring board 2 while heating the repair chip 7 to about 230 ° C. This repair tip 7 is pressed for 5 seconds to pressurize (200 g),
The porous metal 7b of the repair chip 7, the residue 3b bump 3 sucks by capillary action (Step S 5).
【００２５】この場合毛細管現象によりバンプ３の残渣
３ａのはんだ、インジウム等を吸い取るので、この残渣
３ａを良好に除去することができる。In this case, since the solder, indium and the like of the residue 3a of the bump 3 is absorbed by the capillary phenomenon, the residue 3a can be removed well.
【００２６】その後このリペアチップ７を廃棄し（ステ
ップＳ6 ）、次にこの配線基板２のバンプ３の残渣３ａ
のきれいに除去されたパッド６に新しい半導体チップ１
をバンプ３を介して接続する（ステップＳ7 ）。Thereafter, the repair chip 7 is discarded (step S 6 ), and then the residue 3 a of the bump 3 on the wiring board 2 is removed.
Newly removed semiconductor chip 1 on the pad 6
Are connected via the bumps 3 (step S 7 ).
【００２７】従って本例によれば、リペアの際にこの半
導体チップ１を取った後に、この配線基板２側に残るバ
ンプ３の残渣３ａを加熱し、リペアチップ７のポーラス
な金属により毛細管現象で吸い取り、きれいにした状態
で再びフリップチップ実装するので、新しい半導体チッ
プ１を配線基板２に良好に接合することができる利益が
ある。Therefore, according to this example, after the semiconductor chip 1 is taken during the repair, the residue 3a of the bump 3 remaining on the wiring substrate 2 side is heated and the porous metal of the repair chip 7 causes a capillary phenomenon. Since it is sucked up and flip-chip mounted again in a clean state, there is an advantage that the new semiconductor chip 1 can be satisfactorily bonded to the wiring board 2.
【００２８】図８はリペアチップ７の他の例を示し、こ
の図８のリペアチップ７は熱伝導性の良い金属より成る
ベース７ａの一表面７ｃをあらして、ポーラスな金属と
同様の効果を得るようにしたものである。FIG. 8 shows another example of the repair tip 7. The repair tip 7 of FIG. 8 has one surface 7c of a base 7a made of a metal having a good thermal conductivity, and has the same effect as a porous metal. It's something I got to get.
【００２９】またこのリペアチップ７として、ビース
状、中空繊維（例えばガラス製）の集合体により構成
し、この毛細管現象により加熱されたバンプ３の残渣３
ａを吸い取るようにしても上述同様の作用効果が得られ
ることは勿論である。The repair tip 7 is composed of a bead-shaped, hollow fiber (for example, glass) aggregate, and the residue 3 of the bump 3 heated by this capillary phenomenon.
Needless to say, the same effect as described above can be obtained even if a is absorbed.
【００３０】尚本発明は上述実施例に限ることなく本発
明の要旨を逸脱することなく、その他種々の構成が採り
得ることは勿論である。The present invention is not limited to the above-mentioned embodiments, and it goes without saying that various other configurations can be adopted without departing from the gist of the present invention.
【００３１】[0031]
【発明の効果】本発明によればリペアする際に、最初に
実装したバンプ３より高いバンプ４により接続するよう
にしたので、半導体チップ１を取ったときに配線基板２
に残るバンプ３の残渣３ａの高さが、この高いバンプ４
の誤差範囲内となり、加熱加圧により、この半導体チッ
プ１ａを配線基板２に良好に接合できる利益がある。According to the present invention, at the time of repairing, the bumps 4 higher than the first mounted bumps 3 are connected to each other. Therefore, when the semiconductor chip 1 is taken out, the wiring board 2
The height of the residue 3a of the bump 3 remaining in the
Within the error range, there is an advantage that the semiconductor chip 1a can be satisfactorily bonded to the wiring board 2 by heating and pressing.
【００３２】また本発明によれば、この半導体チップ１
を取った後は、この配線基板２側に残るバンプ３の残渣
３ａを加熱し、ポーラスな金属又は中空構造を持つ繊維
により毛細管現象で吸い取り、きれいにした状態で、フ
リップチップ実装するので新しい半導体チップ１を配線
基板２に良好に接合することができる利益がある。Further, according to the present invention, this semiconductor chip 1
After the removal, the residue 3a of the bump 3 remaining on the wiring board 2 side is heated and absorbed by a capillary phenomenon by a porous metal or a fiber having a hollow structure, and in a clean state, flip chip mounting is performed. There is an advantage that 1 can be satisfactorily bonded to the wiring board 2.
【図１】本発明の一実施例に使用されるフリップチップ
ボンダの例を示す構成図である。FIG. 1 is a configuration diagram showing an example of a flip chip bonder used in an embodiment of the present invention.
【図２】本発明の説明に供する線図である。FIG. 2 is a diagram for explaining the present invention.
【図３】本発明の説明に供する線図である。FIG. 3 is a diagram for explaining the present invention.
【図４】本発明の説明に供する線図である。FIG. 4 is a diagram for explaining the present invention.
【図５】本発明の説明に供する線図である。FIG. 5 is a diagram for explaining the present invention.
【図６】リペアチップの例を示す側面図である。FIG. 6 is a side view showing an example of a repair chip.
【図７】本発明の説明に供する線図である。FIG. 7 is a diagram used for explaining the present invention.
【図８】リペアチップの例を示す側面図である。FIG. 8 is a side view showing an example of a repair chip.
【図９】フリップチップ実装の説明に供する線図であ
る。FIG. 9 is a diagram for explaining flip-chip mounting.
【図１０】従来の説明に供する線図である。FIG. 10 is a diagram used for conventional description.
【図１１】従来の説明に供する線図である。FIG. 11 is a diagram used for conventional description.
１，１ａ 半導体チップ ２ 配線基板 ３，４ バンプ ６ パッド ７ リペアチップ 1,1a Semiconductor chip 2 Wiring board 3,4 Bump 6 Pad 7 Repair chip
Claims (3)
て接続する配線基板の接続方法において、 リペアする際に、最初に実装したバンプより高いバンプ
により接続するようにしたことを特徴とする配線基板の
接続方法。1. A wiring board connecting method for connecting a semiconductor chip to a wiring board via bumps, wherein when repairing, a bump higher than the first mounted bump is used for connection. Connection method.
て接続する配線基板の接続方法において、 リペアする際に、上記半導体チップを取った後、上記配
線基板側に残るバンプの残渣を毛細管現象を利用して除
去し、その後上記配線基板に半導体チップをバンプを介
して接続するようにしたことを特徴とする配線基板の接
続方法。2. A wiring board connecting method for connecting a semiconductor chip to a wiring board via bumps, wherein when repairing, the residue of the bumps remaining on the wiring board side after the semiconductor chip is removed is capillarized. A method of connecting a wiring board, characterized in that the semiconductor chip is connected to the wiring board via bumps after the removal.
て、接続する配線基板の接続方法において、 リペアする際に、上記半導体チップを取った後、上記配
線基板側に残るバンプの残渣をポーラスな金属又は中空
構造を持つ繊維により毛細管現象を利用して除去し、そ
の後上記配線基板に半導体チップをバンプを介して接続
するようにしたことを特徴とする配線基板の接続方法。3. A wiring board connecting method for connecting a semiconductor chip to a wiring board via bumps, wherein, when repairing, the residue of the bumps remaining on the wiring board side after taking the semiconductor chip is porous. A method for connecting a wiring board, characterized in that a metal or a fiber having a hollow structure is used to remove by using a capillary phenomenon, and then a semiconductor chip is connected to the wiring board via a bump.
Priority Applications (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18665092A JP3235192B2 (en) | 1992-07-14 | 1992-07-14 | Wiring board connection method |
Applications Claiming Priority (1)
| Application Number | Priority Date | Filing Date | Title |
|---|---|---|---|
| JP18665092A JP3235192B2 (en) | 1992-07-14 | 1992-07-14 | Wiring board connection method |
Publications (2)
| Publication Number | Publication Date |
|---|---|
| JPH0637145A true JPH0637145A (en) | 1994-02-10 |
| JP3235192B2 JP3235192B2 (en) | 2001-12-04 |
Family
ID=16192293
Family Applications (1)
| Application Number | Title | Priority Date | Filing Date |
|---|---|---|---|
| JP18665092A Expired - Fee Related JP3235192B2 (en) | 1992-07-14 | 1992-07-14 | Wiring board connection method |
Country Status (1)
| Country | Link |
|---|---|
| JP (1) | JP3235192B2 (en) |
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09330956A (en) * | 1996-06-13 | 1997-12-22 | Nec Corp | Method and device for repairing semiconductor device |
| KR100325293B1 (en) * | 1999-05-20 | 2002-02-21 | 김영환 | ball mounting device for repairing ball for semiconductor package and method for mounting ball with such ball mounting device |
-
1992
- 1992-07-14 JP JP18665092A patent/JP3235192B2/en not_active Expired - Fee Related
Cited By (2)
| Publication number | Priority date | Publication date | Assignee | Title |
|---|---|---|---|---|
| JPH09330956A (en) * | 1996-06-13 | 1997-12-22 | Nec Corp | Method and device for repairing semiconductor device |
| KR100325293B1 (en) * | 1999-05-20 | 2002-02-21 | 김영환 | ball mounting device for repairing ball for semiconductor package and method for mounting ball with such ball mounting device |
Also Published As
| Publication number | Publication date |
|---|---|
| JP3235192B2 (en) | 2001-12-04 |
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