JP2812304B2 - Repair method for flip-chip type semiconductor device - Google Patents

Repair method for flip-chip type semiconductor device

Info

Publication number
JP2812304B2
JP2812304B2 JP8176331A JP17633196A JP2812304B2 JP 2812304 B2 JP2812304 B2 JP 2812304B2 JP 8176331 A JP8176331 A JP 8176331A JP 17633196 A JP17633196 A JP 17633196A JP 2812304 B2 JP2812304 B2 JP 2812304B2
Authority
JP
Japan
Prior art keywords
solder
chip
flip
lsi
type semiconductor
Prior art date
Legal status (The legal status is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the status listed.)
Expired - Fee Related
Application number
JP8176331A
Other languages
Japanese (ja)
Other versions
JPH1022340A (en
Inventor
博文 中村
Current Assignee (The listed assignees may be inaccurate. Google has not performed a legal analysis and makes no representation or warranty as to the accuracy of the list.)
NEC Corp
Original Assignee
NEC Corp
Priority date (The priority date is an assumption and is not a legal conclusion. Google has not performed a legal analysis and makes no representation as to the accuracy of the date listed.)
Filing date
Publication date
Application filed by NEC Corp filed Critical NEC Corp
Priority to JP8176331A priority Critical patent/JP2812304B2/en
Publication of JPH1022340A publication Critical patent/JPH1022340A/en
Application granted granted Critical
Publication of JP2812304B2 publication Critical patent/JP2812304B2/en
Anticipated expiration legal-status Critical
Expired - Fee Related legal-status Critical Current

Links

Classifications

    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/01Means for bonding being attached to, or being formed on, the surface to be connected, e.g. chip-to-package, die-attach, "first-level" interconnects; Manufacturing methods related thereto
    • H01L2224/10Bump connectors; Manufacturing methods related thereto
    • H01L2224/15Structure, shape, material or disposition of the bump connectors after the connecting process
    • H01L2224/16Structure, shape, material or disposition of the bump connectors after the connecting process of an individual bump connector
    • H01L2224/161Disposition
    • H01L2224/16151Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive
    • H01L2224/16221Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked
    • H01L2224/16225Disposition the bump connector connecting between a semiconductor or solid-state body and an item not being a semiconductor or solid-state body, e.g. chip-to-substrate, chip-to-passive the body and the item being stacked the item being non-metallic, e.g. insulating substrate with or without metallisation
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/73Means for bonding being of different types provided for in two or more of groups H01L2224/10, H01L2224/18, H01L2224/26, H01L2224/34, H01L2224/42, H01L2224/50, H01L2224/63, H01L2224/71
    • H01L2224/732Location after the connecting process
    • H01L2224/73201Location after the connecting process on the same surface
    • H01L2224/73203Bump and layer connectors
    • H01L2224/73204Bump and layer connectors the bump connector being embedded into the layer connector
    • HELECTRICITY
    • H01ELECTRIC ELEMENTS
    • H01LSEMICONDUCTOR DEVICES NOT COVERED BY CLASS H10
    • H01L2224/00Indexing scheme for arrangements for connecting or disconnecting semiconductor or solid-state bodies and methods related thereto as covered by H01L24/00
    • H01L2224/91Methods for connecting semiconductor or solid state bodies including different methods provided for in two or more of groups H01L2224/80 - H01L2224/90
    • H01L2224/92Specific sequence of method steps
    • H01L2224/921Connecting a surface with connectors of different types
    • H01L2224/9212Sequential connecting processes
    • H01L2224/92122Sequential connecting processes the first connecting process involving a bump connector
    • H01L2224/92125Sequential connecting processes the first connecting process involving a bump connector the second connecting process involving a layer connector
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/22Secondary treatment of printed circuits
    • H05K3/225Correcting or repairing of printed circuits
    • HELECTRICITY
    • H05ELECTRIC TECHNIQUES NOT OTHERWISE PROVIDED FOR
    • H05KPRINTED CIRCUITS; CASINGS OR CONSTRUCTIONAL DETAILS OF ELECTRIC APPARATUS; MANUFACTURE OF ASSEMBLAGES OF ELECTRICAL COMPONENTS
    • H05K3/00Apparatus or processes for manufacturing printed circuits
    • H05K3/30Assembling printed circuits with electric components, e.g. with resistor
    • H05K3/32Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits
    • H05K3/34Assembling printed circuits with electric components, e.g. with resistor electrically connecting electric components or wires to printed circuits by soldering
    • H05K3/341Surface mounted components
    • H05K3/3431Leadless components
    • H05K3/3436Leadless components having an array of bottom contacts, e.g. pad grid array or ball grid array components

Description

【発明の詳細な説明】DETAILED DESCRIPTION OF THE INVENTION

【0001】[0001]

【発明の属する技術分野】本発明は、フリップチップ型
半導体装置のリペア方法に係り、特に、金バンプを採用
するフリップチップ型半導体装置に好適なリペア方法に
関する。
The present invention relates to a method for repairing a flip-chip type semiconductor device, and more particularly to a repair method suitable for a flip-chip type semiconductor device employing gold bumps.

【0002】[0002]

【従来の技術】従来、フリップチップ型半導体の基板へ
の取り付けは、一般的に次の方法による。即ち、基板上
にフェイスダウンでLSIチップを実装し、基板のパッ
ド上に形成したはんだバンプをN2 雰囲気中で溶融さ
せ、基板とLSIチップを電気的に接続させる。また、
不良LSIチップを基板上から除去する場合は、当該L
SIチップを加熱し、はんだを溶融させ、LSIチップ
を引き剥がす。
2. Description of the Related Art Conventionally, a flip chip type semiconductor is generally mounted on a substrate by the following method. That is, the LSI chip is mounted face down on the substrate, the solder bumps formed on the pads of the substrate are melted in an N 2 atmosphere, and the substrate and the LSI chip are electrically connected. Also,
When removing a defective LSI chip from the substrate,
The SI chip is heated to melt the solder, and the LSI chip is peeled off.

【0003】このようなリペア方法の技術は種々開示さ
れている。例えば、LSIチップと配線基板との接続バ
ンプがはんだバンプの場合におけるリペア方法は、社団
法人SHM発行「MES’95第6回マイクロエレクト
ロニクスシンポジウム論文集」第151〜154頁や特
開平3−253049号公報(フリップチップボンディ
ングリペア方法)に開示されている。
Various techniques of such a repair method have been disclosed. For example, when a connection bump between an LSI chip and a wiring board is a solder bump, a repair method is described in "MES '95 6th Microelectronics Symposium", pages 151-154, published by SHM, and JP-A-3-253049. It is disclosed in a gazette (flip chip bonding repair method).

【0004】[0004]

【発明が解決しようとする課題】しかしながら、LSI
チップと配線基板との接続バンプが金の場合は、LSI
チップ除去後の基板に再はんだ供給することが難しいこ
とから、リペア方法が確立されていなかった。即ち、L
SIチップの除去後に、各バンプ接合部分においてはん
だの溶融濡れ状態が相違するため、斑にはんだが除去さ
れるところ、配線基板の実装用パッド上にはんだが不均
一に残り、はんだの再供給を難しくしていた。
SUMMARY OF THE INVENTION However, LSI
If the connection bump between the chip and the wiring board is gold, use LSI
The repair method has not been established because it is difficult to supply the solder again to the substrate after chip removal. That is, L
After the removal of the SI chip, the molten and wet state of the solder differs at each bump joint, so that the solder is removed at the spots, but the solder remains unevenly on the mounting pads of the wiring board, and the solder must be resupplied. It was difficult.

【0005】ここで、接続用バンプに金が使用されてい
るLSIチップの初期取り付けは、一般に、配線基板の
LSI実装用パッドに予めはんだを付与し、このはんだ
とLSIチップの金バンプを接続させて行う。この基板
側へのはんだ供給方法として、昭和電工(株)のスーパ
ージャフィット法や古川電工(株)のスーパーソルダー
法等があるが、いずれも部品実装前の配線基板において
LSI実装用パッドにはんだを供給する方法ゆえ、LS
Iチップを取り替える場合の再はんだ供給には不向きで
ある。
[0005] Here, in the initial mounting of an LSI chip in which gold is used for the connection bump, generally, solder is applied in advance to the LSI mounting pad of the wiring board, and this solder is connected to the gold bump of the LSI chip. Do it. As a method of supplying the solder to the board side, there are a Super Jafit method of Showa Denko KK and a super solder method of Furukawa Denko KK. LS
It is not suitable for re-solder supply when replacing an I chip.

【0006】[0006]

【発明の目的】本発明は、かかる従来例の有する不都合
を改善し、特に、金バンプを用いたフリップチップ型半
導体装置に好適なリペア方法を提供することを、その目
的とする。
SUMMARY OF THE INVENTION An object of the present invention is to provide a repair method suitable for a flip-chip type semiconductor device using gold bumps, which alleviates the disadvantages of the prior art.

【0007】[0007]

【課題を解決するための手段】上記目的を達成するた
め、本願では、配線基板に設けられたチップ実装用パッ
ドにフリップチップ型半導体を接合しているはんだを溶
融し上記配線基板からフリップチップ型半導体を取り外
す除去工程と、上記チップ実装用パッドにはんだを付与
するはんだ供給工程と、上記チップ実装用パッドに付与
したはんだを溶融して代替半導体を上記チップ実装用パ
ッドに接合する再取付工程とを有するフリップチップ型
半導体装置のリペア方法において、以下の方法を採って
いる。
In order to achieve the above object, in the present application, a solder bonding a flip-chip type semiconductor to a chip mounting pad provided on a wiring substrate is melted, and the flip-chip type is removed from the wiring substrate. A removing step of removing the semiconductor, a solder supplying step of applying solder to the chip mounting pad, and a reattaching step of melting the solder applied to the chip mounting pad and joining a substitute semiconductor to the chip mounting pad. In the method of repairing a flip-chip type semiconductor device having the following, the following method is employed.

【0008】請求項1記載の発明では、上記はんだ供給
工程は、上記チップ実装用パッドにフラックスを塗布す
る第1工程と、はんだフィルムから打ち抜いたはんだ片
を上記フラックスを介し上記チップ実装用パッドに付着
させる第2工程とを備えている、という方法を採ってい
る。
According to the first aspect of the present invention, the solder supply
The process is to apply flux to the chip mounting pad
The first step, the solder pieces punched from the solder film
Adhere to the chip mounting pad via the flux
And the second step of causing
You.

【0009】本発明では、はんだフィルムから打ち抜か
れた微細なはんだ片が予めチップ実装用パッドに塗布さ
れたフラックスに付着することによりチップ実装用パッ
ドに供給される。
In the present invention, a fine solder piece punched out of a solder film is supplied to a chip mounting pad by adhering to a flux previously applied to the chip mounting pad.

【0010】請求項記載の発明では、上記はんだ供給
工程は、上記配線基板とは別に設けられた熱伝導性基板
にフラックスを塗布する第1工程と、はんだフィルムか
ら打ち抜いたはんだ片を上記配線基板に設けられたチッ
プ実装用パッドの配列に対応させて上記フラックスを介
し熱伝導性基板に付着させる第2工程と、この熱伝導性
基板に付着させたはんだ片がチップ実装用パッドと接触
するように当該熱伝導性基板を上記配線基板に対向さ
せ,当該熱伝導性基板に熱を加えてはんだ片を溶融させ
る第3工程とを備えている、という方法を採っている。
本発明では、チップ実装用パッドの配置に合わせて熱伝
導性基板に付着させたはんだ片を、当該熱伝導性基板を
チップ実装用パッドの配置位置に併せて配線基板と対向
させ、複数のはんだ片を各チップ実装用パッドとおよそ
接触させた状態で溶融させることにより、チップ実装用
パッドに供給する。
[0010] In the second aspect of the present invention, the solder supply step includes a first step of applying a flux to a heat conductive substrate provided separately from the wiring substrate, and a step of applying a solder piece punched from a solder film to the wiring. A second step of attaching the chip to the thermally conductive substrate via the flux in accordance with the arrangement of the chip mounting pads provided on the substrate, and the solder pieces attached to the thermally conductive substrate contacting the chip mounting pad Thus, a third step of causing the heat conductive substrate to face the wiring substrate and applying heat to the heat conductive substrate to melt the solder pieces is provided.
In the present invention, a plurality of solder pieces attached to the heat conductive substrate in accordance with the arrangement of the chip mounting pads are opposed to the wiring board in accordance with the position of the heat conductive substrate in which the chip mounting pads are arranged. The piece is supplied to the chip mounting pads by being melted in a state of being substantially in contact with each chip mounting pad.

【0011】上記請求項記載の発明では、上記はんだ
片を溶融するときに、当該溶融箇所に向けて窒素ガスを
吹き付けるようにしても良い。これによると、チップ実
装用パッドに溶融により供給されたはんだの表面が平滑
化される。
In the second aspect of the present invention, when melting the solder piece, nitrogen gas may be blown toward the melting point. According to this, the surface of the solder supplied to the chip mounting pad by melting is smoothed.

【0012】また、上記請求項記載の発明では、上記
熱伝導性基板を上記配線基板に対向させるときに、上記
チップ実装用パッド間に当該チップ実装用パッドと上記
はんだ片とがおよそ接触する程度の厚みを有する金属板
を配置するようにしても良い。これによると、熱伝導性
基板と配線基板との間に挟まれる金属板の厚みにより、
当該熱伝導性基板と配線基板との距離が一定以上近づか
ないように保持される。
According to the second aspect of the present invention, when the heat conductive substrate is opposed to the wiring substrate, the chip mounting pad and the solder piece are almost in contact between the chip mounting pads. You may make it arrange | position a metal plate which has about a thickness. According to this, due to the thickness of the metal plate sandwiched between the heat conductive substrate and the wiring board,
The distance between the heat conductive substrate and the wiring substrate is maintained so as not to approach a certain distance or more.

【0013】これらにより前述した目的を達成しようと
するものである。
Accordingly, the above-mentioned object is achieved.

【0014】[0014]

【発明の実施の形態】BEST MODE FOR CARRYING OUT THE INVENTION

【0015】〔第1実施形態〕 以下、本発明の一実施形態を図1に基づいて説明する。[First Embodiment] An embodiment of the present invention will be described below with reference to FIG.

【0016】LSIチップは、配線基板5に取り付けた
後、図1(b)に示すように封止樹脂6で完全に接着す
るが、その前に、電気的な動作チェックを行い、LSI
の良否を判断するのが通例である。今、この判断の結果
図1(a)のLSIチップ2が不良であったとする。
After the LSI chip is mounted on the wiring board 5, the LSI chip is completely adhered with a sealing resin 6 as shown in FIG. 1 (b).
Is usually determined. Now, it is assumed that as a result of this determination, the LSI chip 2 in FIG. 1A is defective.

【0017】まず、不良LSIチップ2の除去方法につ
いて説明する。
First, a method of removing the defective LSI chip 2 will be described.

【0018】図1(a)の如く、LSI吸着加熱手段1
を不良LSIチップ2に吸着させた後、不良LSIチッ
プ2を加熱してはんだを溶融させ、不良LSI2を配線
基板5上から引き剥す。LSI吸着加熱手段1は、加熱
加圧機構を有すると共にLSIチップの吸引機構を備え
たものである。このとき、不良LSI2と配線基板5と
の接合部分4に窒素ガスを吹き付けながら不良LSIチ
ップ2を配線基板より引き剥すことを特徴とする。不良
LSIチップ2の除去は、当該不良LSIチップ2を吸
引保持したLSI吸着加熱手段1を操作して行う。
As shown in FIG. 1A, an LSI adsorption heating means 1
Is adsorbed to the defective LSI chip 2, the defective LSI chip 2 is heated to melt the solder, and the defective LSI 2 is peeled off from the wiring board 5. The LSI adsorption and heating means 1 has a heating and pressing mechanism and a suction mechanism for an LSI chip. At this time, the defective LSI chip 2 is peeled off from the wiring substrate while blowing nitrogen gas onto the joint portion 4 between the defective LSI 2 and the wiring substrate 5. The removal of the defective LSI chip 2 is performed by operating the LSI adsorption and heating means 1 which holds the defective LSI chip 2 by suction.

【0019】これによると、LSIチップ2を除去した
後、LSI実装用パッド11に残存するはんだのばらつ
きが抑制され、チップ再取付のためにLSI実装用パッ
ド11の表面を平滑化する工程を省略することができ、
リペア工程を簡略化することができる。
According to this, after the LSI chip 2 is removed, the variation in the solder remaining on the LSI mounting pad 11 is suppressed, and the step of smoothing the surface of the LSI mounting pad 11 for reattaching the chip is omitted. Can be
The repair process can be simplified.

【0020】ここで、本実施形態の更に具体的な実施例
を示せば、封止樹脂6には、エポキシ封止樹脂を用い
た。LSI吸着加熱手段1による不良LSIチップ2の
加熱は、250〜300〔℃〕とした。窒素ガスは、酸
素濃度が500ppm以下の条件で吹き付けた。
Here, as a more specific example of the present embodiment, an epoxy sealing resin is used as the sealing resin 6. Heating of the defective LSI chip 2 by the LSI adsorption and heating means 1 was performed at 250 to 300 ° C. Nitrogen gas was blown under the condition that the oxygen concentration was 500 ppm or less.

【0021】次に、代替LSIチップの取付方法を説明
する。
Next, a method of mounting the alternative LSI chip will be described.

【0022】図1(b)は、不良LSIチップ2を除去
した後の状態を示す。配線基板5上には、一組のLSI
実装用パッド11が残されている。この状態において、
まず、LSI実装用パッド11にフラックス13を層状
に塗布する。続いて、ダイス7の面上に展開した層状の
はんだフィルム8を当該ダイス7と共に実装用パッド1
1の上方に位置づけ、ポンチ9を用いてはんだフィルム
8を打ち抜く。これにより、打ち抜いた層状のはんだデ
ィスク10をLSI実装用パッド11の上層に付与する
(以下、このはんだ供給方法をマイクロプレス法とい
う。マイクロプレス法は、金属突起物の形成方法および
治具(特願平02−178854号)に記載された内容
を用いて行う方法である。)。はんだディスク10は、
LSI実装用パッド11に予め塗布したフラックス13
により当該LSI実装用パッド11に接着させる(図1
(d))。
FIG. 1B shows a state after the defective LSI chip 2 is removed. On the wiring board 5, a set of LSI
The mounting pad 11 is left. In this state,
First, a flux 13 is applied to the LSI mounting pad 11 in a layered manner. Subsequently, the layered solder film 8 spread on the surface of the die 7 is mounted together with the die 7 on the mounting pad 1.
1 and punched out the solder film 8 using a punch 9. In this way, the punched layered solder disk 10 is applied to the upper layer of the LSI mounting pad 11 (hereinafter, this solder supply method is referred to as a micro press method. The micro press method is a method for forming a metal projection and a jig (special method). No. 02-178854).) The solder disk 10
Flux 13 previously applied to LSI mounting pad 11
To the LSI mounting pad 11 (FIG. 1).
(D)).

【0023】続いて、図1(e)の如く、新しい代替L
SIチップ12をLSI吸着加熱手段1に吸着させ、L
SI実装用パット11の上方にて位置合わせを行う。そ
して、LSI吸着加熱手段1を所定温度に加熱して新し
いLSIチップ12を昇温させた後、配線基板5に加圧
してはんだディスク10を溶融させる。これにより、新
しいLSIチップ12とLSI実装用パッド11とを接
合する。その後、図1(f)の如く封止樹脂6で接着固
定する。
Subsequently, as shown in FIG.
The SI chip 12 is adsorbed by the LSI adsorption heating means 1 and
Positioning is performed above the SI mounting pad 11. Then, the LSI adsorption and heating means 1 is heated to a predetermined temperature to raise the temperature of the new LSI chip 12, and then the wiring board 5 is pressed to melt the solder disk 10. Thus, the new LSI chip 12 and the LSI mounting pad 11 are joined. After that, as shown in FIG.

【0024】これによると、チップ再取付位置の周囲に
既に実装された部品があるときでも、LSI実装用パッ
ド11に対応した所望の位置にはんだディスク10を供
給することができ、リペア作業の容易化を図ることがで
きる。
According to this, even when there is a component already mounted around the chip re-attachment position, the solder disk 10 can be supplied to a desired position corresponding to the LSI mounting pad 11, thereby facilitating repair work. Can be achieved.

【0025】ここで、本実施形態の更に具体的な実施例
を示せば、フラックス13は、比較的粘着性が高いもの
が望ましいことから、千住金属製デルタラックス527
−7を用いた。はんだフィルム8には50〔μm〕厚の
錫銀はんだを用い、これを打ち抜いて直径80〔μm〕
の錫銀はんだディスク10を形成した。LSI吸着加圧
手段1の加熱は、250〜300℃とした。LSIチッ
プ12は、配線基板5に0.5kgで加圧した。このと
き、LSIチップ12と配線基板5との隙間に窒素ガス
を吹き付け、酸素濃度を500ppm以下とした。
Here, if a more specific example of the present embodiment is shown, it is desirable that the flux 13 has a relatively high adhesiveness. Therefore, the Deltalux 527 made by Senju Metal Co., Ltd.
-7 was used. A tin-silver solder having a thickness of 50 [μm] is used for the solder film 8 and is punched out to a diameter of 80 [μm].
A tin-silver solder disk 10 was formed. The heating of the LSI adsorption and pressurizing means 1 was set at 250 to 300 ° C. The LSI chip 12 was pressed against the wiring board 5 at 0.5 kg. At this time, nitrogen gas was blown into the gap between the LSI chip 12 and the wiring board 5 to reduce the oxygen concentration to 500 ppm or less.

【0026】〔第2実施形態〕 次に、本発明の第2実施形態を図2に基づいて説明す
る。本実施形態は、不良LSIチップを除去した後、代
替LSIチップを取り付ける前における、LSI実装用
パッドへのはんだ供給工程に特徴を有する。以下、この
はんだ供給工程を説明する。
[Second Embodiment] Next, a second embodiment of the present invention will be described with reference to FIG. This embodiment is characterized in a process of supplying solder to the pads for mounting the LSI before removing the defective LSI chip and before attaching the replacement LSI chip. Hereinafter, this solder supply step will be described.

【0027】図2(a)は、第1実施形態と同一のLS
Iチップ除去工程により、不良LSIチップを配線基板
5上から除去した状態を示す。まず、図2(b)に示す
ように、配線基板5とは別に準備したセラミックス基板
14にフラックス13を塗布する。続いて、このセラミ
ックス基板14上に、配線基板5上に配置されたLSI
実装用パッド11の位置と対応させて、マイクロプレス
法によりはんだディスク10を付与し、フラックス13
に接着させる。
FIG. 2A shows the same LS as in the first embodiment.
This shows a state in which a defective LSI chip has been removed from above the wiring board 5 by the I chip removal step. First, as shown in FIG. 2B, a flux 13 is applied to a ceramic substrate 14 prepared separately from the wiring substrate 5. Subsequently, on the ceramic substrate 14, the LSI disposed on the wiring substrate 5 is used.
The solder disk 10 is applied by a micro-press method in correspondence with the position of the mounting pad 11, and the flux 13
Adhere to.

【0028】その後、図2(c)の如く、セラミックス
基板14のはんだディスク10が接着されていない面を
LSI吸着加熱手段1に吸着させ、はんだディスク10
とLSI実装用パッド11とが向かい合うように配線基
板5と対向させる。そして、LSI実装用パッド11と
はんだディスク10との位置合わせを行い、LSI吸着
加熱手段1を下降させ、はんだディスク10とLSI実
装パッド11とを接触させる。この状態でLSI吸着加
熱手段1を加熱すると共に、配線基板5側に加圧し、は
んだディスク10を溶融させる。これにより、図2
(d)の如く、LSI実装用パッド11にはんだディス
ク10が転写され、LSI実装用パッド11にはんだが
供給される。
Thereafter, as shown in FIG. 2C, the surface of the ceramic substrate 14 to which the solder disk 10 is not bonded is sucked by the LSI suction and heating means 1 and
And the LSI mounting pad 11 are opposed to the wiring board 5 so as to face each other. Then, the LSI mounting pad 11 and the solder disk 10 are aligned, and the LSI suction and heating means 1 is lowered to bring the solder disk 10 into contact with the LSI mounting pad 11. In this state, the LSI suction heating means 1 is heated, and at the same time, pressure is applied to the wiring board 5 side to melt the solder disk 10. As a result, FIG.
As shown in (d), the solder disk 10 is transferred to the LSI mounting pad 11, and the solder is supplied to the LSI mounting pad 11.

【0029】これによると、セラミックス基板14に付
着させた複数のはんだディスク10の配置位置を確認し
た後で複数のはんだディスク10を一度に精度良く各L
SI実装用パッド11に供給することができ、チップの
再取付位置の周囲に既に実装された部品が密集している
状況にあっても、はんだ供給を容易に行うことができ
る。また、はんだの溶融時に接合部分に窒素ガスを吹き
付けても良い。これによりLSI実装用パッド11側に
転写されたはんだの表面を平滑化することができる。
According to this, after confirming the arrangement position of the plurality of solder disks 10 attached to the ceramic substrate 14, each of the plurality of solder disks 10
The solder can be supplied to the SI mounting pad 11, and the solder can be easily supplied even in a situation where the already mounted components are densely packed around the chip reattachment position. Further, a nitrogen gas may be blown to the joint portion when the solder is melted. Thereby, the surface of the solder transferred to the LSI mounting pad 11 side can be smoothed.

【0030】ここで、本実施形態の更に具体的な実施例
を示せば、セラミックス基板14は0.3〔mm〕厚と
した。本実施形態で使用するセラミックス基板14に
は、熱伝導率の良い窒化アルミ基板が好適である。フラ
ックス13は、第1実施形態と同様にデルタラックス5
27−7を使用した。マイクロプレス法により形成する
はんだディスク10は錫銀はんだで直径80〔μm〕と
した。LSI加熱加圧手段1による加熱は250〜30
0〔℃〕とした
Here, as a more specific example of the present embodiment, the ceramic substrate 14 was 0.3 [mm] thick. As the ceramic substrate 14 used in the present embodiment, an aluminum nitride substrate having good thermal conductivity is preferable. The flux 13 is made of Deltalux 5 similarly to the first embodiment.
27-7 was used. The solder disk 10 formed by the micropress method was made of tin silver solder and had a diameter of 80 [μm]. Heating by the LSI heating and pressing means 1 is 250 to 30
Was 0 [℃].

【0031】〔第3実施形態〕 次に、本発明の第3実施形態を図3に基づいて説明す
る。本実施形態は、第2実施形態と同様にLSI実装用
パッド11へのはんだ供給工程に特徴を有し、特に、微
細なピッチLSI実装用パッドにはんだを再供給する方
法に関する。以下、はんだの供給工程について説明す
る。
[Third Embodiment] Next, a third embodiment of the present invention will be described with reference to FIG. This embodiment has a feature in the step of supplying solder to the LSI mounting pads 11 as in the second embodiment, and particularly relates to a method of re-supplying solder to fine pitch LSI mounting pads. Hereinafter, the solder supply step will be described.

【0032】図3(a)は、第1実施形態と同一のLS
Iチップ除去方法により、不良LSIチップを配線基板
5上から除去した状態を示す。まず、図3(a)に示す
ように、LSI実装用パッド11の間に当該LSI実装
用パッド11よりも厚い金属平板15を配置する。続い
て第2実施形態と同様に、セラミックス基板14にフラ
ックス13を塗布した後、はんだディスク10を接着さ
せる(図3(b))。更に、第2実施形態と同様に、L
SI吸着加熱手段1に保持させたセラミックス基板14
を配線基板5と対向させ、はんだディスク10とLSI
実装用パッド11とが接触するまでLSI吸着加熱手段
1を下降させる(図3(c))。そして、LSI吸着加
熱手段1の加熱・加圧により、はんだディスク10をL
SI実装用パッド11に転写する(図3(d))。
FIG. 3A shows the same LS as in the first embodiment.
The state where the defective LSI chip is removed from the wiring substrate 5 by the I chip removal method is shown. First, as shown in FIG. 3A, a metal flat plate 15 thicker than the LSI mounting pad 11 is arranged between the LSI mounting pads 11. Subsequently, similarly to the second embodiment, after applying the flux 13 to the ceramic substrate 14, the solder disk 10 is bonded (FIG. 3B). Further, as in the second embodiment, L
Ceramic substrate 14 held by SI adsorption heating means 1
Is opposed to the wiring board 5, and the solder disk 10 and the LSI
The LSI suction heating means 1 is lowered until the mounting pads 11 come into contact with the mounting pads 11 (FIG. 3C). Then, the heating and pressurization of the LSI adsorption and heating means 1 causes the solder disk 10 to
The image is transferred to the SI mounting pad 11 (FIG. 3D).

【0033】このとき、セラミックス基板14と配線基
板5との間に挟まれる金属板15の厚みにより、当該セ
ラミックス基板14と配線基板5との距離が一定以上近
づかないように保持されるので、微細なピッチのLSI
実装用パッド11上に転写されたはんだディスク10を
必要以上に変形させずに保持することができる。また、
はんだの溶融時に接合部分に窒素ガスを吹き付けても良
い。これによりLSI実装用パッド11側に転写された
はんだの表面を平滑化することができる。
At this time, the thickness of the metal plate 15 sandwiched between the ceramic substrate 14 and the wiring substrate 5 keeps the distance between the ceramic substrate 14 and the wiring substrate 5 from approaching a certain value or more. High pitch LSI
The solder disk 10 transferred onto the mounting pads 11 can be held without being deformed more than necessary. Also,
Nitrogen gas may be blown to the joint when the solder is melted. Thereby, the surface of the solder transferred to the LSI mounting pad 11 side can be smoothed.

【0034】ここで、本実施形態の更に具体的な実施例
を示せば、上記実施形態は、LSI実装用パッド11の
ピッチが120〔μm〕以下と微細であるときに特に有
効である。また、金属平板15には、厚みが30〔μ
m〕のステンレス板を用いた。セラミックス基板14に
は、窒化アルミ基板(アルミナ基板)を用いた。フラッ
クス13には、第1実施形態と同様にデルタラックス5
27−7を用いた。はんだディスク10は、錫銀はんだ
で直径80〔μm〕としたが、はんだディスク10の径
と厚みは、LSI実装用パッド11の面積により変更す
る必要がある。LSI吸着加熱手段1の加熱は250〜
300〔℃〕とし、加圧は0.5〜1.0〔kg〕とし
た。
Here, a more specific example of this embodiment will be described. The above embodiment is particularly effective when the pitch of the LSI mounting pad 11 is as fine as 120 [μm] or less. The metal plate 15 has a thickness of 30 [μ
m]. As the ceramic substrate 14, an aluminum nitride substrate (alumina substrate) was used. The flux 13 has a Deltalux 5 as in the first embodiment.
27-7 was used. The diameter of the solder disk 10 is 80 [μm] using tin-silver solder. However, the diameter and thickness of the solder disk 10 need to be changed according to the area of the LSI mounting pad 11. The heating of the LSI adsorption heating means 1 is 250 to
The temperature was 300 ° C., and the pressure was 0.5 to 1.0 kg.

【0035】以上説明した各実施形態は、金バンプを用
いたフリップチップ型半導体装置のリペアに特に好適で
ある。
The embodiments described above are particularly suitable for repairing flip-chip type semiconductor devices using gold bumps.

【0036】ここで、上記各実施形態において、チップ
の再取付工程が終了した後は、フラックスの洗浄工程を
実行すれば良い。窒素ガスの吹き付けは、接合部分に対
し相対向する2方向又は4方向から行っても良い。これ
によると、はんだ面が特に均一に斑なく平滑化される。
金属板は、20〜50〔μm〕厚に設定すると良い。
Here, in each of the above embodiments, after the chip reattachment step is completed, a flux cleaning step may be performed. Spraying of the nitrogen gas may be performed from two directions or four directions facing each other with respect to the joint portion. According to this, the solder surface is particularly uniformly smoothed without unevenness.
The metal plate is preferably set to have a thickness of 20 to 50 [μm].

【0037】[0037]

【発明の効果】本発明は、以上のように構成され機能す
るので
Since the present invention is constructed and functions as described above ,

【0038】請求項記載の発明では、はんだディスク
から打ち抜いたはんだ片をチップ実装用ディスクに供給
するので、チップ再取付位置の周囲に既に実装された部
品があるときでも、チップ実装用パッドに対応した所望
の位置にはんだ片を供給することができ、リペア作業の
容易化を図ることができる。
According to the first aspect of the present invention, since the solder pieces punched out from the solder disk are supplied to the chip mounting disk, even when there are already mounted components around the chip re-attachment position, the chip mounting pads can be used. The solder pieces can be supplied to the corresponding desired positions, and the repair work can be facilitated.

【0039】請求項記載の発明では、一度熱伝導性基
板の所定位置に付着させたはんだ片を配線基板のチップ
実装用パッドに転写するので、熱伝導性基板に付着させ
た複数のはんだ片の配置位置を確認した後で複数のはん
だ片を一度に精度良く各チップ実装用パッドに供給する
ことができ、チップの再取付位置の周囲に既に実装され
た部品が密集している状況にあっても、はんだ供給を容
易に行うことができる。
According to the second aspect of the present invention, since the solder pieces once adhered to the predetermined position on the heat conductive substrate are transferred to the chip mounting pads of the wiring board, the plurality of solder pieces adhered to the heat conductive substrate are transferred. After confirming the placement position of the chip, multiple solder pieces can be supplied to each chip mounting pad with high precision at once, and in a situation where the already mounted components are densely packed around the chip re-attachment position. However, it is possible to easily supply the solder.

【0040】請求項記載の発明では、はんだの溶融時
に接合部分に窒素ガスを吹き付けることにより、チップ
実装用パッド側に転写されたはんだの表面を平滑化する
ことができ、チップの再取付を容易に行うことができ
る。
According to the third aspect of the present invention, the surface of the solder transferred to the chip mounting pad side can be smoothed by blowing a nitrogen gas to the joint portion when the solder is melted, and the chip can be reattached. It can be done easily.

【0041】請求項記載の発明では、熱伝導性基板と
配線基板との間に所定厚さの金属板を配置するので、熱
伝導性基板と配線基板との間に挟まれる金属板の厚みに
より、当該熱伝導性基板と配線基板との距離が一定以上
近づかないように保持され、微細なピッチのチップ実装
用パッド上に転写されたはんだ片を必要以上に変形させ
ずに保持することができる。従って、微細ピッチのチッ
プ実装用パッドを採用するフリップチップ型半導体装置
のリペア作業を容易にすることができる。
According to the fourth aspect of the present invention, since the metal plate having a predetermined thickness is arranged between the heat conductive substrate and the wiring substrate, the thickness of the metal plate sandwiched between the heat conductive substrate and the wiring substrate is reduced. Thereby, the distance between the heat conductive substrate and the wiring substrate is held so as not to be closer than a certain value, and the solder pieces transferred onto the fine pitch chip mounting pads can be held without being deformed more than necessary. it can. Therefore, the repair work of the flip chip type semiconductor device employing the fine pitch chip mounting pads can be facilitated.

【0042】本発明は、金バンプを用いたフリップチッ
プ型半導体装置のリペアに特に有効であり、従来であれ
ば再はんだ供給ができないためにリペアできず廃棄して
いた金バンプ採用のフリップチップ型半導体装置をリペ
ア可能となり、フリップチップ型半導体装置の歩留まり
を向上できると共に産業廃棄物の削減にも寄与するとい
う従来にない優れたフリップチップ型半導体装置のリペ
ア方法を提供することができる。
The present invention is particularly effective for repairing a flip-chip type semiconductor device using gold bumps. A flip-chip type employing gold bumps which could not be repaired and discarded because re-solder could not be supplied in the past. It is possible to provide an unprecedented method of repairing a flip-chip type semiconductor device which can repair the semiconductor device, improve the yield of the flip-chip type semiconductor device and contribute to the reduction of industrial waste.

【図面の簡単な説明】[Brief description of the drawings]

【図1】本発明の第1実施形態におけるリペア工程の流
れを示す状態図であり、図1(a)は不良チップを取り
外す前、図1(b)は不良チップを取り外した後、図1
(c)ははんだ供給工程、図1(d)ははんだ供給後、
図1(e)はチップの再取付、図1(f)はチップの再
取付後、の状態をそれぞれ示す。
FIG. 1 is a state diagram showing a flow of a repair process according to a first embodiment of the present invention. FIG. 1A shows a state before a defective chip is removed, and FIG.
(C) is a solder supply step, and FIG.
FIG. 1E shows the state after reattachment of the chip, and FIG. 1F shows the state after reattachment of the chip.

【図2】本発明の第2実施形態におけるはんだ供給工程
の流れを示す状態図であり、図2(a)は不良チップ取
り外し後、図2(b)は熱伝導性基板へのはんだ片供
給、図2(c)は熱伝導性基板から配線基板へのはんだ
片の転写、図2(d)ははんだ片の転写後、の状態をそ
れぞれ示す。
FIG. 2 is a state diagram showing a flow of a solder supply step in a second embodiment of the present invention. FIG. 2 (a) shows a state after a defective chip is removed, and FIG. FIG. 2C shows the state after the transfer of the solder piece from the heat conductive substrate to the wiring board, and FIG. 2D shows the state after the transfer of the solder piece.

【図3】本発明の第3実施形態におけるはんだ供給工程
の流れを示す状態図であり、図3(a)は不良チップ取
り外し後の金属板の配置、図3(b)は熱伝導性基板へ
のはんだ片供給、図3(c)は熱伝導性基板から配線基
板へのはんだ片の転写、図3(d)ははんだ片の転写
後、の状態をそれぞれ示す。
FIG. 3 is a state diagram showing a flow of a solder supply step according to a third embodiment of the present invention. FIG. 3 (a) is an arrangement of a metal plate after a defective chip is removed, and FIG. 3 (b) is a heat conductive substrate. FIG. 3 (c) shows a state after the solder piece is transferred from the heat conductive substrate to the wiring board, and FIG. 3 (d) shows a state after the solder piece is transferred.

【符号の説明】[Explanation of symbols]

1 吸着加熱手段 2 不良LSIチップ 3 良品LSIチップ 4 LSIチップと配線基板とのはんだ接続部 5 配線基板 6 封止樹脂 7 ポンチ 8 はんだフィルム 9 ダイス 10 はんだディスク(はんだ片) 11 LSI実装用パッド(チップ実装用パッド) 12 新しいLSIチップ(代替半導体) 13 フラックス 14 セラミックス基板(熱伝導性基板) 15 金属板 DESCRIPTION OF SYMBOLS 1 Adsorption heating means 2 Defective LSI chip 3 Non-defective LSI chip 4 Solder connection part between LSI chip and wiring board 5 Wiring board 6 Sealing resin 7 Punch 8 Solder film 9 Dice 10 Solder disk (solder piece) 11 LSI mounting pad ( Chip mounting pad) 12 New LSI chip (alternative semiconductor) 13 Flux 14 Ceramic substrate (thermally conductive substrate) 15 Metal plate

Claims (4)

(57)【特許請求の範囲】(57) [Claims] 【請求項1】 配線基板に設けられたチップ実装用パッ
ドにフリップチップ型半導体を接合しているはんだを溶
融し前記配線基板からフリップチップ型半導体を取り外
す除去工程と、前記チップ実装用パッドにはんだを付与
するはんだ供給工程と、前記チップ実装用パッドに付与
したはんだを溶融して代替半導体を前記チップ実装用パ
ッドに接合する再取付工程とを有するフリップチップ型
半導体装置のリペア方法において、 前記はんだ供給工程は、前記チップ実装用パッドにフラ
ックスを塗布する第1工程と、はんだフィルムから打ち
抜いたはんだ片を前記フラックスを介し前記チップ実装
用パッドに付着させる第2工程とを備えていることを特
徴としたフリップチップ型半導体装置のリペア方法。
A package for chip mounting provided on a wiring board.
Melt the solder joining the flip-chip type semiconductor
Remove the flip-chip type semiconductor from the wiring board
Removal process and applying solder to the chip mounting pad
Solder supply process to be applied and applied to the chip mounting pad
After melting the solder, substitute semiconductor
Chip type having a reattaching step of joining to a pad
In the method of repairing a semiconductor device, the solder supply step may include flushing the chip mounting pad.
The first step of applying the soldering and punching from the solder film
Mounting the chip with the removed solder piece via the flux
And a second step of adhering to the pad for use.
A method for repairing a flip-chip type semiconductor device.
【請求項2】 配線基板に設けられたチップ実装用パッ
ドにフリップチップ型半導体を接合しているはんだを溶
融し前記配線基板からフリップチップ型半導体を取り外
す除去工程と、前記チップ実装用パッドにはんだを付与
するはんだ供給工程と、前記チップ実装用パッドに付与
したはんだを溶融して代替半導体を前記チップ実装用パ
ッドに接合する再取付工程とを有するフリップチップ型
半導体装置のリペア方法において、 前記はんだ供給工程は、前記配線基板とは別に設けられ
た熱伝導性基板にフラックスを塗布する第1工程と、は
んだフィルムから打ち抜いたはんだ片を前記配線基板に
設けられたチップ実装用パッドの配列に対応させて前記
フラックスを介し熱伝導性基板に付着させる第2工程
と、この熱伝導性基板に付着させたはんだ片がチップ実
装用パッドと接触するように当該熱伝導性基板を前記配
線基板に対向させ,当該熱伝導性基板に熱を加えてはん
だ片を溶融させる第3工程とを備えていることを特徴と
したフリップチップ型半導体装置のリペア方法。
2. A chip mounting package provided on a wiring board.
Melt the solder joining the flip-chip type semiconductor
Remove the flip-chip type semiconductor from the wiring board
Removal process and applying solder to the chip mounting pad
Solder supply process to be applied and applied to the chip mounting pad
After melting the solder, substitute semiconductor
Chip type having a reattaching step of joining to a pad
In the method for repairing a semiconductor device, the solder supply step is provided separately from the wiring board.
The first step of applying flux to the thermally conductive substrate,
Solder pieces punched from solder film are applied to the wiring board
According to the arrangement of the provided chip mounting pads,
Second step of attaching to the heat conductive substrate via the flux
And the solder pieces attached to the heat conductive substrate
The heat conductive substrate so as to be in contact with the mounting pad.
The heat conductive substrate is heated by applying heat to the heat conductive substrate.
And a third step of melting the piece.
Repair method for a flip-chip type semiconductor device.
【請求項3】 前記はんだ片を溶融するときに、当該溶
融箇所に向けて窒素ガスを吹き付けることを特徴とした
請求項2記載のフリップチップ型半導体装置のリペア方
法。
3. When the solder piece is melted,
It is characterized by blowing nitrogen gas toward the melting point
A method of repairing the flip-chip type semiconductor device according to claim 2.
Law.
【請求項4】 前記熱伝導性基板を前記配線基板に対向
させるときに、前記チップ実装用パッド間に当該チップ
実装用パッドと前記はんだ片とがおよそ接触する程度の
厚みを有する金属板を配置することを特徴とした請求項
2記載のフリップチップ型半導体装置のリペア方法。
4. The heat conductive substrate is opposed to the wiring substrate.
When the chip is mounted between the chip mounting pads.
The mounting pad and the solder piece are in contact with each other.
A metal plate having a thickness is arranged.
3. The method for repairing a flip-chip type semiconductor device according to item 2.
JP8176331A 1996-07-05 1996-07-05 Repair method for flip-chip type semiconductor device Expired - Fee Related JP2812304B2 (en)

Priority Applications (1)

Application Number Priority Date Filing Date Title
JP8176331A JP2812304B2 (en) 1996-07-05 1996-07-05 Repair method for flip-chip type semiconductor device

Applications Claiming Priority (1)

Application Number Priority Date Filing Date Title
JP8176331A JP2812304B2 (en) 1996-07-05 1996-07-05 Repair method for flip-chip type semiconductor device

Publications (2)

Publication Number Publication Date
JPH1022340A JPH1022340A (en) 1998-01-23
JP2812304B2 true JP2812304B2 (en) 1998-10-22

Family

ID=16011729

Family Applications (1)

Application Number Title Priority Date Filing Date
JP8176331A Expired - Fee Related JP2812304B2 (en) 1996-07-05 1996-07-05 Repair method for flip-chip type semiconductor device

Country Status (1)

Country Link
JP (1) JP2812304B2 (en)

Families Citing this family (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JP4036555B2 (en) 1999-01-14 2008-01-23 松下電器産業株式会社 Mounting structure manufacturing method and mounting structure
CN113130714B (en) * 2021-04-13 2022-10-14 东莞市中麒光电技术有限公司 LED device repairing method

Family Cites Families (2)

* Cited by examiner, † Cited by third party
Publication number Priority date Publication date Assignee Title
JPH05243288A (en) * 1992-03-02 1993-09-21 Sharp Corp Repair method for semiconductor device
JPH0936536A (en) * 1995-07-19 1997-02-07 Nippon Bonkooto Kk Bga repair device

Also Published As

Publication number Publication date
JPH1022340A (en) 1998-01-23

Similar Documents

Publication Publication Date Title
JP3663938B2 (en) Flip chip mounting method
US5813115A (en) Method of mounting a semiconductor chip on a wiring substrate
JP5066935B2 (en) Method for manufacturing electronic component and electronic device
JP3269390B2 (en) Semiconductor device
JPH10284535A (en) Method for producing semiconductor device and semiconductor component
JP2812304B2 (en) Repair method for flip-chip type semiconductor device
JPH0645740A (en) Solder connecting method
JP2000208547A (en) Bump reinforcing structure and its forming method in semiconductor device
JPH01209736A (en) Method of replacing semiconductor element
JP3235192B2 (en) Wiring board connection method
JP2001156441A (en) Method for repairing csp/bga
JPH11135561A (en) Anisotropic conductive adhesive film, its manufacture, flip-chip mounting method, and flip-chip packaging board
JP4214127B2 (en) Flip chip mounting method
JP3445687B2 (en) Mounting method of semiconductor chip
JPH1022344A (en) Bonding method for work with bumps
JPH07201894A (en) Manufacture of electronic parts mounting device
JPH04343239A (en) Bonding tool
JP2591600B2 (en) Bonding method
JP3061017B2 (en) Mounting structure of integrated circuit device and mounting method thereof
JP3284890B2 (en) Bonding method of work with bump
JPS6297341A (en) Bonding device
JP3548671B2 (en) Semiconductor device and manufacturing method thereof
JPH09214128A (en) Bonding tool
JPH08139138A (en) Connection method of electronic device
JPH08148491A (en) Forming method of connection electrode

Legal Events

Date Code Title Description
A01 Written decision to grant a patent or to grant a registration (utility model)

Free format text: JAPANESE INTERMEDIATE CODE: A01

Effective date: 19980707

LAPS Cancellation because of no payment of annual fees